1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright 2020-2021, 2023-2024 NXP 4 */ 5 #ifndef S32CC_CLK_REGS_H 6 #define S32CC_CLK_REGS_H 7 8 #include <lib/utils_def.h> 9 10 #define FXOSC_BASE_ADDR (0x40050000UL) 11 #define ARMPLL_BASE_ADDR (0x40038000UL) 12 #define CGM1_BASE_ADDR (0x40034000UL) 13 14 /* FXOSC */ 15 #define FXOSC_CTRL(FXOSC) ((FXOSC) + 0x0UL) 16 #define FXOSC_CTRL_OSC_BYP BIT_32(31U) 17 #define FXOSC_CTRL_COMP_EN BIT_32(24U) 18 #define FXOSC_CTRL_EOCV_OFFSET 16U 19 #define FXOSC_CTRL_EOCV_MASK GENMASK_32(23U, FXOSC_CTRL_EOCV_OFFSET) 20 #define FXOSC_CTRL_EOCV(VAL) (FXOSC_CTRL_EOCV_MASK & \ 21 ((uint32_t)(VAL) << FXOSC_CTRL_EOCV_OFFSET)) 22 #define FXOSC_CTRL_GM_SEL_OFFSET 4U 23 #define FXOSC_CTRL_GM_SEL_MASK GENMASK_32(7U, FXOSC_CTRL_GM_SEL_OFFSET) 24 #define FXOSC_CTRL_GM_SEL(VAL) (FXOSC_CTRL_GM_SEL_MASK & \ 25 ((uint32_t)(VAL) << FXOSC_CTRL_GM_SEL_OFFSET)) 26 #define FXOSC_CTRL_OSCON BIT_32(0U) 27 28 #define FXOSC_STAT(FXOSC) ((FXOSC) + 0x4UL) 29 #define FXOSC_STAT_OSC_STAT BIT_32(31U) 30 31 /* PLL */ 32 #define PLLDIG_PLLCR(PLL) ((PLL) + 0x0UL) 33 #define PLLDIG_PLLCR_PLLPD BIT_32(31U) 34 35 #define PLLDIG_PLLSR(PLL) ((PLL) + 0x4UL) 36 #define PLLDIG_PLLSR_LOCK BIT_32(2U) 37 38 #define PLLDIG_PLLDV(PLL) ((PLL) + 0x8UL) 39 #define PLLDIG_PLLDV_RDIV_OFFSET 12U 40 #define PLLDIG_PLLDV_RDIV_MASK GENMASK_32(14U, PLLDIG_PLLDV_RDIV_OFFSET) 41 #define PLLDIG_PLLDV_RDIV_SET(VAL) (PLLDIG_PLLDV_RDIV_MASK & \ 42 ((VAL) << PLLDIG_PLLDV_RDIV_OFFSET)) 43 #define PLLDIG_PLLDV_MFI_MASK GENMASK_32(7U, 0U) 44 #define PLLDIG_PLLDV_MFI(DIV) (PLLDIG_PLLDV_MFI_MASK & (DIV)) 45 46 #define PLLDIG_PLLFD(PLL) ((PLL) + 0x10UL) 47 #define PLLDIG_PLLFD_SMDEN BIT_32(30U) 48 #define PLLDIG_PLLFD_MFN_MASK GENMASK_32(14U, 0U) 49 #define PLLDIG_PLLFD_MFN_SET(VAL) (PLLDIG_PLLFD_MFN_MASK & (VAL)) 50 51 #define PLLDIG_PLLCLKMUX(PLL) ((PLL) + 0x20UL) 52 53 #define PLLDIG_PLLODIV(PLL, N) ((PLL) + 0x80UL + ((N) * 0x4UL)) 54 #define PLLDIG_PLLODIV_DE BIT_32(31U) 55 #define PLLDIG_PLLODIV_DIV_OFFSET 16U 56 #define PLLDIG_PLLODIV_DIV_MASK GENMASK_32(23U, PLLDIG_PLLODIV_DIV_OFFSET) 57 #define PLLDIG_PLLODIV_DIV(VAL) (((VAL) & PLLDIG_PLLODIV_DIV_MASK) >> \ 58 PLLDIG_PLLODIV_DIV_OFFSET) 59 #define PLLDIG_PLLODIV_DIV_SET(VAL) (PLLDIG_PLLODIV_DIV_MASK & ((VAL) << \ 60 PLLDIG_PLLODIV_DIV_OFFSET)) 61 62 /* MMC_CGM */ 63 #define CGM_MUXn_CSC(CGM_ADDR, MUX) ((CGM_ADDR) + 0x300UL + ((MUX) * 0x40UL)) 64 #define MC_CGM_MUXn_CSC_SELCTL_OFFSET 24U 65 #define MC_CGM_MUXn_CSC_SELCTL_MASK GENMASK_32(29U, MC_CGM_MUXn_CSC_SELCTL_OFFSET) 66 #define MC_CGM_MUXn_CSC_SELCTL(val) (MC_CGM_MUXn_CSC_SELCTL_MASK & ((val) \ 67 << MC_CGM_MUXn_CSC_SELCTL_OFFSET)) 68 #define MC_CGM_MUXn_CSC_CLK_SW BIT_32(2U) 69 #define MC_CGM_MUXn_CSC_SAFE_SW BIT_32(3U) 70 71 #define CGM_MUXn_CSS(CGM_ADDR, MUX) ((CGM_ADDR) + 0x304UL + ((MUX) * 0x40UL)) 72 #define MC_CGM_MUXn_CSS_SELSTAT_OFFSET 24U 73 #define MC_CGM_MUXn_CSS_SELSTAT_MASK GENMASK_32(29U, MC_CGM_MUXn_CSS_SELSTAT_OFFSET) 74 #define MC_CGM_MUXn_CSS_SELSTAT(css) ((MC_CGM_MUXn_CSS_SELSTAT_MASK & (css))\ 75 >> MC_CGM_MUXn_CSS_SELSTAT_OFFSET) 76 #define MC_CGM_MUXn_CSS_SWTRG(css) ((MC_CGM_MUXn_CSS_SWTRG_MASK & (css)) \ 77 >> MC_CGM_MUXn_CSS_SWTRG_OFFSET) 78 #define MC_CGM_MUXn_CSS_SWTRG_OFFSET 17U 79 #define MC_CGM_MUXn_CSS_SWTRG_MASK GENMASK_32(19U, MC_CGM_MUXn_CSS_SWTRG_OFFSET) 80 #define MC_CGM_MUXn_CSS_SWTRG_SUCCESS 0x1U 81 #define MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK 0x4U 82 #define MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK_INACTIVE 0x5U 83 #define MC_CGM_MUXn_CSS_SWIP BIT_32(16U) 84 #define MC_CGM_MUXn_CSS_SAFE_SW BIT_32(3U) 85 86 #endif /* S32CC_CLK_REGS_H */ 87