1*8ab34357SGhennadi Procopciuc // SPDX-License-Identifier: BSD-3-Clause 2*8ab34357SGhennadi Procopciuc /* 3*8ab34357SGhennadi Procopciuc * Copyright 2020-2021, 2023-2024 NXP 4*8ab34357SGhennadi Procopciuc */ 5*8ab34357SGhennadi Procopciuc #ifndef S32CC_CLK_REGS_H 6*8ab34357SGhennadi Procopciuc #define S32CC_CLK_REGS_H 7*8ab34357SGhennadi Procopciuc 8*8ab34357SGhennadi Procopciuc #include <lib/utils_def.h> 9*8ab34357SGhennadi Procopciuc 10*8ab34357SGhennadi Procopciuc #define FXOSC_BASE_ADDR (0x40050000UL) 11*8ab34357SGhennadi Procopciuc 12*8ab34357SGhennadi Procopciuc /* FXOSC */ 13*8ab34357SGhennadi Procopciuc #define FXOSC_CTRL(FXOSC) ((FXOSC) + 0x0UL) 14*8ab34357SGhennadi Procopciuc #define FXOSC_CTRL_OSC_BYP BIT_32(31U) 15*8ab34357SGhennadi Procopciuc #define FXOSC_CTRL_COMP_EN BIT_32(24U) 16*8ab34357SGhennadi Procopciuc #define FXOSC_CTRL_EOCV_OFFSET 16U 17*8ab34357SGhennadi Procopciuc #define FXOSC_CTRL_EOCV_MASK GENMASK_32(23U, FXOSC_CTRL_EOCV_OFFSET) 18*8ab34357SGhennadi Procopciuc #define FXOSC_CTRL_EOCV(VAL) (FXOSC_CTRL_EOCV_MASK & \ 19*8ab34357SGhennadi Procopciuc ((uint32_t)(VAL) << FXOSC_CTRL_EOCV_OFFSET)) 20*8ab34357SGhennadi Procopciuc #define FXOSC_CTRL_GM_SEL_OFFSET 4U 21*8ab34357SGhennadi Procopciuc #define FXOSC_CTRL_GM_SEL_MASK GENMASK_32(7U, FXOSC_CTRL_GM_SEL_OFFSET) 22*8ab34357SGhennadi Procopciuc #define FXOSC_CTRL_GM_SEL(VAL) (FXOSC_CTRL_GM_SEL_MASK & \ 23*8ab34357SGhennadi Procopciuc ((uint32_t)(VAL) << FXOSC_CTRL_GM_SEL_OFFSET)) 24*8ab34357SGhennadi Procopciuc #define FXOSC_CTRL_OSCON BIT_32(0U) 25*8ab34357SGhennadi Procopciuc 26*8ab34357SGhennadi Procopciuc #define FXOSC_STAT(FXOSC) ((FXOSC) + 0x4UL) 27*8ab34357SGhennadi Procopciuc #define FXOSC_STAT_OSC_STAT BIT_32(31U) 28*8ab34357SGhennadi Procopciuc 29*8ab34357SGhennadi Procopciuc #endif /* S32CC_CLK_REGS_H */ 30