105e6a563SLionel Debieve /* 205e6a563SLionel Debieve * Copyright (c) 2019, STMicroelectronics - All Rights Reserved 305e6a563SLionel Debieve * 405e6a563SLionel Debieve * SPDX-License-Identifier: BSD-3-Clause 505e6a563SLionel Debieve */ 605e6a563SLionel Debieve 705e6a563SLionel Debieve #include <assert.h> 8*4ce3e99aSScott Branden #include <inttypes.h> 9*4ce3e99aSScott Branden #include <stdint.h> 1005e6a563SLionel Debieve 1105e6a563SLionel Debieve #include <libfdt.h> 1205e6a563SLionel Debieve 1305e6a563SLionel Debieve #include <drivers/spi_mem.h> 1405e6a563SLionel Debieve #include <lib/utils_def.h> 1505e6a563SLionel Debieve 1605e6a563SLionel Debieve #define SPI_MEM_DEFAULT_SPEED_HZ 100000U 1705e6a563SLionel Debieve 1805e6a563SLionel Debieve /* 1905e6a563SLionel Debieve * struct spi_slave - Representation of a SPI slave. 2005e6a563SLionel Debieve * 2105e6a563SLionel Debieve * @max_hz: Maximum speed for this slave in Hertz. 2205e6a563SLionel Debieve * @cs: ID of the chip select connected to the slave. 2305e6a563SLionel Debieve * @mode: SPI mode to use for this slave (see SPI mode flags). 2405e6a563SLionel Debieve * @ops: Ops defined by the bus. 2505e6a563SLionel Debieve */ 2605e6a563SLionel Debieve struct spi_slave { 2705e6a563SLionel Debieve unsigned int max_hz; 2805e6a563SLionel Debieve unsigned int cs; 2905e6a563SLionel Debieve unsigned int mode; 3005e6a563SLionel Debieve const struct spi_bus_ops *ops; 3105e6a563SLionel Debieve }; 3205e6a563SLionel Debieve 3305e6a563SLionel Debieve static struct spi_slave spi_slave; 3405e6a563SLionel Debieve 3505e6a563SLionel Debieve static bool spi_mem_check_buswidth_req(uint8_t buswidth, bool tx) 3605e6a563SLionel Debieve { 3705e6a563SLionel Debieve switch (buswidth) { 3805e6a563SLionel Debieve case 1U: 3905e6a563SLionel Debieve return true; 4005e6a563SLionel Debieve 4105e6a563SLionel Debieve case 2U: 4205e6a563SLionel Debieve if ((tx && (spi_slave.mode & (SPI_TX_DUAL | SPI_TX_QUAD)) != 4305e6a563SLionel Debieve 0U) || 4405e6a563SLionel Debieve (!tx && (spi_slave.mode & (SPI_RX_DUAL | SPI_RX_QUAD)) != 4505e6a563SLionel Debieve 0U)) { 4605e6a563SLionel Debieve return true; 4705e6a563SLionel Debieve } 4805e6a563SLionel Debieve break; 4905e6a563SLionel Debieve 5005e6a563SLionel Debieve case 4U: 5105e6a563SLionel Debieve if ((tx && (spi_slave.mode & SPI_TX_QUAD) != 0U) || 5205e6a563SLionel Debieve (!tx && (spi_slave.mode & SPI_RX_QUAD) != 0U)) { 5305e6a563SLionel Debieve return true; 5405e6a563SLionel Debieve } 5505e6a563SLionel Debieve break; 5605e6a563SLionel Debieve 5705e6a563SLionel Debieve default: 5805e6a563SLionel Debieve break; 5905e6a563SLionel Debieve } 6005e6a563SLionel Debieve 6105e6a563SLionel Debieve return false; 6205e6a563SLionel Debieve } 6305e6a563SLionel Debieve 6405e6a563SLionel Debieve static bool spi_mem_supports_op(const struct spi_mem_op *op) 6505e6a563SLionel Debieve { 6605e6a563SLionel Debieve if (!spi_mem_check_buswidth_req(op->cmd.buswidth, true)) { 6705e6a563SLionel Debieve return false; 6805e6a563SLionel Debieve } 6905e6a563SLionel Debieve 7005e6a563SLionel Debieve if ((op->addr.nbytes != 0U) && 7105e6a563SLionel Debieve !spi_mem_check_buswidth_req(op->addr.buswidth, true)) { 7205e6a563SLionel Debieve return false; 7305e6a563SLionel Debieve } 7405e6a563SLionel Debieve 7505e6a563SLionel Debieve if ((op->dummy.nbytes != 0U) && 7605e6a563SLionel Debieve !spi_mem_check_buswidth_req(op->dummy.buswidth, true)) { 7705e6a563SLionel Debieve return false; 7805e6a563SLionel Debieve } 7905e6a563SLionel Debieve 8005e6a563SLionel Debieve if ((op->data.nbytes != 0U) && 8105e6a563SLionel Debieve !spi_mem_check_buswidth_req(op->data.buswidth, 8205e6a563SLionel Debieve op->data.dir == SPI_MEM_DATA_OUT)) { 8305e6a563SLionel Debieve return false; 8405e6a563SLionel Debieve } 8505e6a563SLionel Debieve 8605e6a563SLionel Debieve return true; 8705e6a563SLionel Debieve } 8805e6a563SLionel Debieve 8905e6a563SLionel Debieve static int spi_mem_set_speed_mode(void) 9005e6a563SLionel Debieve { 9105e6a563SLionel Debieve const struct spi_bus_ops *ops = spi_slave.ops; 9205e6a563SLionel Debieve int ret; 9305e6a563SLionel Debieve 9405e6a563SLionel Debieve ret = ops->set_speed(spi_slave.max_hz); 9505e6a563SLionel Debieve if (ret != 0) { 9605e6a563SLionel Debieve VERBOSE("Cannot set speed (err=%d)\n", ret); 9705e6a563SLionel Debieve return ret; 9805e6a563SLionel Debieve } 9905e6a563SLionel Debieve 10005e6a563SLionel Debieve ret = ops->set_mode(spi_slave.mode); 10105e6a563SLionel Debieve if (ret != 0) { 10205e6a563SLionel Debieve VERBOSE("Cannot set mode (err=%d)\n", ret); 10305e6a563SLionel Debieve return ret; 10405e6a563SLionel Debieve } 10505e6a563SLionel Debieve 10605e6a563SLionel Debieve return 0; 10705e6a563SLionel Debieve } 10805e6a563SLionel Debieve 10905e6a563SLionel Debieve static int spi_mem_check_bus_ops(const struct spi_bus_ops *ops) 11005e6a563SLionel Debieve { 11105e6a563SLionel Debieve bool error = false; 11205e6a563SLionel Debieve 11305e6a563SLionel Debieve if (ops->claim_bus == NULL) { 11405e6a563SLionel Debieve VERBOSE("Ops claim bus is not defined\n"); 11505e6a563SLionel Debieve error = true; 11605e6a563SLionel Debieve } 11705e6a563SLionel Debieve 11805e6a563SLionel Debieve if (ops->release_bus == NULL) { 11905e6a563SLionel Debieve VERBOSE("Ops release bus is not defined\n"); 12005e6a563SLionel Debieve error = true; 12105e6a563SLionel Debieve } 12205e6a563SLionel Debieve 12305e6a563SLionel Debieve if (ops->exec_op == NULL) { 12405e6a563SLionel Debieve VERBOSE("Ops exec op is not defined\n"); 12505e6a563SLionel Debieve error = true; 12605e6a563SLionel Debieve } 12705e6a563SLionel Debieve 12805e6a563SLionel Debieve if (ops->set_speed == NULL) { 12905e6a563SLionel Debieve VERBOSE("Ops set speed is not defined\n"); 13005e6a563SLionel Debieve error = true; 13105e6a563SLionel Debieve } 13205e6a563SLionel Debieve 13305e6a563SLionel Debieve if (ops->set_mode == NULL) { 13405e6a563SLionel Debieve VERBOSE("Ops set mode is not defined\n"); 13505e6a563SLionel Debieve error = true; 13605e6a563SLionel Debieve } 13705e6a563SLionel Debieve 13805e6a563SLionel Debieve return error ? -EINVAL : 0; 13905e6a563SLionel Debieve } 14005e6a563SLionel Debieve 14105e6a563SLionel Debieve /* 14205e6a563SLionel Debieve * spi_mem_exec_op() - Execute a memory operation. 14305e6a563SLionel Debieve * @op: The memory operation to execute. 14405e6a563SLionel Debieve * 14505e6a563SLionel Debieve * This function first checks that @op is supported and then tries to execute 14605e6a563SLionel Debieve * it. 14705e6a563SLionel Debieve * 14805e6a563SLionel Debieve * Return: 0 in case of success, a negative error code otherwise. 14905e6a563SLionel Debieve */ 15005e6a563SLionel Debieve int spi_mem_exec_op(const struct spi_mem_op *op) 15105e6a563SLionel Debieve { 15205e6a563SLionel Debieve const struct spi_bus_ops *ops = spi_slave.ops; 15305e6a563SLionel Debieve int ret; 15405e6a563SLionel Debieve 155*4ce3e99aSScott Branden VERBOSE("%s: cmd:%x mode:%d.%d.%d.%d addqr:%" PRIx64 " len:%x\n", 15605e6a563SLionel Debieve __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, 15705e6a563SLionel Debieve op->dummy.buswidth, op->data.buswidth, 15805e6a563SLionel Debieve op->addr.val, op->data.nbytes); 15905e6a563SLionel Debieve 16005e6a563SLionel Debieve if (!spi_mem_supports_op(op)) { 16105e6a563SLionel Debieve WARN("Error in spi_mem_support\n"); 16205e6a563SLionel Debieve return -ENOTSUP; 16305e6a563SLionel Debieve } 16405e6a563SLionel Debieve 16505e6a563SLionel Debieve ret = ops->claim_bus(spi_slave.cs); 16605e6a563SLionel Debieve if (ret != 0) { 16705e6a563SLionel Debieve WARN("Error claim_bus\n"); 16805e6a563SLionel Debieve return ret; 16905e6a563SLionel Debieve } 17005e6a563SLionel Debieve 17105e6a563SLionel Debieve ret = ops->exec_op(op); 17205e6a563SLionel Debieve 17305e6a563SLionel Debieve ops->release_bus(); 17405e6a563SLionel Debieve 17505e6a563SLionel Debieve return ret; 17605e6a563SLionel Debieve } 17705e6a563SLionel Debieve 17805e6a563SLionel Debieve /* 17905e6a563SLionel Debieve * spi_mem_init_slave() - SPI slave device initialization. 18005e6a563SLionel Debieve * @fdt: Pointer to the device tree blob. 18105e6a563SLionel Debieve * @bus_node: Offset of the bus node. 18205e6a563SLionel Debieve * @ops: The SPI bus ops defined. 18305e6a563SLionel Debieve * 18405e6a563SLionel Debieve * This function first checks that @ops are supported and then tries to find 18505e6a563SLionel Debieve * a SPI slave device. 18605e6a563SLionel Debieve * 18705e6a563SLionel Debieve * Return: 0 in case of success, a negative error code otherwise. 18805e6a563SLionel Debieve */ 18905e6a563SLionel Debieve int spi_mem_init_slave(void *fdt, int bus_node, const struct spi_bus_ops *ops) 19005e6a563SLionel Debieve { 19105e6a563SLionel Debieve int ret; 19205e6a563SLionel Debieve int mode = 0; 19305e6a563SLionel Debieve int nchips = 0; 19405e6a563SLionel Debieve int bus_subnode = 0; 19505e6a563SLionel Debieve const fdt32_t *cuint = NULL; 19605e6a563SLionel Debieve 19705e6a563SLionel Debieve ret = spi_mem_check_bus_ops(ops); 19805e6a563SLionel Debieve if (ret != 0) { 19905e6a563SLionel Debieve return ret; 20005e6a563SLionel Debieve } 20105e6a563SLionel Debieve 20205e6a563SLionel Debieve fdt_for_each_subnode(bus_subnode, fdt, bus_node) { 20305e6a563SLionel Debieve nchips++; 20405e6a563SLionel Debieve } 20505e6a563SLionel Debieve 20605e6a563SLionel Debieve if (nchips != 1) { 20705e6a563SLionel Debieve ERROR("Only one SPI device is currently supported\n"); 20805e6a563SLionel Debieve return -EINVAL; 20905e6a563SLionel Debieve } 21005e6a563SLionel Debieve 21105e6a563SLionel Debieve fdt_for_each_subnode(bus_subnode, fdt, bus_node) { 21205e6a563SLionel Debieve /* Get chip select */ 21305e6a563SLionel Debieve cuint = fdt_getprop(fdt, bus_subnode, "reg", NULL); 21405e6a563SLionel Debieve if (cuint == NULL) { 21505e6a563SLionel Debieve ERROR("Chip select not well defined\n"); 21605e6a563SLionel Debieve return -EINVAL; 21705e6a563SLionel Debieve } 21805e6a563SLionel Debieve spi_slave.cs = fdt32_to_cpu(*cuint); 21905e6a563SLionel Debieve 22005e6a563SLionel Debieve /* Get max slave frequency */ 22105e6a563SLionel Debieve spi_slave.max_hz = SPI_MEM_DEFAULT_SPEED_HZ; 22205e6a563SLionel Debieve cuint = fdt_getprop(fdt, bus_subnode, 22305e6a563SLionel Debieve "spi-max-frequency", NULL); 22405e6a563SLionel Debieve if (cuint != NULL) { 22505e6a563SLionel Debieve spi_slave.max_hz = fdt32_to_cpu(*cuint); 22605e6a563SLionel Debieve } 22705e6a563SLionel Debieve 22805e6a563SLionel Debieve /* Get mode */ 22905e6a563SLionel Debieve if ((fdt_getprop(fdt, bus_subnode, "spi-cpol", NULL)) != NULL) { 23005e6a563SLionel Debieve mode |= SPI_CPOL; 23105e6a563SLionel Debieve } 23205e6a563SLionel Debieve if ((fdt_getprop(fdt, bus_subnode, "spi-cpha", NULL)) != NULL) { 23305e6a563SLionel Debieve mode |= SPI_CPHA; 23405e6a563SLionel Debieve } 23505e6a563SLionel Debieve if ((fdt_getprop(fdt, bus_subnode, "spi-cs-high", NULL)) != 23605e6a563SLionel Debieve NULL) { 23705e6a563SLionel Debieve mode |= SPI_CS_HIGH; 23805e6a563SLionel Debieve } 23905e6a563SLionel Debieve if ((fdt_getprop(fdt, bus_subnode, "spi-3wire", NULL)) != 24005e6a563SLionel Debieve NULL) { 24105e6a563SLionel Debieve mode |= SPI_3WIRE; 24205e6a563SLionel Debieve } 24305e6a563SLionel Debieve if ((fdt_getprop(fdt, bus_subnode, "spi-half-duplex", NULL)) != 24405e6a563SLionel Debieve NULL) { 24505e6a563SLionel Debieve mode |= SPI_PREAMBLE; 24605e6a563SLionel Debieve } 24705e6a563SLionel Debieve 24805e6a563SLionel Debieve /* Get dual/quad mode */ 24905e6a563SLionel Debieve cuint = fdt_getprop(fdt, bus_subnode, "spi-tx-bus-width", NULL); 25005e6a563SLionel Debieve if (cuint != NULL) { 25105e6a563SLionel Debieve switch (fdt32_to_cpu(*cuint)) { 25205e6a563SLionel Debieve case 1U: 25305e6a563SLionel Debieve break; 25405e6a563SLionel Debieve case 2U: 25505e6a563SLionel Debieve mode |= SPI_TX_DUAL; 25605e6a563SLionel Debieve break; 25705e6a563SLionel Debieve case 4U: 25805e6a563SLionel Debieve mode |= SPI_TX_QUAD; 25905e6a563SLionel Debieve break; 26005e6a563SLionel Debieve default: 26105e6a563SLionel Debieve WARN("spi-tx-bus-width %d not supported\n", 26205e6a563SLionel Debieve fdt32_to_cpu(*cuint)); 26305e6a563SLionel Debieve return -EINVAL; 26405e6a563SLionel Debieve } 26505e6a563SLionel Debieve } 26605e6a563SLionel Debieve 26705e6a563SLionel Debieve cuint = fdt_getprop(fdt, bus_subnode, "spi-rx-bus-width", NULL); 26805e6a563SLionel Debieve if (cuint != NULL) { 26905e6a563SLionel Debieve switch (fdt32_to_cpu(*cuint)) { 27005e6a563SLionel Debieve case 1U: 27105e6a563SLionel Debieve break; 27205e6a563SLionel Debieve case 2U: 27305e6a563SLionel Debieve mode |= SPI_RX_DUAL; 27405e6a563SLionel Debieve break; 27505e6a563SLionel Debieve case 4U: 27605e6a563SLionel Debieve mode |= SPI_RX_QUAD; 27705e6a563SLionel Debieve break; 27805e6a563SLionel Debieve default: 27905e6a563SLionel Debieve WARN("spi-rx-bus-width %d not supported\n", 28005e6a563SLionel Debieve fdt32_to_cpu(*cuint)); 28105e6a563SLionel Debieve return -EINVAL; 28205e6a563SLionel Debieve } 28305e6a563SLionel Debieve } 28405e6a563SLionel Debieve 28505e6a563SLionel Debieve spi_slave.mode = mode; 28605e6a563SLionel Debieve spi_slave.ops = ops; 28705e6a563SLionel Debieve } 28805e6a563SLionel Debieve 28905e6a563SLionel Debieve return spi_mem_set_speed_mode(); 29005e6a563SLionel Debieve } 291