1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 /* AP806 Marvell SoC driver */ 9 10 #include <common/debug.h> 11 #include <drivers/marvell/ccu.h> 12 #include <drivers/marvell/cache_llc.h> 13 #include <drivers/marvell/io_win.h> 14 #include <drivers/marvell/mci.h> 15 #include <drivers/marvell/mochi/ap_setup.h> 16 #include <lib/mmio.h> 17 18 #include <mvebu_def.h> 19 20 #define SMMU_sACR (MVEBU_SMMU_BASE + 0x10) 21 #define SMMU_sACR_PG_64K (1 << 16) 22 23 #define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) + \ 24 0x3F0) 25 #define GSPMU_CPU_CONTROL (0x1 << 0) 26 27 #define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) + \ 28 0x200) 29 #define CCU_SET_POC_OFFSET 5 30 31 #define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \ 32 0x90 + 4 * (win)) 33 34 #define DSS_CR0 (MVEBU_RFU_BASE + 0x100) 35 #define DVM_48BIT_VA_ENABLE (1 << 21) 36 37 /* Secure MoChi incoming access */ 38 #define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738) 39 #define SEC_MOCHI_IN_ACC_IHB0_EN (1) 40 #define SEC_MOCHI_IN_ACC_IHB1_EN (1 << 3) 41 #define SEC_MOCHI_IN_ACC_IHB2_EN (1 << 6) 42 #define SEC_MOCHI_IN_ACC_PIDI_EN (1 << 9) 43 #define SEC_IN_ACCESS_ENA_ALL_MASTERS (SEC_MOCHI_IN_ACC_IHB0_EN | \ 44 SEC_MOCHI_IN_ACC_IHB1_EN | \ 45 SEC_MOCHI_IN_ACC_IHB2_EN | \ 46 SEC_MOCHI_IN_ACC_PIDI_EN) 47 48 /* SYSRST_OUTn Config definitions */ 49 #define MVEBU_SYSRST_OUT_CONFIG_REG (MVEBU_MISC_SOC_BASE + 0x4) 50 #define WD_MASK_SYS_RST_OUT (1 << 2) 51 52 /* Generic Timer System Controller */ 53 #define MVEBU_MSS_GTCR_REG (MVEBU_REGS_BASE + 0x581000) 54 #define MVEBU_MSS_GTCR_ENABLE_BIT 0x1 55 56 /* 57 * AXI Configuration. 58 */ 59 60 /* Used for Units of AP-806 (e.g. SDIO and etc) */ 61 #define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580) 62 #define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \ 63 0x4 * index) 64 65 enum axi_attr { 66 AXI_SDIO_ATTR = 0, 67 AXI_DFX_ATTR, 68 AXI_MAX_ATTR, 69 }; 70 71 static void apn_sec_masters_access_en(uint32_t enable) 72 { 73 uint32_t reg; 74 75 /* Open/Close incoming access for all masters. 76 * The access is disabled in trusted boot mode 77 * Could only be done in EL3 78 */ 79 reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG); 80 if (enable) 81 mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg | 82 SEC_IN_ACCESS_ENA_ALL_MASTERS); 83 else 84 mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg & 85 ~SEC_IN_ACCESS_ENA_ALL_MASTERS); 86 } 87 88 static void setup_smmu(void) 89 { 90 uint32_t reg; 91 92 /* Set the SMMU page size to 64 KB */ 93 reg = mmio_read_32(SMMU_sACR); 94 reg |= SMMU_sACR_PG_64K; 95 mmio_write_32(SMMU_sACR, reg); 96 } 97 98 static void apn806_errata_wa_init(void) 99 { 100 /* 101 * ERRATA ID: RES-3033912 - Internal Address Space Init state causes 102 * a hang upon accesses to [0xf070_0000, 0xf07f_ffff] 103 * Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to 104 * split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and 105 * [0x80_0000, 0xff_ffff] that cause accesses to the 106 * segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI. 107 */ 108 mmio_write_32(CCU_RGF(4), 0x37f9b809); 109 mmio_write_32(CCU_RGF(5), 0x7ffa0009); 110 } 111 112 static void init_aurora2(void) 113 { 114 uint32_t reg; 115 116 /* Enable GSPMU control by CPU */ 117 reg = mmio_read_32(CCU_GSPMU_CR); 118 reg |= GSPMU_CPU_CONTROL; 119 mmio_write_32(CCU_GSPMU_CR, reg); 120 121 #if LLC_ENABLE 122 /* Enable LLC for AP806 in exclusive mode */ 123 llc_enable(0, 1); 124 125 /* Set point of coherency to DDR. 126 * This is required by units which have 127 * SW cache coherency 128 */ 129 reg = mmio_read_32(CCU_HTC_CR); 130 reg |= (0x1 << CCU_SET_POC_OFFSET); 131 mmio_write_32(CCU_HTC_CR, reg); 132 #endif /* LLC_ENABLE */ 133 134 apn806_errata_wa_init(); 135 } 136 137 138 /* MCIx indirect access register are based by default at 0xf4000000/0xf6000000 139 * to avoid conflict of internal registers of units connected via MCIx, which 140 * can be based on the same address (i.e CP1 base is also 0xf4000000), 141 * the following routines remaps the MCIx indirect bases to another domain 142 */ 143 static void mci_remap_indirect_access_base(void) 144 { 145 uint32_t mci; 146 147 for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++) 148 mmio_write_32(MCIX4_REG_START_ADDRESS_REG(mci), 149 MVEBU_MCI_REG_BASE_REMAP(mci) >> 150 MCI_REMAP_OFF_SHIFT); 151 } 152 153 static void apn806_axi_attr_init(void) 154 { 155 uint32_t index, data; 156 157 /* Initialize AXI attributes for APN806 */ 158 159 /* Go over the AXI attributes and set Ax-Cache and Ax-Domain */ 160 for (index = 0; index < AXI_MAX_ATTR; index++) { 161 switch (index) { 162 /* DFX works with no coherent only - 163 * there's no option to configure the Ax-Cache and Ax-Domain 164 */ 165 case AXI_DFX_ATTR: 166 continue; 167 default: 168 /* Set Ax-Cache as cacheable, no allocate, modifiable, 169 * bufferable 170 * The values are different because Read & Write 171 * definition is different in Ax-Cache 172 */ 173 data = mmio_read_32(MVEBU_AXI_ATTR_REG(index)); 174 data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; 175 data |= (CACHE_ATTR_WRITE_ALLOC | 176 CACHE_ATTR_CACHEABLE | 177 CACHE_ATTR_BUFFERABLE) << 178 MVEBU_AXI_ATTR_ARCACHE_OFFSET; 179 data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; 180 data |= (CACHE_ATTR_READ_ALLOC | 181 CACHE_ATTR_CACHEABLE | 182 CACHE_ATTR_BUFFERABLE) << 183 MVEBU_AXI_ATTR_AWCACHE_OFFSET; 184 /* Set Ax-Domain as Outer domain */ 185 data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; 186 data |= DOMAIN_OUTER_SHAREABLE << 187 MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; 188 data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; 189 data |= DOMAIN_OUTER_SHAREABLE << 190 MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; 191 mmio_write_32(MVEBU_AXI_ATTR_REG(index), data); 192 } 193 } 194 } 195 196 static void dss_setup(void) 197 { 198 /* Enable 48-bit VA */ 199 mmio_setbits_32(DSS_CR0, DVM_48BIT_VA_ENABLE); 200 } 201 202 void misc_soc_configurations(void) 203 { 204 uint32_t reg; 205 206 /* Un-mask Watchdog reset from influencing the SYSRST_OUTn. 207 * Otherwise, upon WD timeout, the WD reset signal won't trigger reset 208 */ 209 reg = mmio_read_32(MVEBU_SYSRST_OUT_CONFIG_REG); 210 reg &= ~(WD_MASK_SYS_RST_OUT); 211 mmio_write_32(MVEBU_SYSRST_OUT_CONFIG_REG, reg); 212 } 213 214 void ap_init(void) 215 { 216 /* Setup Aurora2. */ 217 init_aurora2(); 218 219 /* configure MCI mapping */ 220 mci_remap_indirect_access_base(); 221 222 /* configure IO_WIN windows */ 223 init_io_win(MVEBU_AP0); 224 225 /* configure CCU windows */ 226 init_ccu(MVEBU_AP0); 227 228 /* configure DSS */ 229 dss_setup(); 230 231 /* configure the SMMU */ 232 setup_smmu(); 233 234 /* Open APN incoming access for all masters */ 235 apn_sec_masters_access_en(1); 236 237 /* configure axi for APN*/ 238 apn806_axi_attr_init(); 239 240 /* misc configuration of the SoC */ 241 misc_soc_configurations(); 242 } 243 244 void ap_ble_init(void) 245 { 246 } 247 248 int ap_get_count(void) 249 { 250 return 1; 251 } 252 253