1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 /* AP807 Marvell SoC driver */ 9 10 #include <common/debug.h> 11 #include <drivers/marvell/cache_llc.h> 12 #include <drivers/marvell/ccu.h> 13 #include <drivers/marvell/io_win.h> 14 #include <drivers/marvell/mci.h> 15 #include <drivers/marvell/mochi/ap_setup.h> 16 #include <lib/mmio.h> 17 18 #include <mvebu_def.h> 19 20 #define SMMU_sACR (MVEBU_SMMU_BASE + 0x10) 21 #define SMMU_sACR_PG_64K (1 << 16) 22 23 #define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) \ 24 + 0x3F0) 25 #define GSPMU_CPU_CONTROL (0x1 << 0) 26 27 #define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) \ 28 + 0x200) 29 #define CCU_SET_POC_OFFSET 5 30 31 #define DSS_CR0 (MVEBU_RFU_BASE + 0x100) 32 #define DVM_48BIT_VA_ENABLE (1 << 21) 33 34 /* Secure MoChi incoming access */ 35 #define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738) 36 #define SEC_MOCHI_IN_ACC_IHB0_EN (1) 37 #define SEC_MOCHI_IN_ACC_IHB1_EN (1 << 3) 38 #define SEC_MOCHI_IN_ACC_IHB2_EN (1 << 6) 39 #define SEC_MOCHI_IN_ACC_PIDI_EN (1 << 9) 40 #define SEC_IN_ACCESS_ENA_ALL_MASTERS (SEC_MOCHI_IN_ACC_IHB0_EN | \ 41 SEC_MOCHI_IN_ACC_IHB1_EN | \ 42 SEC_MOCHI_IN_ACC_IHB2_EN | \ 43 SEC_MOCHI_IN_ACC_PIDI_EN) 44 45 /* SYSRST_OUTn Config definitions */ 46 #define MVEBU_SYSRST_OUT_CONFIG_REG (MVEBU_MISC_SOC_BASE + 0x4) 47 #define WD_MASK_SYS_RST_OUT (1 << 2) 48 49 /* DSS PHY for DRAM */ 50 #define DSS_SCR_REG (MVEBU_RFU_BASE + 0x208) 51 #define DSS_PPROT_OFFS 4 52 #define DSS_PPROT_MASK 0x7 53 #define DSS_PPROT_PRIV_SECURE_DATA 0x1 54 55 /* Used for Units of AP-807 (e.g. SDIO and etc) */ 56 #define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580) 57 #define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \ 58 0x4 * index) 59 60 enum axi_attr { 61 AXI_SDIO_ATTR = 0, 62 AXI_DFX_ATTR, 63 AXI_MAX_ATTR, 64 }; 65 66 static void ap_sec_masters_access_en(uint32_t enable) 67 { 68 uint32_t reg; 69 70 /* Open/Close incoming access for all masters. 71 * The access is disabled in trusted boot mode 72 * Could only be done in EL3 73 */ 74 reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG); 75 if (enable) 76 mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg | 77 SEC_IN_ACCESS_ENA_ALL_MASTERS); 78 else 79 mmio_write_32(SEC_MOCHI_IN_ACC_REG, 80 reg & ~SEC_IN_ACCESS_ENA_ALL_MASTERS); 81 } 82 83 static void setup_smmu(void) 84 { 85 uint32_t reg; 86 87 /* Set the SMMU page size to 64 KB */ 88 reg = mmio_read_32(SMMU_sACR); 89 reg |= SMMU_sACR_PG_64K; 90 mmio_write_32(SMMU_sACR, reg); 91 } 92 93 static void init_aurora2(void) 94 { 95 uint32_t reg; 96 97 /* Enable GSPMU control by CPU */ 98 reg = mmio_read_32(CCU_GSPMU_CR); 99 reg |= GSPMU_CPU_CONTROL; 100 mmio_write_32(CCU_GSPMU_CR, reg); 101 102 #if LLC_ENABLE 103 /* Enable LLC for AP807 in exclusive mode */ 104 llc_enable(0, 1); 105 106 /* Set point of coherency to DDR. 107 * This is required by units which have 108 * SW cache coherency 109 */ 110 reg = mmio_read_32(CCU_HTC_CR); 111 reg |= (0x1 << CCU_SET_POC_OFFSET); 112 mmio_write_32(CCU_HTC_CR, reg); 113 #endif /* LLC_ENABLE */ 114 } 115 116 117 /* MCIx indirect access register are based by default at 0xf4000000/0xf6000000 118 * to avoid conflict of internal registers of units connected via MCIx, which 119 * can be based on the same address (i.e CP1 base is also 0xf4000000), 120 * the following routines remaps the MCIx indirect bases to another domain 121 */ 122 static void mci_remap_indirect_access_base(void) 123 { 124 uint32_t mci; 125 126 for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++) 127 mmio_write_32(MCIX4_REG_START_ADDRESS_REG(mci), 128 MVEBU_MCI_REG_BASE_REMAP(mci) >> 129 MCI_REMAP_OFF_SHIFT); 130 } 131 132 static void ap807_axi_attr_init(void) 133 { 134 uint32_t index, data; 135 136 /* Initialize AXI attributes for AP807 */ 137 /* Go over the AXI attributes and set Ax-Cache and Ax-Domain */ 138 for (index = 0; index < AXI_MAX_ATTR; index++) { 139 switch (index) { 140 /* DFX works with no coherent only - 141 * there's no option to configure the Ax-Cache and Ax-Domain 142 */ 143 case AXI_DFX_ATTR: 144 continue; 145 default: 146 /* Set Ax-Cache as cacheable, no allocate, modifiable, 147 * bufferable. 148 * The values are different because Read & Write 149 * definition is different in Ax-Cache 150 */ 151 data = mmio_read_32(MVEBU_AXI_ATTR_REG(index)); 152 data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; 153 data |= (CACHE_ATTR_WRITE_ALLOC | 154 CACHE_ATTR_CACHEABLE | 155 CACHE_ATTR_BUFFERABLE) << 156 MVEBU_AXI_ATTR_ARCACHE_OFFSET; 157 data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; 158 data |= (CACHE_ATTR_READ_ALLOC | 159 CACHE_ATTR_CACHEABLE | 160 CACHE_ATTR_BUFFERABLE) << 161 MVEBU_AXI_ATTR_AWCACHE_OFFSET; 162 /* Set Ax-Domain as Outer domain */ 163 data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; 164 data |= DOMAIN_OUTER_SHAREABLE << 165 MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; 166 data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; 167 data |= DOMAIN_OUTER_SHAREABLE << 168 MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; 169 mmio_write_32(MVEBU_AXI_ATTR_REG(index), data); 170 } 171 } 172 } 173 174 static void misc_soc_configurations(void) 175 { 176 uint32_t reg; 177 178 /* Enable 48-bit VA */ 179 mmio_setbits_32(DSS_CR0, DVM_48BIT_VA_ENABLE); 180 181 /* Un-mask Watchdog reset from influencing the SYSRST_OUTn. 182 * Otherwise, upon WD timeout, the WD reset signal won't trigger reset 183 */ 184 reg = mmio_read_32(MVEBU_SYSRST_OUT_CONFIG_REG); 185 reg &= ~(WD_MASK_SYS_RST_OUT); 186 mmio_write_32(MVEBU_SYSRST_OUT_CONFIG_REG, reg); 187 } 188 189 void ap_init(void) 190 { 191 /* Setup Aurora2. */ 192 init_aurora2(); 193 194 /* configure MCI mapping */ 195 mci_remap_indirect_access_base(); 196 197 /* configure IO_WIN windows */ 198 init_io_win(MVEBU_AP0); 199 200 /* configure CCU windows */ 201 init_ccu(MVEBU_AP0); 202 203 /* configure the SMMU */ 204 setup_smmu(); 205 206 /* Open AP incoming access for all masters */ 207 ap_sec_masters_access_en(1); 208 209 /* configure axi for AP */ 210 ap807_axi_attr_init(); 211 212 /* misc configuration of the SoC */ 213 misc_soc_configurations(); 214 } 215 216 static void ap807_dram_phy_access_config(void) 217 { 218 uint32_t reg_val; 219 /* Update DSS port access permission to DSS_PHY */ 220 reg_val = mmio_read_32(DSS_SCR_REG); 221 reg_val &= ~(DSS_PPROT_MASK << DSS_PPROT_OFFS); 222 reg_val |= ((DSS_PPROT_PRIV_SECURE_DATA & DSS_PPROT_MASK) << 223 DSS_PPROT_OFFS); 224 mmio_write_32(DSS_SCR_REG, reg_val); 225 } 226 227 void ap_ble_init(void) 228 { 229 /* Enable DSS port */ 230 ap807_dram_phy_access_config(); 231 } 232 233 int ap_get_count(void) 234 { 235 return 1; 236 } 237 238 239