1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 /* AP807 Marvell SoC driver */ 9 10 #include <common/debug.h> 11 #include <drivers/marvell/cache_llc.h> 12 #include <drivers/marvell/ccu.h> 13 #include <drivers/marvell/io_win.h> 14 #include <drivers/marvell/iob.h> 15 #include <drivers/marvell/mci.h> 16 #include <drivers/marvell/mochi/ap_setup.h> 17 #include <lib/mmio.h> 18 19 #include <mvebu_def.h> 20 21 #define SMMU_sACR (MVEBU_SMMU_BASE + 0x10) 22 #define SMMU_sACR_PG_64K (1 << 16) 23 24 #define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) \ 25 + 0x3F0) 26 #define GSPMU_CPU_CONTROL (0x1 << 0) 27 28 #define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) \ 29 + 0x200) 30 #define CCU_SET_POC_OFFSET 5 31 32 #define DSS_CR0 (MVEBU_RFU_BASE + 0x100) 33 #define DVM_48BIT_VA_ENABLE (1 << 21) 34 35 36 /* SoC RFU / IHBx4 Control */ 37 #define MCIX4_807_REG_START_ADDR_REG(unit_id) (MVEBU_RFU_BASE + \ 38 0x4258 + (unit_id * 0x4)) 39 40 /* Secure MoChi incoming access */ 41 #define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738) 42 #define SEC_MOCHI_IN_ACC_IHB0_EN (1) 43 #define SEC_MOCHI_IN_ACC_IHB1_EN (1 << 3) 44 #define SEC_MOCHI_IN_ACC_IHB2_EN (1 << 6) 45 #define SEC_MOCHI_IN_ACC_PIDI_EN (1 << 9) 46 #define SEC_IN_ACCESS_ENA_ALL_MASTERS (SEC_MOCHI_IN_ACC_IHB0_EN | \ 47 SEC_MOCHI_IN_ACC_IHB1_EN | \ 48 SEC_MOCHI_IN_ACC_IHB2_EN | \ 49 SEC_MOCHI_IN_ACC_PIDI_EN) 50 51 /* SYSRST_OUTn Config definitions */ 52 #define MVEBU_SYSRST_OUT_CONFIG_REG (MVEBU_MISC_SOC_BASE + 0x4) 53 #define WD_MASK_SYS_RST_OUT (1 << 2) 54 55 /* DSS PHY for DRAM */ 56 #define DSS_SCR_REG (MVEBU_RFU_BASE + 0x208) 57 #define DSS_PPROT_OFFS 4 58 #define DSS_PPROT_MASK 0x7 59 #define DSS_PPROT_PRIV_SECURE_DATA 0x1 60 61 /* Used for Units of AP-807 (e.g. SDIO and etc) */ 62 #define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580) 63 #define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \ 64 0x4 * index) 65 66 enum axi_attr { 67 AXI_SDIO_ATTR = 0, 68 AXI_DFX_ATTR, 69 AXI_MAX_ATTR, 70 }; 71 72 static void ap_sec_masters_access_en(uint32_t enable) 73 { 74 uint32_t reg; 75 76 /* Open/Close incoming access for all masters. 77 * The access is disabled in trusted boot mode 78 * Could only be done in EL3 79 */ 80 reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG); 81 if (enable) 82 mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg | 83 SEC_IN_ACCESS_ENA_ALL_MASTERS); 84 else 85 mmio_write_32(SEC_MOCHI_IN_ACC_REG, 86 reg & ~SEC_IN_ACCESS_ENA_ALL_MASTERS); 87 } 88 89 static void setup_smmu(void) 90 { 91 uint32_t reg; 92 93 /* Set the SMMU page size to 64 KB */ 94 reg = mmio_read_32(SMMU_sACR); 95 reg |= SMMU_sACR_PG_64K; 96 mmio_write_32(SMMU_sACR, reg); 97 } 98 99 static void init_aurora2(void) 100 { 101 uint32_t reg; 102 103 /* Enable GSPMU control by CPU */ 104 reg = mmio_read_32(CCU_GSPMU_CR); 105 reg |= GSPMU_CPU_CONTROL; 106 mmio_write_32(CCU_GSPMU_CR, reg); 107 108 #if LLC_ENABLE 109 /* Enable LLC for AP807 in exclusive mode */ 110 llc_enable(0, 1); 111 112 /* Set point of coherency to DDR. 113 * This is required by units which have 114 * SW cache coherency 115 */ 116 reg = mmio_read_32(CCU_HTC_CR); 117 reg |= (0x1 << CCU_SET_POC_OFFSET); 118 mmio_write_32(CCU_HTC_CR, reg); 119 #endif /* LLC_ENABLE */ 120 } 121 122 123 /* MCIx indirect access register are based by default at 0xf4000000/0xf6000000 124 * to avoid conflict of internal registers of units connected via MCIx, which 125 * can be based on the same address (i.e CP1 base is also 0xf4000000), 126 * the following routines remaps the MCIx indirect bases to another domain 127 */ 128 static void mci_remap_indirect_access_base(void) 129 { 130 uint32_t mci; 131 132 for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++) 133 mmio_write_32(MCIX4_807_REG_START_ADDR_REG(mci), 134 MVEBU_MCI_REG_BASE_REMAP(mci) >> 135 MCI_REMAP_OFF_SHIFT); 136 } 137 138 static void ap807_axi_attr_init(void) 139 { 140 uint32_t index, data; 141 142 /* Initialize AXI attributes for AP807 */ 143 /* Go over the AXI attributes and set Ax-Cache and Ax-Domain */ 144 for (index = 0; index < AXI_MAX_ATTR; index++) { 145 switch (index) { 146 /* DFX works with no coherent only - 147 * there's no option to configure the Ax-Cache and Ax-Domain 148 */ 149 case AXI_DFX_ATTR: 150 continue; 151 default: 152 /* Set Ax-Cache as cacheable, no allocate, modifiable, 153 * bufferable. 154 * The values are different because Read & Write 155 * definition is different in Ax-Cache 156 */ 157 data = mmio_read_32(MVEBU_AXI_ATTR_REG(index)); 158 data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; 159 data |= (CACHE_ATTR_WRITE_ALLOC | 160 CACHE_ATTR_CACHEABLE | 161 CACHE_ATTR_BUFFERABLE) << 162 MVEBU_AXI_ATTR_ARCACHE_OFFSET; 163 data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; 164 data |= (CACHE_ATTR_READ_ALLOC | 165 CACHE_ATTR_CACHEABLE | 166 CACHE_ATTR_BUFFERABLE) << 167 MVEBU_AXI_ATTR_AWCACHE_OFFSET; 168 /* Set Ax-Domain as Outer domain */ 169 data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; 170 data |= DOMAIN_OUTER_SHAREABLE << 171 MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; 172 data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; 173 data |= DOMAIN_OUTER_SHAREABLE << 174 MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; 175 mmio_write_32(MVEBU_AXI_ATTR_REG(index), data); 176 } 177 } 178 } 179 180 static void misc_soc_configurations(void) 181 { 182 uint32_t reg; 183 184 /* Enable 48-bit VA */ 185 mmio_setbits_32(DSS_CR0, DVM_48BIT_VA_ENABLE); 186 187 /* Un-mask Watchdog reset from influencing the SYSRST_OUTn. 188 * Otherwise, upon WD timeout, the WD reset signal won't trigger reset 189 */ 190 reg = mmio_read_32(MVEBU_SYSRST_OUT_CONFIG_REG); 191 reg &= ~(WD_MASK_SYS_RST_OUT); 192 mmio_write_32(MVEBU_SYSRST_OUT_CONFIG_REG, reg); 193 } 194 195 /* 196 * By default all external CPs start with configuration address space set to 197 * 0xf200_0000. To overcome this issue, go in the loop and initialize the 198 * CP one by one, using temporary window configuration which allows to access 199 * each CP and update its configuration space according to decoding 200 * windows scheme defined for each platform. 201 */ 202 void update_cp110_default_win(int cp_id) 203 { 204 int mci_id = cp_id - 1; 205 uintptr_t cp110_base, cp110_temp_base; 206 207 /* CP110 default configuration address space */ 208 cp110_temp_base = MVEBU_AP_IO_BASE(MVEBU_AP0); 209 210 struct addr_map_win iowin_temp_win = { 211 .base_addr = cp110_temp_base, 212 .win_size = MVEBU_CP_OFFSET, 213 }; 214 215 iowin_temp_win.target_id = mci_id; 216 iow_temp_win_insert(0, &iowin_temp_win, 1); 217 218 /* Calculate the new CP110 - base address */ 219 cp110_base = MVEBU_CP_REGS_BASE(cp_id); 220 /* Go and update the CP110 configuration address space */ 221 iob_cfg_space_update(0, cp_id, cp110_temp_base, cp110_base); 222 223 /* Remove the temporary IO-WIN window */ 224 iow_temp_win_remove(0, &iowin_temp_win, 1); 225 } 226 227 void ap_init(void) 228 { 229 /* Setup Aurora2. */ 230 init_aurora2(); 231 232 /* configure MCI mapping */ 233 mci_remap_indirect_access_base(); 234 235 /* configure IO_WIN windows */ 236 init_io_win(MVEBU_AP0); 237 238 /* configure CCU windows */ 239 init_ccu(MVEBU_AP0); 240 241 /* configure the SMMU */ 242 setup_smmu(); 243 244 /* Open AP incoming access for all masters */ 245 ap_sec_masters_access_en(1); 246 247 /* configure axi for AP */ 248 ap807_axi_attr_init(); 249 250 /* misc configuration of the SoC */ 251 misc_soc_configurations(); 252 } 253 254 static void ap807_dram_phy_access_config(void) 255 { 256 uint32_t reg_val; 257 /* Update DSS port access permission to DSS_PHY */ 258 reg_val = mmio_read_32(DSS_SCR_REG); 259 reg_val &= ~(DSS_PPROT_MASK << DSS_PPROT_OFFS); 260 reg_val |= ((DSS_PPROT_PRIV_SECURE_DATA & DSS_PPROT_MASK) << 261 DSS_PPROT_OFFS); 262 mmio_write_32(DSS_SCR_REG, reg_val); 263 } 264 265 void ap_ble_init(void) 266 { 267 /* Enable DSS port */ 268 ap807_dram_phy_access_config(); 269 } 270 271 int ap_get_count(void) 272 { 273 return 1; 274 } 275 276 277