1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 /* AP807 Marvell SoC driver */ 9 10 #include <common/debug.h> 11 #include <drivers/marvell/cache_llc.h> 12 #include <drivers/marvell/ccu.h> 13 #include <drivers/marvell/io_win.h> 14 #include <drivers/marvell/iob.h> 15 #include <drivers/marvell/mci.h> 16 #include <drivers/marvell/mochi/ap_setup.h> 17 #include <lib/mmio.h> 18 19 #include <mvebu_def.h> 20 21 #define SMMU_sACR (MVEBU_SMMU_BASE + 0x10) 22 #define SMMU_sACR_PG_64K (1 << 16) 23 24 #define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) \ 25 + 0x3F0) 26 #define GSPMU_CPU_CONTROL (0x1 << 0) 27 28 #define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) \ 29 + 0x200) 30 #define CCU_SET_POC_OFFSET 5 31 32 #define DSS_CR0 (MVEBU_RFU_BASE + 0x100) 33 #define DVM_48BIT_VA_ENABLE (1 << 21) 34 35 36 /* SoC RFU / IHBx4 Control */ 37 #define MCIX4_807_REG_START_ADDR_REG(unit_id) (MVEBU_RFU_BASE + \ 38 0x4258 + (unit_id * 0x4)) 39 40 /* Secure MoChi incoming access */ 41 #define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738) 42 #define SEC_MOCHI_IN_ACC_IHB0_EN (1) 43 #define SEC_MOCHI_IN_ACC_IHB1_EN (1 << 3) 44 #define SEC_MOCHI_IN_ACC_IHB2_EN (1 << 6) 45 #define SEC_MOCHI_IN_ACC_PIDI_EN (1 << 9) 46 #define SEC_IN_ACCESS_ENA_ALL_MASTERS (SEC_MOCHI_IN_ACC_IHB0_EN | \ 47 SEC_MOCHI_IN_ACC_IHB1_EN | \ 48 SEC_MOCHI_IN_ACC_IHB2_EN | \ 49 SEC_MOCHI_IN_ACC_PIDI_EN) 50 #define MOCHI_IN_ACC_LEVEL_FORCE_NONSEC (0) 51 #define MOCHI_IN_ACC_LEVEL_FORCE_SEC (1) 52 #define MOCHI_IN_ACC_LEVEL_LEAVE_ORIG (2) 53 #define MOCHI_IN_ACC_LEVEL_MASK_ALL (3) 54 #define SEC_MOCHI_IN_ACC_IHB0_LEVEL(l) ((l) << 1) 55 #define SEC_MOCHI_IN_ACC_IHB1_LEVEL(l) ((l) << 4) 56 #define SEC_MOCHI_IN_ACC_PIDI_LEVEL(l) ((l) << 10) 57 58 59 /* SYSRST_OUTn Config definitions */ 60 #define MVEBU_SYSRST_OUT_CONFIG_REG (MVEBU_MISC_SOC_BASE + 0x4) 61 #define WD_MASK_SYS_RST_OUT (1 << 2) 62 63 /* DSS PHY for DRAM */ 64 #define DSS_SCR_REG (MVEBU_RFU_BASE + 0x208) 65 #define DSS_PPROT_OFFS 4 66 #define DSS_PPROT_MASK 0x7 67 #define DSS_PPROT_PRIV_SECURE_DATA 0x1 68 69 /* Used for Units of AP-807 (e.g. SDIO and etc) */ 70 #define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580) 71 #define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \ 72 0x4 * index) 73 74 enum axi_attr { 75 AXI_SDIO_ATTR = 0, 76 AXI_DFX_ATTR, 77 AXI_MAX_ATTR, 78 }; 79 80 static void ap_sec_masters_access_en(uint32_t enable) 81 { 82 /* Open/Close incoming access for all masters. 83 * The access is disabled in trusted boot mode 84 * Could only be done in EL3 85 */ 86 if (enable != 0) { 87 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 0x0U, /* no clear */ 88 SEC_IN_ACCESS_ENA_ALL_MASTERS); 89 #if LLC_SRAM 90 /* Do not change access security level 91 * for PIDI masters 92 */ 93 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 94 SEC_MOCHI_IN_ACC_PIDI_LEVEL( 95 MOCHI_IN_ACC_LEVEL_MASK_ALL), 96 SEC_MOCHI_IN_ACC_PIDI_LEVEL( 97 MOCHI_IN_ACC_LEVEL_LEAVE_ORIG)); 98 #endif 99 } else { 100 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 101 SEC_IN_ACCESS_ENA_ALL_MASTERS, 102 0x0U /* no set */); 103 #if LLC_SRAM 104 /* Return PIDI access level to the default */ 105 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 106 SEC_MOCHI_IN_ACC_PIDI_LEVEL( 107 MOCHI_IN_ACC_LEVEL_MASK_ALL), 108 SEC_MOCHI_IN_ACC_PIDI_LEVEL( 109 MOCHI_IN_ACC_LEVEL_FORCE_NONSEC)); 110 #endif 111 } 112 } 113 114 static void setup_smmu(void) 115 { 116 uint32_t reg; 117 118 /* Set the SMMU page size to 64 KB */ 119 reg = mmio_read_32(SMMU_sACR); 120 reg |= SMMU_sACR_PG_64K; 121 mmio_write_32(SMMU_sACR, reg); 122 } 123 124 static void init_aurora2(void) 125 { 126 uint32_t reg; 127 128 /* Enable GSPMU control by CPU */ 129 reg = mmio_read_32(CCU_GSPMU_CR); 130 reg |= GSPMU_CPU_CONTROL; 131 mmio_write_32(CCU_GSPMU_CR, reg); 132 133 #if LLC_ENABLE 134 /* Enable LLC for AP807 in exclusive mode */ 135 llc_enable(0, 1); 136 137 /* Set point of coherency to DDR. 138 * This is required by units which have 139 * SW cache coherency 140 */ 141 reg = mmio_read_32(CCU_HTC_CR); 142 reg |= (0x1 << CCU_SET_POC_OFFSET); 143 mmio_write_32(CCU_HTC_CR, reg); 144 #endif /* LLC_ENABLE */ 145 146 errata_wa_init(); 147 } 148 149 150 /* MCIx indirect access register are based by default at 0xf4000000/0xf6000000 151 * to avoid conflict of internal registers of units connected via MCIx, which 152 * can be based on the same address (i.e CP1 base is also 0xf4000000), 153 * the following routines remaps the MCIx indirect bases to another domain 154 */ 155 static void mci_remap_indirect_access_base(void) 156 { 157 uint32_t mci; 158 159 for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++) 160 mmio_write_32(MCIX4_807_REG_START_ADDR_REG(mci), 161 MVEBU_MCI_REG_BASE_REMAP(mci) >> 162 MCI_REMAP_OFF_SHIFT); 163 } 164 165 static void ap807_axi_attr_init(void) 166 { 167 uint32_t index, data; 168 169 /* Initialize AXI attributes for AP807 */ 170 /* Go over the AXI attributes and set Ax-Cache and Ax-Domain */ 171 for (index = 0; index < AXI_MAX_ATTR; index++) { 172 switch (index) { 173 /* DFX works with no coherent only - 174 * there's no option to configure the Ax-Cache and Ax-Domain 175 */ 176 case AXI_DFX_ATTR: 177 continue; 178 default: 179 /* Set Ax-Cache as cacheable, no allocate, modifiable, 180 * bufferable. 181 * The values are different because Read & Write 182 * definition is different in Ax-Cache 183 */ 184 data = mmio_read_32(MVEBU_AXI_ATTR_REG(index)); 185 data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; 186 data |= (CACHE_ATTR_WRITE_ALLOC | 187 CACHE_ATTR_CACHEABLE | 188 CACHE_ATTR_BUFFERABLE) << 189 MVEBU_AXI_ATTR_ARCACHE_OFFSET; 190 data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; 191 data |= (CACHE_ATTR_READ_ALLOC | 192 CACHE_ATTR_CACHEABLE | 193 CACHE_ATTR_BUFFERABLE) << 194 MVEBU_AXI_ATTR_AWCACHE_OFFSET; 195 /* Set Ax-Domain as Outer domain */ 196 data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; 197 data |= DOMAIN_OUTER_SHAREABLE << 198 MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; 199 data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; 200 data |= DOMAIN_OUTER_SHAREABLE << 201 MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; 202 mmio_write_32(MVEBU_AXI_ATTR_REG(index), data); 203 } 204 } 205 } 206 207 static void misc_soc_configurations(void) 208 { 209 uint32_t reg; 210 211 /* Enable 48-bit VA */ 212 mmio_setbits_32(DSS_CR0, DVM_48BIT_VA_ENABLE); 213 214 /* Un-mask Watchdog reset from influencing the SYSRST_OUTn. 215 * Otherwise, upon WD timeout, the WD reset signal won't trigger reset 216 */ 217 reg = mmio_read_32(MVEBU_SYSRST_OUT_CONFIG_REG); 218 reg &= ~(WD_MASK_SYS_RST_OUT); 219 mmio_write_32(MVEBU_SYSRST_OUT_CONFIG_REG, reg); 220 } 221 222 /* 223 * By default all external CPs start with configuration address space set to 224 * 0xf200_0000. To overcome this issue, go in the loop and initialize the 225 * CP one by one, using temporary window configuration which allows to access 226 * each CP and update its configuration space according to decoding 227 * windows scheme defined for each platform. 228 */ 229 void update_cp110_default_win(int cp_id) 230 { 231 int mci_id = cp_id - 1; 232 uintptr_t cp110_base, cp110_temp_base; 233 234 /* CP110 default configuration address space */ 235 cp110_temp_base = MVEBU_AP_IO_BASE(MVEBU_AP0); 236 237 struct addr_map_win iowin_temp_win = { 238 .base_addr = cp110_temp_base, 239 .win_size = MVEBU_CP_OFFSET, 240 }; 241 242 iowin_temp_win.target_id = mci_id; 243 iow_temp_win_insert(0, &iowin_temp_win, 1); 244 245 /* Calculate the new CP110 - base address */ 246 cp110_base = MVEBU_CP_REGS_BASE(cp_id); 247 /* Go and update the CP110 configuration address space */ 248 iob_cfg_space_update(0, cp_id, cp110_temp_base, cp110_base); 249 250 /* Remove the temporary IO-WIN window */ 251 iow_temp_win_remove(0, &iowin_temp_win, 1); 252 } 253 254 void ap_init(void) 255 { 256 /* Setup Aurora2. */ 257 init_aurora2(); 258 259 /* configure MCI mapping */ 260 mci_remap_indirect_access_base(); 261 262 /* configure IO_WIN windows */ 263 init_io_win(MVEBU_AP0); 264 265 /* configure CCU windows */ 266 init_ccu(MVEBU_AP0); 267 268 /* configure the SMMU */ 269 setup_smmu(); 270 271 /* Open AP incoming access for all masters */ 272 ap_sec_masters_access_en(1); 273 274 /* configure axi for AP */ 275 ap807_axi_attr_init(); 276 277 /* misc configuration of the SoC */ 278 misc_soc_configurations(); 279 } 280 281 static void ap807_dram_phy_access_config(void) 282 { 283 uint32_t reg_val; 284 /* Update DSS port access permission to DSS_PHY */ 285 reg_val = mmio_read_32(DSS_SCR_REG); 286 reg_val &= ~(DSS_PPROT_MASK << DSS_PPROT_OFFS); 287 reg_val |= ((DSS_PPROT_PRIV_SECURE_DATA & DSS_PPROT_MASK) << 288 DSS_PPROT_OFFS); 289 mmio_write_32(DSS_SCR_REG, reg_val); 290 } 291 292 void ap_ble_init(void) 293 { 294 /* Enable DSS port */ 295 ap807_dram_phy_access_config(); 296 } 297 298 int ap_get_count(void) 299 { 300 return 1; 301 } 302 303 304