xref: /rk3399_ARM-atf/drivers/marvell/iob.c (revision 27528f72015091df7b5d0a80ceb859e283e45c95)
1c0474d58SKonstantin Porotchkin /*
2c0474d58SKonstantin Porotchkin  * Copyright (C) 2016 - 2018 Marvell International Ltd.
3c0474d58SKonstantin Porotchkin  *
4c0474d58SKonstantin Porotchkin  * SPDX-License-Identifier:     BSD-3-Clause
5c0474d58SKonstantin Porotchkin  * https://spdx.org/licenses
6c0474d58SKonstantin Porotchkin  */
7c0474d58SKonstantin Porotchkin 
8c0474d58SKonstantin Porotchkin /* IOW unit device driver for Marvell CP110 and CP115 SoCs */
9c0474d58SKonstantin Porotchkin 
10c0474d58SKonstantin Porotchkin #include <arch_helpers.h>
1109d40e0eSAntonio Nino Diaz #include <common/debug.h>
1209d40e0eSAntonio Nino Diaz #include <drivers/marvell/iob.h>
1309d40e0eSAntonio Nino Diaz #include <lib/mmio.h>
1409d40e0eSAntonio Nino Diaz 
1509d40e0eSAntonio Nino Diaz #include <armada_common.h>
16c0474d58SKonstantin Porotchkin #include <mvebu.h>
17c0474d58SKonstantin Porotchkin #include <mvebu_def.h>
18c0474d58SKonstantin Porotchkin 
19c0474d58SKonstantin Porotchkin #if LOG_LEVEL >= LOG_LEVEL_INFO
20c0474d58SKonstantin Porotchkin #define DEBUG_ADDR_MAP
21c0474d58SKonstantin Porotchkin #endif
22c0474d58SKonstantin Porotchkin 
23c0474d58SKonstantin Porotchkin #define MVEBU_IOB_OFFSET		(0x190000)
24c0474d58SKonstantin Porotchkin #define MVEBU_IOB_MAX_WINS		16
25c0474d58SKonstantin Porotchkin 
26c0474d58SKonstantin Porotchkin /* common defines */
27c0474d58SKonstantin Porotchkin #define WIN_ENABLE_BIT			(0x1)
28c0474d58SKonstantin Porotchkin /* Physical address of the base of the window = {AddrLow[19:0],20`h0} */
29c0474d58SKonstantin Porotchkin #define ADDRESS_SHIFT			(20 - 4)
30c0474d58SKonstantin Porotchkin #define ADDRESS_MASK			(0xFFFFFFF0)
31c0474d58SKonstantin Porotchkin #define IOB_WIN_ALIGNMENT		(0x100000)
32c0474d58SKonstantin Porotchkin 
33c0474d58SKonstantin Porotchkin /* IOB registers */
34c0474d58SKonstantin Porotchkin #define IOB_WIN_CR_OFFSET(win)		(iob_base + 0x0 + (0x20 * win))
35c0474d58SKonstantin Porotchkin #define IOB_TARGET_ID_OFFSET		(8)
36c0474d58SKonstantin Porotchkin #define IOB_TARGET_ID_MASK		(0xF)
37c0474d58SKonstantin Porotchkin 
38c0474d58SKonstantin Porotchkin #define IOB_WIN_SCR_OFFSET(win)		(iob_base + 0x4 + (0x20 * win))
39c0474d58SKonstantin Porotchkin #define IOB_WIN_ENA_CTRL_WRITE_SECURE	(0x1)
40c0474d58SKonstantin Porotchkin #define IOB_WIN_ENA_CTRL_READ_SECURE	(0x2)
41c0474d58SKonstantin Porotchkin #define IOB_WIN_ENA_WRITE_SECURE	(0x4)
42c0474d58SKonstantin Porotchkin #define IOB_WIN_ENA_READ_SECURE		(0x8)
43c0474d58SKonstantin Porotchkin 
44c0474d58SKonstantin Porotchkin #define IOB_WIN_ALR_OFFSET(win)		(iob_base + 0x8 + (0x20 * win))
45c0474d58SKonstantin Porotchkin #define IOB_WIN_AHR_OFFSET(win)		(iob_base + 0xC + (0x20 * win))
46c0474d58SKonstantin Porotchkin 
47*27528f72SOfer Heifetz #define IOB_WIN_DIOB_CR_OFFSET(win)	(iob_base + 0x10 + (0x20 * win))
48*27528f72SOfer Heifetz #define IOB_WIN_XOR0_DIOB_EN		BIT(0)
49*27528f72SOfer Heifetz #define IOB_WIN_XOR1_DIOB_EN		BIT(1)
50*27528f72SOfer Heifetz 
51c0474d58SKonstantin Porotchkin uintptr_t iob_base;
52c0474d58SKonstantin Porotchkin 
53c0474d58SKonstantin Porotchkin static void iob_win_check(struct addr_map_win *win, uint32_t win_num)
54c0474d58SKonstantin Porotchkin {
55c0474d58SKonstantin Porotchkin 	/* check if address is aligned to the size */
56c0474d58SKonstantin Porotchkin 	if (IS_NOT_ALIGN(win->base_addr, IOB_WIN_ALIGNMENT)) {
57c0474d58SKonstantin Porotchkin 		win->base_addr = ALIGN_UP(win->base_addr, IOB_WIN_ALIGNMENT);
58c0474d58SKonstantin Porotchkin 		ERROR("Window %d: base address unaligned to 0x%x\n",
59c0474d58SKonstantin Porotchkin 		      win_num, IOB_WIN_ALIGNMENT);
6039b6cc66SAntonio Nino Diaz 		printf("Align up the base address to 0x%llx\n",
61c0474d58SKonstantin Porotchkin 		       win->base_addr);
62c0474d58SKonstantin Porotchkin 	}
63c0474d58SKonstantin Porotchkin 
64c0474d58SKonstantin Porotchkin 	/* size parameter validity check */
65c0474d58SKonstantin Porotchkin 	if (IS_NOT_ALIGN(win->win_size, IOB_WIN_ALIGNMENT)) {
66c0474d58SKonstantin Porotchkin 		win->win_size = ALIGN_UP(win->win_size, IOB_WIN_ALIGNMENT);
67c0474d58SKonstantin Porotchkin 		ERROR("Window %d: window size unaligned to 0x%x\n", win_num,
68c0474d58SKonstantin Porotchkin 		      IOB_WIN_ALIGNMENT);
6939b6cc66SAntonio Nino Diaz 		printf("Aligning size to 0x%llx\n", win->win_size);
70c0474d58SKonstantin Porotchkin 	}
71c0474d58SKonstantin Porotchkin }
72c0474d58SKonstantin Porotchkin 
73c0474d58SKonstantin Porotchkin static void iob_enable_win(struct addr_map_win *win, uint32_t win_id)
74c0474d58SKonstantin Porotchkin {
75c0474d58SKonstantin Porotchkin 	uint32_t iob_win_reg;
76c0474d58SKonstantin Porotchkin 	uint32_t alr, ahr;
77c0474d58SKonstantin Porotchkin 	uint64_t end_addr;
78*27528f72SOfer Heifetz 	uint32_t reg_en;
79*27528f72SOfer Heifetz 
80*27528f72SOfer Heifetz 	/* move XOR (DMA) to use WIN1 which is used for PCI-EP address space */
81*27528f72SOfer Heifetz 	reg_en = IOB_WIN_XOR0_DIOB_EN | IOB_WIN_XOR1_DIOB_EN;
82*27528f72SOfer Heifetz 	iob_win_reg = mmio_read_32(IOB_WIN_DIOB_CR_OFFSET(0));
83*27528f72SOfer Heifetz 	iob_win_reg &= ~reg_en;
84*27528f72SOfer Heifetz 	mmio_write_32(IOB_WIN_DIOB_CR_OFFSET(0), iob_win_reg);
85*27528f72SOfer Heifetz 
86*27528f72SOfer Heifetz 	iob_win_reg = mmio_read_32(IOB_WIN_DIOB_CR_OFFSET(1));
87*27528f72SOfer Heifetz 	iob_win_reg |= reg_en;
88*27528f72SOfer Heifetz 	mmio_write_32(IOB_WIN_DIOB_CR_OFFSET(1), iob_win_reg);
89c0474d58SKonstantin Porotchkin 
90c0474d58SKonstantin Porotchkin 	end_addr = (win->base_addr + win->win_size - 1);
91c0474d58SKonstantin Porotchkin 	alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
92c0474d58SKonstantin Porotchkin 	ahr = (uint32_t)((end_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
93c0474d58SKonstantin Porotchkin 
94c0474d58SKonstantin Porotchkin 	mmio_write_32(IOB_WIN_ALR_OFFSET(win_id), alr);
95c0474d58SKonstantin Porotchkin 	mmio_write_32(IOB_WIN_AHR_OFFSET(win_id), ahr);
96c0474d58SKonstantin Porotchkin 
97c0474d58SKonstantin Porotchkin 	iob_win_reg = WIN_ENABLE_BIT;
98c0474d58SKonstantin Porotchkin 	iob_win_reg |= (win->target_id & IOB_TARGET_ID_MASK)
99c0474d58SKonstantin Porotchkin 		       << IOB_TARGET_ID_OFFSET;
100c0474d58SKonstantin Porotchkin 	mmio_write_32(IOB_WIN_CR_OFFSET(win_id), iob_win_reg);
101c0474d58SKonstantin Porotchkin 
102c0474d58SKonstantin Porotchkin }
103c0474d58SKonstantin Porotchkin 
104c0474d58SKonstantin Porotchkin #ifdef DEBUG_ADDR_MAP
105c0474d58SKonstantin Porotchkin static void dump_iob(void)
106c0474d58SKonstantin Porotchkin {
107c0474d58SKonstantin Porotchkin 	uint32_t win_id, win_cr, alr, ahr;
108c0474d58SKonstantin Porotchkin 	uint8_t target_id;
109c0474d58SKonstantin Porotchkin 	uint64_t start, end;
110c0474d58SKonstantin Porotchkin 	char *iob_target_name[IOB_MAX_TID] = {
111c0474d58SKonstantin Porotchkin 		"CFG  ", "MCI0 ", "PEX1 ", "PEX2 ",
112c0474d58SKonstantin Porotchkin 		"PEX0 ", "NAND ", "RUNIT", "MCI1 " };
113c0474d58SKonstantin Porotchkin 
114c0474d58SKonstantin Porotchkin 	/* Dump all IOB windows */
11539b6cc66SAntonio Nino Diaz 	printf("bank  id target  start              end\n");
11639b6cc66SAntonio Nino Diaz 	printf("----------------------------------------------------\n");
117c0474d58SKonstantin Porotchkin 	for (win_id = 0; win_id < MVEBU_IOB_MAX_WINS; win_id++) {
118c0474d58SKonstantin Porotchkin 		win_cr = mmio_read_32(IOB_WIN_CR_OFFSET(win_id));
119c0474d58SKonstantin Porotchkin 		if (win_cr & WIN_ENABLE_BIT) {
120c0474d58SKonstantin Porotchkin 			target_id = (win_cr >> IOB_TARGET_ID_OFFSET) &
121c0474d58SKonstantin Porotchkin 				     IOB_TARGET_ID_MASK;
122c0474d58SKonstantin Porotchkin 			alr = mmio_read_32(IOB_WIN_ALR_OFFSET(win_id));
123c0474d58SKonstantin Porotchkin 			start = ((uint64_t)alr << ADDRESS_SHIFT);
124c0474d58SKonstantin Porotchkin 			if (win_id != 0) {
125c0474d58SKonstantin Porotchkin 				ahr = mmio_read_32(IOB_WIN_AHR_OFFSET(win_id));
126c0474d58SKonstantin Porotchkin 				end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT);
127c0474d58SKonstantin Porotchkin 			} else {
128c0474d58SKonstantin Porotchkin 				/* Window #0 size is hardcoded to 16MB, as it's
129c0474d58SKonstantin Porotchkin 				 * reserved for CP configuration space.
130c0474d58SKonstantin Porotchkin 				 */
131c0474d58SKonstantin Porotchkin 				end = start + (16 << 20);
132c0474d58SKonstantin Porotchkin 			}
13339b6cc66SAntonio Nino Diaz 			printf("iob   %02d %s   0x%016llx 0x%016llx\n",
134c0474d58SKonstantin Porotchkin 			       win_id, iob_target_name[target_id],
135c0474d58SKonstantin Porotchkin 			       start, end);
136c0474d58SKonstantin Porotchkin 		}
137c0474d58SKonstantin Porotchkin 	}
138c0474d58SKonstantin Porotchkin }
139c0474d58SKonstantin Porotchkin #endif
140c0474d58SKonstantin Porotchkin 
141c0474d58SKonstantin Porotchkin void iob_cfg_space_update(int ap_idx, int cp_idx, uintptr_t base,
142c0474d58SKonstantin Porotchkin 			  uintptr_t new_base)
143c0474d58SKonstantin Porotchkin {
144c0474d58SKonstantin Porotchkin 	debug_enter();
145c0474d58SKonstantin Porotchkin 
146c0474d58SKonstantin Porotchkin 	iob_base = base + MVEBU_IOB_OFFSET;
147c0474d58SKonstantin Porotchkin 
148c0474d58SKonstantin Porotchkin 	NOTICE("Change the base address of AP%d-CP%d to %lx\n",
149c0474d58SKonstantin Porotchkin 	       ap_idx, cp_idx, new_base);
150c0474d58SKonstantin Porotchkin 	mmio_write_32(IOB_WIN_ALR_OFFSET(0), new_base >> ADDRESS_SHIFT);
151c0474d58SKonstantin Porotchkin 
152c0474d58SKonstantin Porotchkin 	iob_base = new_base + MVEBU_IOB_OFFSET;
153c0474d58SKonstantin Porotchkin 
154c0474d58SKonstantin Porotchkin 	/* Make sure the address was configured by the CPU before
155c0474d58SKonstantin Porotchkin 	 * any possible access to the CP.
156c0474d58SKonstantin Porotchkin 	 */
157c0474d58SKonstantin Porotchkin 	dsb();
158c0474d58SKonstantin Porotchkin 
159c0474d58SKonstantin Porotchkin 	debug_exit();
160c0474d58SKonstantin Porotchkin }
161c0474d58SKonstantin Porotchkin 
162c0474d58SKonstantin Porotchkin int init_iob(uintptr_t base)
163c0474d58SKonstantin Porotchkin {
164c0474d58SKonstantin Porotchkin 	struct addr_map_win *win;
165c0474d58SKonstantin Porotchkin 	uint32_t win_id, win_reg;
166c0474d58SKonstantin Porotchkin 	uint32_t win_count;
167c0474d58SKonstantin Porotchkin 
168c0474d58SKonstantin Porotchkin 	INFO("Initializing IOB Address decoding\n");
169c0474d58SKonstantin Porotchkin 
170c0474d58SKonstantin Porotchkin 	/* Get the base address of the address decoding MBUS */
171c0474d58SKonstantin Porotchkin 	iob_base = base + MVEBU_IOB_OFFSET;
172c0474d58SKonstantin Porotchkin 
173c0474d58SKonstantin Porotchkin 	/* Get the array of the windows and fill the map data */
174c0474d58SKonstantin Porotchkin 	marvell_get_iob_memory_map(&win, &win_count, base);
175c0474d58SKonstantin Porotchkin 	if (win_count <= 0) {
176c0474d58SKonstantin Porotchkin 		INFO("no windows configurations found\n");
177c0474d58SKonstantin Porotchkin 		return 0;
178c0474d58SKonstantin Porotchkin 	} else if (win_count > (MVEBU_IOB_MAX_WINS - 1)) {
179c0474d58SKonstantin Porotchkin 		ERROR("IOB mem map array > than max available windows (%d)\n",
180c0474d58SKonstantin Porotchkin 		      MVEBU_IOB_MAX_WINS);
181c0474d58SKonstantin Porotchkin 		win_count = MVEBU_IOB_MAX_WINS;
182c0474d58SKonstantin Porotchkin 	}
183c0474d58SKonstantin Porotchkin 
184c0474d58SKonstantin Porotchkin 	/* disable all IOB windows, start from win_id = 1
185c0474d58SKonstantin Porotchkin 	 * because can't disable internal register window
186c0474d58SKonstantin Porotchkin 	 */
187c0474d58SKonstantin Porotchkin 	for (win_id = 1; win_id < MVEBU_IOB_MAX_WINS; win_id++) {
188c0474d58SKonstantin Porotchkin 		win_reg = mmio_read_32(IOB_WIN_CR_OFFSET(win_id));
189c0474d58SKonstantin Porotchkin 		win_reg &= ~WIN_ENABLE_BIT;
190c0474d58SKonstantin Porotchkin 		mmio_write_32(IOB_WIN_CR_OFFSET(win_id), win_reg);
191c0474d58SKonstantin Porotchkin 
192c0474d58SKonstantin Porotchkin 		win_reg = ~IOB_WIN_ENA_CTRL_WRITE_SECURE;
193c0474d58SKonstantin Porotchkin 		win_reg &= ~IOB_WIN_ENA_CTRL_READ_SECURE;
194c0474d58SKonstantin Porotchkin 		win_reg &= ~IOB_WIN_ENA_WRITE_SECURE;
195c0474d58SKonstantin Porotchkin 		win_reg &= ~IOB_WIN_ENA_READ_SECURE;
196c0474d58SKonstantin Porotchkin 		mmio_write_32(IOB_WIN_SCR_OFFSET(win_id), win_reg);
197c0474d58SKonstantin Porotchkin 	}
198c0474d58SKonstantin Porotchkin 
199c0474d58SKonstantin Porotchkin 	for (win_id = 1; win_id < win_count + 1; win_id++, win++) {
200c0474d58SKonstantin Porotchkin 		iob_win_check(win, win_id);
201c0474d58SKonstantin Porotchkin 		iob_enable_win(win, win_id);
202c0474d58SKonstantin Porotchkin 	}
203c0474d58SKonstantin Porotchkin 
204c0474d58SKonstantin Porotchkin #ifdef DEBUG_ADDR_MAP
205c0474d58SKonstantin Porotchkin 	dump_iob();
206c0474d58SKonstantin Porotchkin #endif
207c0474d58SKonstantin Porotchkin 
208c0474d58SKonstantin Porotchkin 	INFO("Done IOB Address decoding Initializing\n");
209c0474d58SKonstantin Porotchkin 
210c0474d58SKonstantin Porotchkin 	return 0;
211c0474d58SKonstantin Porotchkin }
212