1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <errno.h> 9 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/spinlock.h> 14 15 #include <mvebu.h> 16 #include <mvebu_def.h> 17 18 #include "phy-comphy-3700.h" 19 #include "phy-comphy-common.h" 20 21 /* 22 * COMPHY_INDIRECT_REG points to ahci address space but the ahci region used in 23 * Linux is up to 0x178 so none will access it from Linux in runtime 24 * concurrently. 25 */ 26 #define COMPHY_INDIRECT_REG (MVEBU_REGS_BASE + 0xE0178) 27 28 /* The USB3_GBE1_PHY range is above USB3 registers used in dts */ 29 #define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000) 30 #define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000) 31 32 /* 33 * Below address in used only for reading, therefore no problem with concurrent 34 * Linux access. 35 */ 36 #define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8) 37 #define MVEBU_XTAL_MODE_MASK BIT(9) 38 #define MVEBU_XTAL_MODE_OFFS 9 39 #define MVEBU_XTAL_CLOCK_25MHZ 0x0 40 41 struct sgmii_phy_init_data_fix { 42 uint16_t addr; 43 uint16_t value; 44 }; 45 46 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ 47 static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = { 48 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000}, 49 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030}, 50 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC}, 51 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA}, 52 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550}, 53 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0}, 54 {0x104, 0x0C10} 55 }; 56 57 /* 40M1G25 mode init data */ 58 static uint16_t sgmii_phy_init[512] = { 59 /* 0 1 2 3 4 5 6 7 */ 60 /*-----------------------------------------------------------*/ 61 /* 8 9 A B C D E F */ 62 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ 63 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ 64 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ 65 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ 66 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ 67 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ 68 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 69 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ 70 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ 71 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ 72 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ 73 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ 74 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ 75 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ 76 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ 77 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ 78 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ 79 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ 80 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ 81 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ 82 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ 83 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ 84 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ 85 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ 86 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ 87 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ 88 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ 89 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ 90 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ 91 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ 92 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ 93 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ 94 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ 95 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ 96 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ 97 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ 98 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ 99 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ 100 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ 101 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ 102 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ 103 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ 104 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ 105 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ 106 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ 107 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ 108 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ 109 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ 110 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ 111 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ 112 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ 113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ 114 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ 115 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ 116 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ 117 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ 118 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ 119 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ 120 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ 121 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ 122 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ 123 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ 124 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ 125 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ 126 }; 127 128 /* returns reference clock in MHz (25 or 40) */ 129 static uint32_t get_ref_clk(void) 130 { 131 uint32_t val; 132 133 val = (mmio_read_32(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >> 134 MVEBU_XTAL_MODE_OFFS; 135 136 if (val == MVEBU_XTAL_CLOCK_25MHZ) 137 return 25; 138 else 139 return 40; 140 } 141 142 /* PHY selector configures with corresponding modes */ 143 static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index, 144 uint32_t comphy_mode) 145 { 146 uint32_t reg; 147 int mode = COMPHY_GET_MODE(comphy_mode); 148 149 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG); 150 switch (mode) { 151 case (COMPHY_SATA_MODE): 152 /* SATA must be in Lane2 */ 153 if (comphy_index == COMPHY_LANE2) 154 reg &= ~COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 155 else 156 goto error; 157 break; 158 159 case (COMPHY_SGMII_MODE): 160 case (COMPHY_HS_SGMII_MODE): 161 if (comphy_index == COMPHY_LANE0) 162 reg &= ~COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 163 else if (comphy_index == COMPHY_LANE1) 164 reg &= ~COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 165 else 166 goto error; 167 break; 168 169 case (COMPHY_USB3H_MODE): 170 case (COMPHY_USB3D_MODE): 171 case (COMPHY_USB3_MODE): 172 if (comphy_index == COMPHY_LANE2) 173 reg |= COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 174 else if (comphy_index == COMPHY_LANE0) 175 reg |= COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 176 else 177 goto error; 178 break; 179 180 case (COMPHY_PCIE_MODE): 181 /* PCIE must be in Lane1 */ 182 if (comphy_index == COMPHY_LANE1) 183 reg |= COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 184 else 185 goto error; 186 break; 187 188 default: 189 goto error; 190 } 191 192 mmio_write_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG, reg); 193 return; 194 error: 195 ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index, mode); 196 } 197 198 /* It is only used for SATA and USB3 on comphy lane2. */ 199 static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data, 200 uint16_t mask, int mode) 201 { 202 /* 203 * When Lane 2 PHY is for USB3, access the PHY registers 204 * through indirect Address and Data registers: 205 * INDIR_ACC_PHY_ADDR (RD00E0178h [31:0]), 206 * INDIR_ACC_PHY_DATA (RD00E017Ch [31:0]), 207 * within the SATA Host Controller registers, Lane 2 base register 208 * offset is 0x200 209 */ 210 if (mode == COMPHY_UNUSED) 211 return; 212 213 if (mode == COMPHY_SATA_MODE) 214 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, offset); 215 else 216 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, 217 offset + USB3PHY_LANE2_REG_BASE_OFFSET); 218 219 reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask); 220 } 221 222 /* It is only used USB3 direct access not on comphy lane2. */ 223 static void comphy_usb3_set_direct(uintptr_t addr, uint32_t reg_offset, 224 uint16_t data, uint16_t mask, int mode) 225 { 226 reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask); 227 } 228 229 static void comphy_sgmii_phy_init(uint32_t comphy_index, uint32_t mode, 230 uintptr_t sd_ip_addr) 231 { 232 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix); 233 int addr, fix_idx; 234 uint16_t val; 235 236 fix_idx = 0; 237 for (addr = 0; addr < 512; addr++) { 238 /* 239 * All PHY register values are defined in full for 3.125Gbps 240 * SERDES speed. The values required for 1.25 Gbps are almost 241 * the same and only few registers should be "fixed" in 242 * comparison to 3.125 Gbps values. These register values are 243 * stored in "sgmii_phy_init_fix" array. 244 */ 245 if ((mode != COMPHY_SGMII_MODE) && 246 (sgmii_phy_init_fix[fix_idx].addr == addr)) { 247 /* Use new value */ 248 val = sgmii_phy_init_fix[fix_idx].value; 249 if (fix_idx < fix_arr_sz) 250 fix_idx++; 251 } else { 252 val = sgmii_phy_init[addr]; 253 } 254 255 reg_set16(SGMIIPHY_ADDR(addr, sd_ip_addr), val, 0xFFFF); 256 } 257 } 258 259 static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index, 260 uint32_t comphy_mode) 261 { 262 int ret = 0; 263 uint32_t offset, data = 0, ref_clk; 264 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 265 int mode = COMPHY_GET_MODE(comphy_mode); 266 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 267 268 debug_enter(); 269 270 /* Configure phy selector for SATA */ 271 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 272 273 /* Clear phy isolation mode to make it work in normal mode */ 274 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 275 comphy_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE, 276 mode); 277 278 /* 0. Check the Polarity invert bits */ 279 if (invert & COMPHY_POLARITY_TXD_INVERT) 280 data |= TXD_INVERT_BIT; 281 if (invert & COMPHY_POLARITY_RXD_INVERT) 282 data |= RXD_INVERT_BIT; 283 284 offset = COMPHY_SYNC_PATTERN_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 285 comphy_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT | 286 RXD_INVERT_BIT, mode); 287 288 /* 1. Select 40-bit data width width */ 289 offset = COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET; 290 comphy_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT, 291 SEL_DATA_WIDTH_MASK, mode); 292 293 /* 2. Select reference clock(25M) and PHY mode (SATA) */ 294 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 295 if (get_ref_clk() == 40) 296 ref_clk = REF_CLOCK_SPEED_40M; 297 else 298 ref_clk = REF_CLOCK_SPEED_25M; 299 300 comphy_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA, 301 REF_FREF_SEL_MASK | PHY_MODE_MASK, mode); 302 303 /* 3. Use maximum PLL rate (no power save) */ 304 offset = COMPHY_KVCO_CAL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 305 comphy_set_indirect(comphy_indir_regs, offset, USE_MAX_PLL_RATE_BIT, 306 USE_MAX_PLL_RATE_BIT, mode); 307 308 /* 4. Reset reserved bit */ 309 comphy_set_indirect(comphy_indir_regs, COMPHY_RESERVED_REG, 0, 310 PHYCTRL_FRM_PIN_BIT, mode); 311 312 /* 5. Set vendor-specific configuration (It is done in sata driver) */ 313 /* XXX: in U-Boot below sequence was executed in this place, in Linux 314 * not. Now it is done only in U-Boot before this comphy 315 * initialization - tests shows that it works ok, but in case of any 316 * future problem it is left for reference. 317 * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff); 318 * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6)); 319 */ 320 321 /* Wait for > 55 us to allow PLL be enabled */ 322 udelay(PLL_SET_DELAY_US); 323 324 /* Polling status */ 325 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 326 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); 327 328 ret = polling_with_timeout(comphy_indir_regs + 329 COMPHY_LANE2_INDIR_DATA_OFFSET, 330 PLL_READY_TX_BIT, PLL_READY_TX_BIT, 331 COMPHY_PLL_TIMEOUT, REG_32BIT); 332 333 debug_exit(); 334 335 return ret; 336 } 337 338 static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index, 339 uint32_t comphy_mode) 340 { 341 int ret = 0; 342 uint32_t mask, data, offset; 343 uintptr_t sd_ip_addr; 344 int mode = COMPHY_GET_MODE(comphy_mode); 345 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 346 347 debug_enter(); 348 349 /* Set selector */ 350 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 351 352 /* Serdes IP Base address 353 * COMPHY Lane0 -- USB3/GBE1 354 * COMPHY Lane1 -- PCIe/GBE0 355 */ 356 if (comphy_index == COMPHY_LANE0) { 357 /* Get usb3 and gbe */ 358 sd_ip_addr = USB3_GBE1_PHY; 359 } else 360 sd_ip_addr = COMPHY_SD_ADDR; 361 362 /* 363 * 1. Reset PHY by setting PHY input port PIN_RESET=1. 364 * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep 365 * PHY TXP/TXN output to idle state during PHY initialization 366 * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. 367 */ 368 data = PIN_PU_IVEREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT; 369 mask = PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | 370 PIN_PU_TX_BIT; 371 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); 372 reg_set(offset, data, mask); 373 374 /* 4. Release reset to the PHY by setting PIN_RESET=0. */ 375 data = 0; 376 mask = PIN_RESET_COMPHY_BIT; 377 reg_set(offset, data, mask); 378 379 /* 380 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY 381 * bit rate 382 */ 383 if (mode == COMPHY_SGMII_MODE) { 384 /* SGMII 1G, SerDes speed 1.25G */ 385 data |= SD_SPEED_1_25_G << GEN_RX_SEL_OFFSET; 386 data |= SD_SPEED_1_25_G << GEN_TX_SEL_OFFSET; 387 } else if (mode == COMPHY_HS_SGMII_MODE) { 388 /* HS SGMII (2.5G), SerDes speed 3.125G */ 389 data |= SD_SPEED_2_5_G << GEN_RX_SEL_OFFSET; 390 data |= SD_SPEED_2_5_G << GEN_TX_SEL_OFFSET; 391 } else { 392 /* Other rates are not supported */ 393 ERROR("unsupported SGMII speed on comphy lane%d\n", 394 comphy_index); 395 return -EINVAL; 396 } 397 mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK; 398 reg_set(offset, data, mask); 399 400 /* 401 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then 402 * start SW programming. 403 */ 404 mdelay(10); 405 406 /* 7. Program COMPHY register PHY_MODE */ 407 data = PHY_MODE_SGMII; 408 mask = PHY_MODE_MASK; 409 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 410 411 /* 412 * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK 413 * source 414 */ 415 data = 0; 416 mask = PHY_REF_CLK_SEL; 417 reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0_ADDR, sd_ip_addr), data, mask); 418 419 /* 420 * 9. Set correct reference clock frequency in COMPHY register 421 * REF_FREF_SEL. 422 */ 423 if (get_ref_clk() == 40) 424 data = REF_CLOCK_SPEED_50M; 425 else 426 data = REF_CLOCK_SPEED_25M; 427 428 mask = REF_FREF_SEL_MASK; 429 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 430 431 /* 10. Program COMPHY register PHY_GEN_MAX[1:0] 432 * This step is mentioned in the flow received from verification team. 433 * However the PHY_GEN_MAX value is only meaningful for other interfaces 434 * (not SGMII). For instance, it selects SATA speed 1.5/3/6 Gbps or PCIe 435 * speed 2.5/5 Gbps 436 */ 437 438 /* 439 * 11. Program COMPHY register SEL_BITS to set correct parallel data 440 * bus width 441 */ 442 data = DATA_WIDTH_10BIT; 443 mask = SEL_DATA_WIDTH_MASK; 444 reg_set16(SGMIIPHY_ADDR(COMPHY_LOOPBACK_REG0, sd_ip_addr), data, mask); 445 446 /* 447 * 12. As long as DFE function needs to be enabled in any mode, 448 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F 449 * for real chip during COMPHY power on. 450 * The step 14 exists (and empty) in the original initialization flow 451 * obtained from the verification team. According to the functional 452 * specification DFE_UPDATE_EN already has the default value 0x3F 453 */ 454 455 /* 456 * 13. Program COMPHY GEN registers. 457 * These registers should be programmed based on the lab testing result 458 * to achieve optimal performance. Please contact the CEA group to get 459 * the related GEN table during real chip bring-up. We only required to 460 * run though the entire registers programming flow defined by 461 * "comphy_sgmii_phy_init" when the REF clock is 40 MHz. For REF clock 462 * 25 MHz the default values stored in PHY registers are OK. 463 */ 464 debug("Running C-DPI phy init %s mode\n", 465 mode == COMPHY_HS_SGMII_MODE ? "2G5" : "1G"); 466 if (get_ref_clk() == 40) 467 comphy_sgmii_phy_init(comphy_index, mode, sd_ip_addr); 468 469 /* 470 * 14. [Simulation Only] should not be used for real chip. 471 * By pass power up calibration by programming EXT_FORCE_CAL_DONE 472 * (R02h[9]) to 1 to shorten COMPHY simulation time. 473 */ 474 475 /* 476 * 15. [Simulation Only: should not be used for real chip] 477 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training 478 * simulation time. 479 */ 480 481 /* 482 * 16. Check the PHY Polarity invert bit 483 */ 484 data = 0x0; 485 if (invert & COMPHY_POLARITY_TXD_INVERT) 486 data |= TXD_INVERT_BIT; 487 if (invert & COMPHY_POLARITY_RXD_INVERT) 488 data |= RXD_INVERT_BIT; 489 reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, 0); 490 491 /* 492 * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to 493 * start PHY power up sequence. All the PHY register programming should 494 * be done before PIN_PU_PLL=1. There should be no register programming 495 * for normal PHY operation from this point. 496 */ 497 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 498 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT, 499 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT); 500 501 /* 502 * 18. Wait for PHY power up sequence to finish by checking output ports 503 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. 504 */ 505 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 506 COMPHY_PHY_STATUS_OFFSET(comphy_index), 507 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 508 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 509 COMPHY_PLL_TIMEOUT, REG_32BIT); 510 if (ret) 511 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 512 513 /* 514 * 19. Set COMPHY input port PIN_TX_IDLE=0 515 */ 516 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 517 0x0, PIN_TX_IDLE_BIT); 518 519 /* 520 * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To 521 * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the 522 * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to 523 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please 524 * refer to RX initialization part for details. 525 */ 526 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 527 PHY_RX_INIT_BIT, 0x0); 528 529 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 530 COMPHY_PHY_STATUS_OFFSET(comphy_index), 531 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 532 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 533 COMPHY_PLL_TIMEOUT, REG_32BIT); 534 if (ret) 535 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 536 537 538 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 539 COMPHY_PHY_STATUS_OFFSET(comphy_index), 540 PHY_RX_INIT_DONE_BIT, PHY_RX_INIT_DONE_BIT, 541 COMPHY_PLL_TIMEOUT, REG_32BIT); 542 if (ret) 543 ERROR("Failed to init RX of SGMII PHY %d\n", comphy_index); 544 545 debug_exit(); 546 547 return ret; 548 } 549 550 static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index, 551 uint32_t comphy_mode) 552 { 553 int ret = 0; 554 uintptr_t reg_base = 0; 555 uint32_t mask, data, addr, cfg, ref_clk; 556 void (*usb3_reg_set)(uintptr_t addr, uint32_t reg_offset, uint16_t data, 557 uint16_t mask, int mode); 558 int mode = COMPHY_GET_MODE(comphy_mode); 559 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 560 561 debug_enter(); 562 563 /* Set phy seclector */ 564 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 565 566 /* Set usb3 reg access func, Lane2 is indirect access */ 567 if (comphy_index == COMPHY_LANE2) { 568 usb3_reg_set = &comphy_set_indirect; 569 reg_base = COMPHY_INDIRECT_REG; 570 } else { 571 /* Get the direct access register resource and map */ 572 usb3_reg_set = &comphy_usb3_set_direct; 573 reg_base = USB3_GBE1_PHY; 574 } 575 576 /* 577 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The 578 * register belong to UTMI module, so it is set in UTMI phy driver. 579 */ 580 581 /* 582 * 1. Set PRD_TXDEEMPH (3.5db de-emph) 583 */ 584 mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK | 585 CFG_TX_ALIGN_POS_MASK; 586 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK, 587 mask, mode); 588 589 /* 590 * 2. Set BIT0: enable transmitter in high impedance mode 591 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency 592 * Set BIT6: Tx detect Rx at HiZ mode 593 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db 594 * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR register 595 */ 596 mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK | 597 TX_ELEC_IDLE_MODE_EN; 598 data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN; 599 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask, mode); 600 601 /* 602 * 3. Set Spread Spectrum Clock Enabled 603 */ 604 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR, 605 SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN, mode); 606 607 /* 608 * 4. Set Override Margining Controls From the MAC: 609 * Use margining signals from lane configuration 610 */ 611 usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR, 612 MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK, mode); 613 614 /* 615 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles 616 * set Mode Clock Source = PCLK is generated from REFCLK 617 */ 618 usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0, 619 (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE | 620 BUNDLE_SAMPLE_CTRL | PLL_READY_DLY), mode); 621 622 /* 623 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K 624 */ 625 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2, 626 G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK, mode); 627 628 /* 629 * 7. Unset G3 Spread Spectrum Clock Amplitude 630 * set G3 TX and RX Register Master Current Select 631 */ 632 mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK | 633 RSVD_PH03FH_6_0_MASK; 634 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3, 635 G3_VREG_RXTX_MAS_ISET_60U, mask, mode); 636 637 /* 638 * 8. Check crystal jumper setting and program the Power and PLL Control 639 * accordingly Change RX wait 640 */ 641 if (get_ref_clk() == 40) { 642 ref_clk = REF_CLOCK_SPEED_40M; 643 cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT; 644 645 } else { 646 /* 25 MHz */ 647 ref_clk = USB3_REF_CLOCK_SPEED_25M; 648 cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT; 649 } 650 651 mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 652 PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | PHY_MODE_MASK | 653 REF_FREF_SEL_MASK; 654 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 655 PU_TX_INTP_BIT | PU_DFE_BIT | PHY_MODE_USB3 | ref_clk; 656 usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask, mode); 657 658 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 659 CFG_PM_RXDLOZ_WAIT_MASK; 660 data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg; 661 usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask, mode); 662 663 /* 664 * 9. Enable idle sync 665 */ 666 data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN; 667 usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK, 668 mode); 669 670 /* 671 * 10. Enable the output of 500M clock 672 */ 673 data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN; 674 usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK, 675 mode); 676 677 /* 678 * 11. Set 20-bit data width 679 */ 680 usb3_reg_set(reg_base, COMPHY_LOOPBACK_REG0, DATA_WIDTH_20BIT, 681 REG_16_BIT_MASK, mode); 682 683 /* 684 * 12. Override Speed_PLL value and use MAC PLL 685 */ 686 usb3_reg_set(reg_base, COMPHY_KVCO_CAL_CTRL, 687 (SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT), 688 REG_16_BIT_MASK, mode); 689 690 /* 691 * 13. Check the Polarity invert bit 692 */ 693 if (invert & COMPHY_POLARITY_TXD_INVERT) 694 usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, TXD_INVERT_BIT, 695 TXD_INVERT_BIT, mode); 696 if (invert & COMPHY_POLARITY_RXD_INVERT) 697 usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, RXD_INVERT_BIT, 698 RXD_INVERT_BIT, mode); 699 700 /* 701 * 14. Set max speed generation to USB3.0 5Gbps 702 */ 703 usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN_REG, PHY_GEN_USB3_5G, 704 PHY_GEN_MAX_MASK, mode); 705 706 /* 707 * 15. Set capacitor value for FFE gain peaking to 0xF 708 */ 709 usb3_reg_set(reg_base, COMPHY_REG_GEN3_SETTINGS_3, 710 COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK, 711 mode); 712 713 /* 714 * 16. Release SW reset 715 */ 716 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4; 717 usb3_reg_set(reg_base, COMPHY_REG_GLOB_PHY_CTRL0_ADDR, data, 718 REG_16_BIT_MASK, mode); 719 720 /* Wait for > 55 us to allow PCLK be enabled */ 721 udelay(PLL_SET_DELAY_US); 722 723 if (comphy_index == COMPHY_LANE2) { 724 data = COMPHY_LOOPBACK_REG0 + USB3PHY_LANE2_REG_BASE_OFFSET; 725 mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET, 726 data); 727 728 addr = COMPHY_LOOPBACK_REG0 + USB3PHY_LANE2_REG_BASE_OFFSET; 729 ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 730 COMPHY_PLL_TIMEOUT, REG_32BIT); 731 } else { 732 ret = polling_with_timeout(LANE_STATUS1_ADDR(USB3) + reg_base, 733 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 734 COMPHY_PLL_TIMEOUT, REG_16BIT); 735 } 736 if (ret) 737 ERROR("Failed to lock USB3 PLL\n"); 738 739 debug_exit(); 740 741 return ret; 742 } 743 744 static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index, 745 uint32_t comphy_mode) 746 { 747 int ret; 748 uint32_t ref_clk; 749 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 750 751 debug_enter(); 752 753 /* 1. Enable max PLL. */ 754 reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR, 755 USE_MAX_PLL_RATE_EN, 0x0); 756 757 /* 2. Select 20 bit SERDES interface. */ 758 reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR, 759 CFG_SEL_20B, 0); 760 761 /* 3. Force to use reg setting for PCIe mode */ 762 reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR, 763 SEL_BITS_PCIE_FORCE, 0); 764 765 /* 4. Change RX wait */ 766 reg_set16(PWR_MGM_TIM1_ADDR(PCIE) + COMPHY_SD_ADDR, 767 CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT, 768 (CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 769 CFG_PM_RXDLOZ_WAIT_MASK)); 770 771 /* 5. Enable idle sync */ 772 reg_set16(UNIT_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 773 UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK); 774 775 /* 6. Enable the output of 100M/125M/500M clock */ 776 reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR, 777 MISC_REG0_DEFAULT_VALUE | CLK500M_EN | CLK100M_125M_EN, 778 REG_16_BIT_MASK); 779 780 /* 781 * 7. Enable TX, PCIE global register, 0xd0074814, it is done in 782 * PCI-E driver 783 */ 784 785 /* 786 * 8. Check crystal jumper setting and program the Power and PLL 787 * Control accordingly 788 */ 789 790 if (get_ref_clk() == 40) 791 ref_clk = REF_CLOCK_SPEED_40M; 792 else 793 ref_clk = PCIE_REF_CLOCK_SPEED_25M; 794 795 reg_set16(PWR_PLL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 796 (PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 797 PU_TX_INTP_BIT | PU_DFE_BIT | ref_clk | PHY_MODE_PCIE), 798 REG_16_BIT_MASK); 799 800 /* 9. Override Speed_PLL value and use MAC PLL */ 801 reg_set16(KVCO_CAL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 802 SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, REG_16_BIT_MASK); 803 804 /* 10. Check the Polarity invert bit */ 805 if (invert & COMPHY_POLARITY_TXD_INVERT) 806 reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, 807 TXD_INVERT_BIT, 0x0); 808 809 if (invert & COMPHY_POLARITY_RXD_INVERT) 810 reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, 811 RXD_INVERT_BIT, 0x0); 812 813 /* 11. Release SW reset */ 814 reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, 815 MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32, 816 SOFT_RESET | MODE_REFDIV); 817 818 /* Wait for > 55 us to allow PCLK be enabled */ 819 udelay(PLL_SET_DELAY_US); 820 821 ret = polling_with_timeout(LANE_STATUS1_ADDR(PCIE) + COMPHY_SD_ADDR, 822 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 823 COMPHY_PLL_TIMEOUT, REG_16BIT); 824 if (ret) 825 ERROR("Failed to lock PCIE PLL\n"); 826 827 debug_exit(); 828 829 return ret; 830 } 831 832 int mvebu_3700_comphy_power_on(uint8_t comphy_index, uint32_t comphy_mode) 833 { 834 int mode = COMPHY_GET_MODE(comphy_mode); 835 int ret = 0; 836 837 debug_enter(); 838 839 switch (mode) { 840 case(COMPHY_SATA_MODE): 841 ret = mvebu_a3700_comphy_sata_power_on(comphy_index, 842 comphy_mode); 843 break; 844 case(COMPHY_SGMII_MODE): 845 case(COMPHY_HS_SGMII_MODE): 846 ret = mvebu_a3700_comphy_sgmii_power_on(comphy_index, 847 comphy_mode); 848 break; 849 case (COMPHY_USB3_MODE): 850 case (COMPHY_USB3H_MODE): 851 ret = mvebu_a3700_comphy_usb3_power_on(comphy_index, 852 comphy_mode); 853 break; 854 case (COMPHY_PCIE_MODE): 855 ret = mvebu_a3700_comphy_pcie_power_on(comphy_index, 856 comphy_mode); 857 break; 858 default: 859 ERROR("comphy%d: unsupported comphy mode\n", comphy_index); 860 ret = -EINVAL; 861 break; 862 } 863 864 debug_exit(); 865 866 return ret; 867 } 868 869 static int mvebu_a3700_comphy_usb3_power_off(void) 870 { 871 /* 872 * Currently the USB3 MAC will control the USB3 PHY to set it to low 873 * state, thus do not need to power off USB3 PHY again. 874 */ 875 debug_enter(); 876 debug_exit(); 877 878 return 0; 879 } 880 881 static int mvebu_a3700_comphy_sata_power_off(uint32_t comphy_mode) 882 { 883 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 884 int mode = COMPHY_GET_MODE(comphy_mode); 885 uint32_t offset; 886 887 debug_enter(); 888 889 /* Set phy isolation mode */ 890 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 891 comphy_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE, 892 PHY_ISOLATE_MODE, mode); 893 894 /* Power off PLL, Tx, Rx */ 895 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 896 comphy_set_indirect(comphy_indir_regs, offset, 0, 897 PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT, mode); 898 899 debug_exit(); 900 901 return 0; 902 } 903 904 int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode) 905 { 906 int mode = COMPHY_GET_MODE(comphy_mode); 907 int err = 0; 908 909 debug_enter(); 910 911 switch (mode) { 912 case (COMPHY_USB3_MODE): 913 case (COMPHY_USB3H_MODE): 914 err = mvebu_a3700_comphy_usb3_power_off(); 915 break; 916 case (COMPHY_SATA_MODE): 917 err = mvebu_a3700_comphy_sata_power_off(comphy_mode); 918 break; 919 920 default: 921 debug("comphy%d: power off is not implemented for mode %d\n", 922 comphy_index, mode); 923 break; 924 } 925 926 debug_exit(); 927 928 return err; 929 } 930 931 static int mvebu_a3700_comphy_sata_is_pll_locked(void) 932 { 933 uint32_t data, addr; 934 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 935 int ret = 0; 936 937 debug_enter(); 938 939 /* Polling status */ 940 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 941 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); 942 addr = comphy_indir_regs + COMPHY_LANE2_INDIR_DATA_OFFSET; 943 data = polling_with_timeout(addr, PLL_READY_TX_BIT, PLL_READY_TX_BIT, 944 COMPHY_PLL_TIMEOUT, REG_32BIT); 945 946 if (data != 0) { 947 ERROR("TX PLL is not locked\n"); 948 ret = -ETIMEDOUT; 949 } 950 951 debug_exit(); 952 953 return ret; 954 } 955 956 int mvebu_3700_comphy_is_pll_locked(uint8_t comphy_index, uint32_t comphy_mode) 957 { 958 int mode = COMPHY_GET_MODE(comphy_mode); 959 int ret = 0; 960 961 debug_enter(); 962 963 switch (mode) { 964 case(COMPHY_SATA_MODE): 965 ret = mvebu_a3700_comphy_sata_is_pll_locked(); 966 break; 967 968 default: 969 ERROR("comphy[%d] mode[%d] doesn't support PLL lock check\n", 970 comphy_index, mode); 971 ret = -EINVAL; 972 break; 973 } 974 975 debug_exit(); 976 977 return ret; 978 } 979