1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <errno.h> 9 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/spinlock.h> 14 15 #include <mvebu.h> 16 #include <mvebu_def.h> 17 18 #include "phy-comphy-3700.h" 19 #include "phy-comphy-common.h" 20 21 /* 22 * COMPHY_INDIRECT_REG points to ahci address space but the ahci region used in 23 * Linux is up to 0x178 so none will access it from Linux in runtime 24 * concurrently. 25 */ 26 #define COMPHY_INDIRECT_REG (MVEBU_REGS_BASE + 0xE0178) 27 28 /* The USB3_GBE1_PHY range is above USB3 registers used in dts */ 29 #define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000) 30 #define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000) 31 32 /* 33 * Below address in used only for reading, therefore no problem with concurrent 34 * Linux access. 35 */ 36 #define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8) 37 #define MVEBU_XTAL_MODE_MASK BIT(9) 38 #define MVEBU_XTAL_MODE_OFFS 9 39 #define MVEBU_XTAL_CLOCK_25MHZ 0x0 40 41 struct sgmii_phy_init_data_fix { 42 uint16_t addr; 43 uint16_t value; 44 }; 45 46 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ 47 static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = { 48 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000}, 49 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030}, 50 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC}, 51 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA}, 52 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550}, 53 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0}, 54 {0x104, 0x0C10} 55 }; 56 57 /* 40M1G25 mode init data */ 58 static uint16_t sgmii_phy_init[512] = { 59 /* 0 1 2 3 4 5 6 7 */ 60 /*-----------------------------------------------------------*/ 61 /* 8 9 A B C D E F */ 62 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ 63 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ 64 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ 65 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ 66 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ 67 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ 68 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 69 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ 70 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ 71 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ 72 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ 73 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ 74 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ 75 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ 76 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ 77 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ 78 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ 79 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ 80 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ 81 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ 82 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ 83 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ 84 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ 85 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ 86 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ 87 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ 88 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ 89 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ 90 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ 91 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ 92 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ 93 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ 94 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ 95 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ 96 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ 97 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ 98 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ 99 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ 100 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ 101 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ 102 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ 103 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ 104 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ 105 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ 106 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ 107 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ 108 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ 109 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ 110 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ 111 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ 112 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ 113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ 114 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ 115 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ 116 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ 117 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ 118 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ 119 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ 120 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ 121 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ 122 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ 123 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ 124 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ 125 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ 126 }; 127 128 /* returns reference clock in MHz (25 or 40) */ 129 static uint32_t get_ref_clk(void) 130 { 131 uint32_t val; 132 133 val = (mmio_read_32(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >> 134 MVEBU_XTAL_MODE_OFFS; 135 136 if (val == MVEBU_XTAL_CLOCK_25MHZ) 137 return 25; 138 else 139 return 40; 140 } 141 142 /* PHY selector configures with corresponding modes */ 143 static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index, 144 uint32_t comphy_mode) 145 { 146 uint32_t reg; 147 int mode = COMPHY_GET_MODE(comphy_mode); 148 149 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG); 150 switch (mode) { 151 case (COMPHY_SATA_MODE): 152 /* SATA must be in Lane2 */ 153 if (comphy_index == COMPHY_LANE2) 154 reg &= ~COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 155 else 156 goto error; 157 break; 158 159 case (COMPHY_SGMII_MODE): 160 case (COMPHY_HS_SGMII_MODE): 161 if (comphy_index == COMPHY_LANE0) 162 reg &= ~COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 163 else if (comphy_index == COMPHY_LANE1) 164 reg &= ~COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 165 else 166 goto error; 167 break; 168 169 case (COMPHY_USB3H_MODE): 170 case (COMPHY_USB3D_MODE): 171 case (COMPHY_USB3_MODE): 172 if (comphy_index == COMPHY_LANE2) 173 reg |= COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 174 else if (comphy_index == COMPHY_LANE0) 175 reg |= COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 176 else 177 goto error; 178 break; 179 180 case (COMPHY_PCIE_MODE): 181 /* PCIE must be in Lane1 */ 182 if (comphy_index == COMPHY_LANE1) 183 reg |= COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 184 else 185 goto error; 186 break; 187 188 default: 189 goto error; 190 } 191 192 mmio_write_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG, reg); 193 return; 194 error: 195 ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index, mode); 196 } 197 198 /* 199 * This is something like the inverse of the previous function: for given 200 * lane it returns COMPHY_*_MODE. 201 * 202 * It is useful when powering the phy off. 203 * 204 * This function returns COMPHY_USB3_MODE even if the phy was configured 205 * with COMPHY_USB3D_MODE or COMPHY_USB3H_MODE. (The usb3 phy initialization 206 * code does not differentiate between these modes.) 207 * Also it returns COMPHY_SGMII_MODE even if the phy was configures with 208 * COMPHY_HS_SGMII_MODE. (The sgmii phy initialization code does differentiate 209 * between these modes, but it is irrelevant when powering the phy off.) 210 */ 211 static int mvebu_a3700_comphy_get_mode(uint8_t comphy_index) 212 { 213 uint32_t reg; 214 215 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG); 216 switch (comphy_index) { 217 case COMPHY_LANE0: 218 if ((reg & COMPHY_SELECTOR_USB3_GBE1_SEL_BIT) != 0) 219 return COMPHY_USB3_MODE; 220 else 221 return COMPHY_SGMII_MODE; 222 case COMPHY_LANE1: 223 if ((reg & COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT) != 0) 224 return COMPHY_PCIE_MODE; 225 else 226 return COMPHY_SGMII_MODE; 227 case COMPHY_LANE2: 228 if ((reg & COMPHY_SELECTOR_USB3_PHY_SEL_BIT) != 0) 229 return COMPHY_USB3_MODE; 230 else 231 return COMPHY_SATA_MODE; 232 } 233 234 return COMPHY_UNUSED; 235 } 236 237 /* It is only used for SATA and USB3 on comphy lane2. */ 238 static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data, 239 uint16_t mask, int mode) 240 { 241 /* 242 * When Lane 2 PHY is for USB3, access the PHY registers 243 * through indirect Address and Data registers: 244 * INDIR_ACC_PHY_ADDR (RD00E0178h [31:0]), 245 * INDIR_ACC_PHY_DATA (RD00E017Ch [31:0]), 246 * within the SATA Host Controller registers, Lane 2 base register 247 * offset is 0x200 248 */ 249 if (mode == COMPHY_UNUSED) 250 return; 251 252 if (mode == COMPHY_SATA_MODE) 253 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, offset); 254 else 255 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, 256 offset + USB3PHY_LANE2_REG_BASE_OFFSET); 257 258 reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask); 259 } 260 261 /* It is only used USB3 direct access not on comphy lane2. */ 262 static void comphy_usb3_set_direct(uintptr_t addr, uint32_t reg_offset, 263 uint16_t data, uint16_t mask, int mode) 264 { 265 reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask); 266 } 267 268 static void comphy_sgmii_phy_init(uint32_t comphy_index, uint32_t mode, 269 uintptr_t sd_ip_addr) 270 { 271 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix); 272 int addr, fix_idx; 273 uint16_t val; 274 275 fix_idx = 0; 276 for (addr = 0; addr < 512; addr++) { 277 /* 278 * All PHY register values are defined in full for 3.125Gbps 279 * SERDES speed. The values required for 1.25 Gbps are almost 280 * the same and only few registers should be "fixed" in 281 * comparison to 3.125 Gbps values. These register values are 282 * stored in "sgmii_phy_init_fix" array. 283 */ 284 if ((mode != COMPHY_SGMII_MODE) && 285 (sgmii_phy_init_fix[fix_idx].addr == addr)) { 286 /* Use new value */ 287 val = sgmii_phy_init_fix[fix_idx].value; 288 if (fix_idx < fix_arr_sz) 289 fix_idx++; 290 } else { 291 val = sgmii_phy_init[addr]; 292 } 293 294 reg_set16(SGMIIPHY_ADDR(addr, sd_ip_addr), val, 0xFFFF); 295 } 296 } 297 298 static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index, 299 uint32_t comphy_mode) 300 { 301 int ret = 0; 302 uint32_t offset, data = 0, ref_clk; 303 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 304 int mode = COMPHY_GET_MODE(comphy_mode); 305 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 306 307 debug_enter(); 308 309 /* Configure phy selector for SATA */ 310 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 311 312 /* Clear phy isolation mode to make it work in normal mode */ 313 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 314 comphy_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE, 315 mode); 316 317 /* 0. Check the Polarity invert bits */ 318 if (invert & COMPHY_POLARITY_TXD_INVERT) 319 data |= TXD_INVERT_BIT; 320 if (invert & COMPHY_POLARITY_RXD_INVERT) 321 data |= RXD_INVERT_BIT; 322 323 offset = COMPHY_SYNC_PATTERN_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 324 comphy_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT | 325 RXD_INVERT_BIT, mode); 326 327 /* 1. Select 40-bit data width width */ 328 offset = COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET; 329 comphy_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT, 330 SEL_DATA_WIDTH_MASK, mode); 331 332 /* 2. Select reference clock(25M) and PHY mode (SATA) */ 333 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 334 if (get_ref_clk() == 40) 335 ref_clk = REF_CLOCK_SPEED_40M; 336 else 337 ref_clk = REF_CLOCK_SPEED_25M; 338 339 comphy_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA, 340 REF_FREF_SEL_MASK | PHY_MODE_MASK, mode); 341 342 /* 3. Use maximum PLL rate (no power save) */ 343 offset = COMPHY_KVCO_CAL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 344 comphy_set_indirect(comphy_indir_regs, offset, USE_MAX_PLL_RATE_BIT, 345 USE_MAX_PLL_RATE_BIT, mode); 346 347 /* 4. Reset reserved bit */ 348 comphy_set_indirect(comphy_indir_regs, COMPHY_RESERVED_REG, 0, 349 PHYCTRL_FRM_PIN_BIT, mode); 350 351 /* 5. Set vendor-specific configuration (It is done in sata driver) */ 352 /* XXX: in U-Boot below sequence was executed in this place, in Linux 353 * not. Now it is done only in U-Boot before this comphy 354 * initialization - tests shows that it works ok, but in case of any 355 * future problem it is left for reference. 356 * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff); 357 * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6)); 358 */ 359 360 /* Wait for > 55 us to allow PLL be enabled */ 361 udelay(PLL_SET_DELAY_US); 362 363 /* Polling status */ 364 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 365 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); 366 367 ret = polling_with_timeout(comphy_indir_regs + 368 COMPHY_LANE2_INDIR_DATA_OFFSET, 369 PLL_READY_TX_BIT, PLL_READY_TX_BIT, 370 COMPHY_PLL_TIMEOUT, REG_32BIT); 371 372 debug_exit(); 373 374 return ret; 375 } 376 377 static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index, 378 uint32_t comphy_mode) 379 { 380 int ret = 0; 381 uint32_t mask, data, offset; 382 uintptr_t sd_ip_addr; 383 int mode = COMPHY_GET_MODE(comphy_mode); 384 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 385 386 debug_enter(); 387 388 /* Set selector */ 389 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 390 391 /* Serdes IP Base address 392 * COMPHY Lane0 -- USB3/GBE1 393 * COMPHY Lane1 -- PCIe/GBE0 394 */ 395 if (comphy_index == COMPHY_LANE0) { 396 /* Get usb3 and gbe */ 397 sd_ip_addr = USB3_GBE1_PHY; 398 } else 399 sd_ip_addr = COMPHY_SD_ADDR; 400 401 /* 402 * 1. Reset PHY by setting PHY input port PIN_RESET=1. 403 * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep 404 * PHY TXP/TXN output to idle state during PHY initialization 405 * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. 406 */ 407 data = PIN_PU_IVEREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT; 408 mask = PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | 409 PIN_PU_TX_BIT; 410 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); 411 reg_set(offset, data, mask); 412 413 /* 4. Release reset to the PHY by setting PIN_RESET=0. */ 414 data = 0; 415 mask = PIN_RESET_COMPHY_BIT; 416 reg_set(offset, data, mask); 417 418 /* 419 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY 420 * bit rate 421 */ 422 if (mode == COMPHY_SGMII_MODE) { 423 /* SGMII 1G, SerDes speed 1.25G */ 424 data |= SD_SPEED_1_25_G << GEN_RX_SEL_OFFSET; 425 data |= SD_SPEED_1_25_G << GEN_TX_SEL_OFFSET; 426 } else if (mode == COMPHY_HS_SGMII_MODE) { 427 /* HS SGMII (2.5G), SerDes speed 3.125G */ 428 data |= SD_SPEED_2_5_G << GEN_RX_SEL_OFFSET; 429 data |= SD_SPEED_2_5_G << GEN_TX_SEL_OFFSET; 430 } else { 431 /* Other rates are not supported */ 432 ERROR("unsupported SGMII speed on comphy lane%d\n", 433 comphy_index); 434 return -EINVAL; 435 } 436 mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK; 437 reg_set(offset, data, mask); 438 439 /* 440 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then 441 * start SW programming. 442 */ 443 mdelay(10); 444 445 /* 7. Program COMPHY register PHY_MODE */ 446 data = PHY_MODE_SGMII; 447 mask = PHY_MODE_MASK; 448 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 449 450 /* 451 * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK 452 * source 453 */ 454 data = 0; 455 mask = PHY_REF_CLK_SEL; 456 reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0_ADDR, sd_ip_addr), data, mask); 457 458 /* 459 * 9. Set correct reference clock frequency in COMPHY register 460 * REF_FREF_SEL. 461 */ 462 if (get_ref_clk() == 40) 463 data = REF_CLOCK_SPEED_50M; 464 else 465 data = REF_CLOCK_SPEED_25M; 466 467 mask = REF_FREF_SEL_MASK; 468 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); 469 470 /* 10. Program COMPHY register PHY_GEN_MAX[1:0] 471 * This step is mentioned in the flow received from verification team. 472 * However the PHY_GEN_MAX value is only meaningful for other interfaces 473 * (not SGMII). For instance, it selects SATA speed 1.5/3/6 Gbps or PCIe 474 * speed 2.5/5 Gbps 475 */ 476 477 /* 478 * 11. Program COMPHY register SEL_BITS to set correct parallel data 479 * bus width 480 */ 481 data = DATA_WIDTH_10BIT; 482 mask = SEL_DATA_WIDTH_MASK; 483 reg_set16(SGMIIPHY_ADDR(COMPHY_LOOPBACK_REG0, sd_ip_addr), data, mask); 484 485 /* 486 * 12. As long as DFE function needs to be enabled in any mode, 487 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F 488 * for real chip during COMPHY power on. 489 * The step 14 exists (and empty) in the original initialization flow 490 * obtained from the verification team. According to the functional 491 * specification DFE_UPDATE_EN already has the default value 0x3F 492 */ 493 494 /* 495 * 13. Program COMPHY GEN registers. 496 * These registers should be programmed based on the lab testing result 497 * to achieve optimal performance. Please contact the CEA group to get 498 * the related GEN table during real chip bring-up. We only required to 499 * run though the entire registers programming flow defined by 500 * "comphy_sgmii_phy_init" when the REF clock is 40 MHz. For REF clock 501 * 25 MHz the default values stored in PHY registers are OK. 502 */ 503 debug("Running C-DPI phy init %s mode\n", 504 mode == COMPHY_HS_SGMII_MODE ? "2G5" : "1G"); 505 if (get_ref_clk() == 40) 506 comphy_sgmii_phy_init(comphy_index, mode, sd_ip_addr); 507 508 /* 509 * 14. [Simulation Only] should not be used for real chip. 510 * By pass power up calibration by programming EXT_FORCE_CAL_DONE 511 * (R02h[9]) to 1 to shorten COMPHY simulation time. 512 */ 513 514 /* 515 * 15. [Simulation Only: should not be used for real chip] 516 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training 517 * simulation time. 518 */ 519 520 /* 521 * 16. Check the PHY Polarity invert bit 522 */ 523 data = 0x0; 524 if (invert & COMPHY_POLARITY_TXD_INVERT) 525 data |= TXD_INVERT_BIT; 526 if (invert & COMPHY_POLARITY_RXD_INVERT) 527 data |= RXD_INVERT_BIT; 528 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 529 reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, mask); 530 531 /* 532 * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to 533 * start PHY power up sequence. All the PHY register programming should 534 * be done before PIN_PU_PLL=1. There should be no register programming 535 * for normal PHY operation from this point. 536 */ 537 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 538 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT, 539 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT); 540 541 /* 542 * 18. Wait for PHY power up sequence to finish by checking output ports 543 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. 544 */ 545 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 546 COMPHY_PHY_STATUS_OFFSET(comphy_index), 547 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 548 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 549 COMPHY_PLL_TIMEOUT, REG_32BIT); 550 if (ret) 551 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 552 553 /* 554 * 19. Set COMPHY input port PIN_TX_IDLE=0 555 */ 556 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 557 0x0, PIN_TX_IDLE_BIT); 558 559 /* 560 * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To 561 * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the 562 * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to 563 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please 564 * refer to RX initialization part for details. 565 */ 566 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), 567 PHY_RX_INIT_BIT, PHY_RX_INIT_BIT); 568 569 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 570 COMPHY_PHY_STATUS_OFFSET(comphy_index), 571 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 572 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT, 573 COMPHY_PLL_TIMEOUT, REG_32BIT); 574 if (ret) 575 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index); 576 577 578 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + 579 COMPHY_PHY_STATUS_OFFSET(comphy_index), 580 PHY_RX_INIT_DONE_BIT, PHY_RX_INIT_DONE_BIT, 581 COMPHY_PLL_TIMEOUT, REG_32BIT); 582 if (ret) 583 ERROR("Failed to init RX of SGMII PHY %d\n", comphy_index); 584 585 debug_exit(); 586 587 return ret; 588 } 589 590 static int mvebu_a3700_comphy_sgmii_power_off(uint8_t comphy_index) 591 { 592 int ret = 0; 593 uint32_t mask, data, offset; 594 595 debug_enter(); 596 597 data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT; 598 mask = data; 599 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); 600 reg_set(offset, data, mask); 601 602 debug_exit(); 603 604 return ret; 605 } 606 607 static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index, 608 uint32_t comphy_mode) 609 { 610 int ret = 0; 611 uintptr_t reg_base = 0; 612 uint32_t mask, data, addr, cfg, ref_clk; 613 void (*usb3_reg_set)(uintptr_t addr, uint32_t reg_offset, uint16_t data, 614 uint16_t mask, int mode); 615 int mode = COMPHY_GET_MODE(comphy_mode); 616 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 617 618 debug_enter(); 619 620 /* Set phy seclector */ 621 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode); 622 623 /* Set usb3 reg access func, Lane2 is indirect access */ 624 if (comphy_index == COMPHY_LANE2) { 625 usb3_reg_set = &comphy_set_indirect; 626 reg_base = COMPHY_INDIRECT_REG; 627 } else { 628 /* Get the direct access register resource and map */ 629 usb3_reg_set = &comphy_usb3_set_direct; 630 reg_base = USB3_GBE1_PHY; 631 } 632 633 /* 634 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The 635 * register belong to UTMI module, so it is set in UTMI phy driver. 636 */ 637 638 /* 639 * 1. Set PRD_TXDEEMPH (3.5db de-emph) 640 */ 641 mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK | 642 CFG_TX_ALIGN_POS_MASK; 643 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK, 644 mask, mode); 645 646 /* 647 * 2. Set BIT0: enable transmitter in high impedance mode 648 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency 649 * Set BIT6: Tx detect Rx at HiZ mode 650 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db 651 * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR register 652 */ 653 mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK | 654 TX_ELEC_IDLE_MODE_EN; 655 data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN; 656 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask, mode); 657 658 /* 659 * 3. Set Spread Spectrum Clock Enabled 660 */ 661 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR, 662 SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN, mode); 663 664 /* 665 * 4. Set Override Margining Controls From the MAC: 666 * Use margining signals from lane configuration 667 */ 668 usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR, 669 MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK, mode); 670 671 /* 672 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles 673 * set Mode Clock Source = PCLK is generated from REFCLK 674 */ 675 usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0, 676 (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE | 677 BUNDLE_SAMPLE_CTRL | PLL_READY_DLY), mode); 678 679 /* 680 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K 681 */ 682 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2, 683 G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK, mode); 684 685 /* 686 * 7. Unset G3 Spread Spectrum Clock Amplitude 687 * set G3 TX and RX Register Master Current Select 688 */ 689 mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK | 690 RSVD_PH03FH_6_0_MASK; 691 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3, 692 G3_VREG_RXTX_MAS_ISET_60U, mask, mode); 693 694 /* 695 * 8. Check crystal jumper setting and program the Power and PLL Control 696 * accordingly Change RX wait 697 */ 698 if (get_ref_clk() == 40) { 699 ref_clk = REF_CLOCK_SPEED_40M; 700 cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT; 701 702 } else { 703 /* 25 MHz */ 704 ref_clk = USB3_REF_CLOCK_SPEED_25M; 705 cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT; 706 } 707 708 mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 709 PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | PHY_MODE_MASK | 710 REF_FREF_SEL_MASK; 711 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 712 PU_TX_INTP_BIT | PU_DFE_BIT | PHY_MODE_USB3 | ref_clk; 713 usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask, mode); 714 715 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 716 CFG_PM_RXDLOZ_WAIT_MASK; 717 data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg; 718 usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask, mode); 719 720 /* 721 * 9. Enable idle sync 722 */ 723 data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN; 724 usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK, 725 mode); 726 727 /* 728 * 10. Enable the output of 500M clock 729 */ 730 data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN; 731 usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK, 732 mode); 733 734 /* 735 * 11. Set 20-bit data width 736 */ 737 usb3_reg_set(reg_base, COMPHY_LOOPBACK_REG0, DATA_WIDTH_20BIT, 738 REG_16_BIT_MASK, mode); 739 740 /* 741 * 12. Override Speed_PLL value and use MAC PLL 742 */ 743 usb3_reg_set(reg_base, COMPHY_KVCO_CAL_CTRL, 744 (SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT), 745 REG_16_BIT_MASK, mode); 746 747 /* 748 * 13. Check the Polarity invert bit 749 */ 750 data = 0U; 751 if (invert & COMPHY_POLARITY_TXD_INVERT) { 752 data |= TXD_INVERT_BIT; 753 } 754 if (invert & COMPHY_POLARITY_RXD_INVERT) { 755 data |= RXD_INVERT_BIT; 756 } 757 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 758 usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask, mode); 759 760 /* 761 * 14. Set max speed generation to USB3.0 5Gbps 762 */ 763 usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN_REG, PHY_GEN_USB3_5G, 764 PHY_GEN_MAX_MASK, mode); 765 766 /* 767 * 15. Set capacitor value for FFE gain peaking to 0xF 768 */ 769 usb3_reg_set(reg_base, COMPHY_REG_GEN3_SETTINGS_3, 770 COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK, 771 mode); 772 773 /* 774 * 16. Release SW reset 775 */ 776 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4; 777 usb3_reg_set(reg_base, COMPHY_REG_GLOB_PHY_CTRL0_ADDR, data, 778 REG_16_BIT_MASK, mode); 779 780 /* Wait for > 55 us to allow PCLK be enabled */ 781 udelay(PLL_SET_DELAY_US); 782 783 if (comphy_index == COMPHY_LANE2) { 784 data = COMPHY_REG_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET; 785 mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET, 786 data); 787 788 addr = reg_base + COMPHY_LANE2_INDIR_DATA_OFFSET; 789 ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 790 COMPHY_PLL_TIMEOUT, REG_32BIT); 791 } else { 792 ret = polling_with_timeout(LANE_STATUS1_ADDR(USB3) + reg_base, 793 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 794 COMPHY_PLL_TIMEOUT, REG_16BIT); 795 } 796 if (ret) 797 ERROR("Failed to lock USB3 PLL\n"); 798 799 debug_exit(); 800 801 return ret; 802 } 803 804 static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index, 805 uint32_t comphy_mode) 806 { 807 int ret; 808 uint32_t ref_clk; 809 uint32_t mask, data; 810 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); 811 812 debug_enter(); 813 814 /* 1. Enable max PLL. */ 815 reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR, 816 USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN); 817 818 /* 2. Select 20 bit SERDES interface. */ 819 reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR, 820 CFG_SEL_20B, CFG_SEL_20B); 821 822 /* 3. Force to use reg setting for PCIe mode */ 823 reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR, 824 SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE); 825 826 /* 4. Change RX wait */ 827 reg_set16(PWR_MGM_TIM1_ADDR(PCIE) + COMPHY_SD_ADDR, 828 CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT, 829 (CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 830 CFG_PM_RXDLOZ_WAIT_MASK)); 831 832 /* 5. Enable idle sync */ 833 reg_set16(UNIT_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 834 UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK); 835 836 /* 6. Enable the output of 100M/125M/500M clock */ 837 reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR, 838 MISC_REG0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN, 839 REG_16_BIT_MASK); 840 841 /* 842 * 7. Enable TX, PCIE global register, 0xd0074814, it is done in 843 * PCI-E driver 844 */ 845 846 /* 847 * 8. Check crystal jumper setting and program the Power and PLL 848 * Control accordingly 849 */ 850 851 if (get_ref_clk() == 40) 852 ref_clk = REF_CLOCK_SPEED_40M; 853 else 854 ref_clk = PCIE_REF_CLOCK_SPEED_25M; 855 856 reg_set16(PWR_PLL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 857 (PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 858 PU_TX_INTP_BIT | PU_DFE_BIT | ref_clk | PHY_MODE_PCIE), 859 REG_16_BIT_MASK); 860 861 /* 9. Override Speed_PLL value and use MAC PLL */ 862 reg_set16(KVCO_CAL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, 863 SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, REG_16_BIT_MASK); 864 865 /* 10. Check the Polarity invert bit */ 866 data = 0U; 867 if (invert & COMPHY_POLARITY_TXD_INVERT) { 868 data |= TXD_INVERT_BIT; 869 } 870 if (invert & COMPHY_POLARITY_RXD_INVERT) { 871 data |= RXD_INVERT_BIT; 872 } 873 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 874 reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); 875 876 /* 11. Release SW reset */ 877 reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, 878 MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32, 879 SOFT_RESET | MODE_REFDIV); 880 881 /* Wait for > 55 us to allow PCLK be enabled */ 882 udelay(PLL_SET_DELAY_US); 883 884 ret = polling_with_timeout(LANE_STATUS1_ADDR(PCIE) + COMPHY_SD_ADDR, 885 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, 886 COMPHY_PLL_TIMEOUT, REG_16BIT); 887 if (ret) 888 ERROR("Failed to lock PCIE PLL\n"); 889 890 debug_exit(); 891 892 return ret; 893 } 894 895 int mvebu_3700_comphy_power_on(uint8_t comphy_index, uint32_t comphy_mode) 896 { 897 int mode = COMPHY_GET_MODE(comphy_mode); 898 int ret = 0; 899 900 debug_enter(); 901 902 switch (mode) { 903 case(COMPHY_SATA_MODE): 904 ret = mvebu_a3700_comphy_sata_power_on(comphy_index, 905 comphy_mode); 906 break; 907 case(COMPHY_SGMII_MODE): 908 case(COMPHY_HS_SGMII_MODE): 909 ret = mvebu_a3700_comphy_sgmii_power_on(comphy_index, 910 comphy_mode); 911 break; 912 case (COMPHY_USB3_MODE): 913 case (COMPHY_USB3H_MODE): 914 ret = mvebu_a3700_comphy_usb3_power_on(comphy_index, 915 comphy_mode); 916 break; 917 case (COMPHY_PCIE_MODE): 918 ret = mvebu_a3700_comphy_pcie_power_on(comphy_index, 919 comphy_mode); 920 break; 921 default: 922 ERROR("comphy%d: unsupported comphy mode\n", comphy_index); 923 ret = -EINVAL; 924 break; 925 } 926 927 debug_exit(); 928 929 return ret; 930 } 931 932 static int mvebu_a3700_comphy_usb3_power_off(void) 933 { 934 /* 935 * Currently the USB3 MAC will control the USB3 PHY to set it to low 936 * state, thus do not need to power off USB3 PHY again. 937 */ 938 debug_enter(); 939 debug_exit(); 940 941 return 0; 942 } 943 944 static int mvebu_a3700_comphy_sata_power_off(uint32_t comphy_mode) 945 { 946 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 947 int mode = COMPHY_GET_MODE(comphy_mode); 948 uint32_t offset; 949 950 debug_enter(); 951 952 /* Set phy isolation mode */ 953 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; 954 comphy_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE, 955 PHY_ISOLATE_MODE, mode); 956 957 /* Power off PLL, Tx, Rx */ 958 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; 959 comphy_set_indirect(comphy_indir_regs, offset, 0, 960 PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT, mode); 961 962 debug_exit(); 963 964 return 0; 965 } 966 967 int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode) 968 { 969 int mode = COMPHY_GET_MODE(comphy_mode); 970 int err = 0; 971 972 debug_enter(); 973 974 if (!mode) { 975 /* 976 * The user did not specify which mode should be powered off. 977 * In this case we can identify this by reading the phy selector 978 * register. 979 */ 980 mode = mvebu_a3700_comphy_get_mode(comphy_index); 981 } 982 983 switch (mode) { 984 case(COMPHY_SGMII_MODE): 985 case(COMPHY_HS_SGMII_MODE): 986 err = mvebu_a3700_comphy_sgmii_power_off(comphy_index); 987 break; 988 case (COMPHY_USB3_MODE): 989 case (COMPHY_USB3H_MODE): 990 err = mvebu_a3700_comphy_usb3_power_off(); 991 break; 992 case (COMPHY_SATA_MODE): 993 err = mvebu_a3700_comphy_sata_power_off(comphy_mode); 994 break; 995 996 default: 997 debug("comphy%d: power off is not implemented for mode %d\n", 998 comphy_index, mode); 999 break; 1000 } 1001 1002 debug_exit(); 1003 1004 return err; 1005 } 1006 1007 static int mvebu_a3700_comphy_sata_is_pll_locked(void) 1008 { 1009 uint32_t data, addr; 1010 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG; 1011 int ret = 0; 1012 1013 debug_enter(); 1014 1015 /* Polling status */ 1016 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, 1017 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); 1018 addr = comphy_indir_regs + COMPHY_LANE2_INDIR_DATA_OFFSET; 1019 data = polling_with_timeout(addr, PLL_READY_TX_BIT, PLL_READY_TX_BIT, 1020 COMPHY_PLL_TIMEOUT, REG_32BIT); 1021 1022 if (data != 0) { 1023 ERROR("TX PLL is not locked\n"); 1024 ret = -ETIMEDOUT; 1025 } 1026 1027 debug_exit(); 1028 1029 return ret; 1030 } 1031 1032 int mvebu_3700_comphy_is_pll_locked(uint8_t comphy_index, uint32_t comphy_mode) 1033 { 1034 int mode = COMPHY_GET_MODE(comphy_mode); 1035 int ret = 0; 1036 1037 debug_enter(); 1038 1039 switch (mode) { 1040 case(COMPHY_SATA_MODE): 1041 ret = mvebu_a3700_comphy_sata_is_pll_locked(); 1042 break; 1043 1044 default: 1045 ERROR("comphy[%d] mode[%d] doesn't support PLL lock check\n", 1046 comphy_index, mode); 1047 ret = -EINVAL; 1048 break; 1049 } 1050 1051 debug_exit(); 1052 1053 return ret; 1054 } 1055