1*0ade8cd8SKonstantin Porotchkin /* 2*0ade8cd8SKonstantin Porotchkin * Copyright (C) 2018 Marvell International Ltd. 3*0ade8cd8SKonstantin Porotchkin * 4*0ade8cd8SKonstantin Porotchkin * SPDX-License-Identifier: BSD-3-Clause 5*0ade8cd8SKonstantin Porotchkin * https://spdx.org/licenses 6*0ade8cd8SKonstantin Porotchkin */ 7*0ade8cd8SKonstantin Porotchkin 8*0ade8cd8SKonstantin Porotchkin /* Marvell CP110 SoC COMPHY unit driver */ 9*0ade8cd8SKonstantin Porotchkin 10*0ade8cd8SKonstantin Porotchkin #ifndef _PHY_COMPHY_CP110_H 11*0ade8cd8SKonstantin Porotchkin #define _PHY_COMPHY_CP110_H 12*0ade8cd8SKonstantin Porotchkin 13*0ade8cd8SKonstantin Porotchkin #define SD_ADDR(base, lane) (base + 0x1000 * lane) 14*0ade8cd8SKonstantin Porotchkin #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) 15*0ade8cd8SKonstantin Porotchkin #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) 16*0ade8cd8SKonstantin Porotchkin 17*0ade8cd8SKonstantin Porotchkin #define MAX_NUM_OF_FFE 8 18*0ade8cd8SKonstantin Porotchkin #define RX_TRAINING_TIMEOUT 500 19*0ade8cd8SKonstantin Porotchkin 20*0ade8cd8SKonstantin Porotchkin /* Comphy registers */ 21*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_CFG1_REG 0x0 22*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_CFG1_PWR_UP_OFFSET 1 23*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_CFG1_PWR_UP_MASK \ 24*0ade8cd8SKonstantin Porotchkin (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET) 25*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2 26*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_CFG1_PIPE_SELECT_MASK \ 27*0ade8cd8SKonstantin Porotchkin (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET) 28*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 13 29*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_CFG1_CORE_RSTN_MASK \ 30*0ade8cd8SKonstantin Porotchkin (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET) 31*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 14 32*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \ 33*0ade8cd8SKonstantin Porotchkin (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET) 34*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_PHY_MODE_OFFSET 15 35*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_PHY_MODE_MASK \ 36*0ade8cd8SKonstantin Porotchkin (0x1 << COMMON_PHY_PHY_MODE_OFFSET) 37*0ade8cd8SKonstantin Porotchkin 38*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_CFG6_REG 0x14 39*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18 40*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_CFG6_IF_40_SEL_MASK \ 41*0ade8cd8SKonstantin Porotchkin (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET) 42*0ade8cd8SKonstantin Porotchkin 43*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_CFG6_REG 0x14 44*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18 45*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_CFG6_IF_40_SEL_MASK \ 46*0ade8cd8SKonstantin Porotchkin (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET) 47*0ade8cd8SKonstantin Porotchkin 48*0ade8cd8SKonstantin Porotchkin #define COMMON_SELECTOR_PHY_REG_OFFSET 0x140 49*0ade8cd8SKonstantin Porotchkin #define COMMON_SELECTOR_PIPE_REG_OFFSET 0x144 50*0ade8cd8SKonstantin Porotchkin #define COMMON_SELECTOR_COMPHY_MASK 0xf 51*0ade8cd8SKonstantin Porotchkin #define COMMON_SELECTOR_COMPHYN_FIELD_WIDTH 4 52*0ade8cd8SKonstantin Porotchkin #define COMMON_SELECTOR_COMPHYN_SATA 0x4 53*0ade8cd8SKonstantin Porotchkin #define COMMON_SELECTOR_PIPE_COMPHY_PCIE 0x4 54*0ade8cd8SKonstantin Porotchkin #define COMMON_SELECTOR_PIPE_COMPHY_USBH 0x1 55*0ade8cd8SKonstantin Porotchkin #define COMMON_SELECTOR_PIPE_COMPHY_USBD 0x2 56*0ade8cd8SKonstantin Porotchkin 57*0ade8cd8SKonstantin Porotchkin /* SGMII/HS-SGMII/SFI/RXAUI */ 58*0ade8cd8SKonstantin Porotchkin #define COMMON_SELECTOR_COMPHY0_1_2_NETWORK 0x1 59*0ade8cd8SKonstantin Porotchkin #define COMMON_SELECTOR_COMPHY3_RXAUI 0x1 60*0ade8cd8SKonstantin Porotchkin #define COMMON_SELECTOR_COMPHY3_SGMII 0x2 61*0ade8cd8SKonstantin Porotchkin #define COMMON_SELECTOR_COMPHY4_PORT1 0x1 62*0ade8cd8SKonstantin Porotchkin #define COMMON_SELECTOR_COMPHY4_ALL_OTHERS 0x2 63*0ade8cd8SKonstantin Porotchkin #define COMMON_SELECTOR_COMPHY5_RXAUI 0x2 64*0ade8cd8SKonstantin Porotchkin #define COMMON_SELECTOR_COMPHY5_SGMII 0x1 65*0ade8cd8SKonstantin Porotchkin 66*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_SD_CTRL1 0x148 67*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_SD_CTRL1_COMPHY_0_PORT_OFFSET 0 68*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_SD_CTRL1_COMPHY_1_PORT_OFFSET 4 69*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_SD_CTRL1_COMPHY_2_PORT_OFFSET 8 70*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_SD_CTRL1_COMPHY_3_PORT_OFFSET 12 71*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_SD_CTRL1_COMPHY_0_3_PORT_MASK 0xFFFF 72*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_SD_CTRL1_COMPHY_0_1_PORT_MASK 0xFF 73*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24 74*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \ 75*0ade8cd8SKonstantin Porotchkin (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET) 76*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25 77*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \ 78*0ade8cd8SKonstantin Porotchkin (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET) 79*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26 80*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \ 81*0ade8cd8SKonstantin Porotchkin (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET) 82*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27 83*0ade8cd8SKonstantin Porotchkin #define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \ 84*0ade8cd8SKonstantin Porotchkin (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET) 85*0ade8cd8SKonstantin Porotchkin 86*0ade8cd8SKonstantin Porotchkin /* DFX register */ 87*0ade8cd8SKonstantin Porotchkin #define DFX_BASE (0x400000) 88*0ade8cd8SKonstantin Porotchkin #define DFX_DEV_GEN_CTRL12_REG (0x280) 89*0ade8cd8SKonstantin Porotchkin #define DFX_DEV_GEN_PCIE_CLK_SRC_MUX (0x3) 90*0ade8cd8SKonstantin Porotchkin #define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7 91*0ade8cd8SKonstantin Porotchkin #define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \ 92*0ade8cd8SKonstantin Porotchkin (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET) 93*0ade8cd8SKonstantin Porotchkin 94*0ade8cd8SKonstantin Porotchkin /* SerDes IP registers */ 95*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG0_REG 0 96*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1 97*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \ 98*0ade8cd8SKonstantin Porotchkin (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET) 99*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3 100*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \ 101*0ade8cd8SKonstantin Porotchkin (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) 102*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7 103*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \ 104*0ade8cd8SKonstantin Porotchkin (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) 105*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11 106*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \ 107*0ade8cd8SKonstantin Porotchkin (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET) 108*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12 109*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \ 110*0ade8cd8SKonstantin Porotchkin (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) 111*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 112*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \ 113*0ade8cd8SKonstantin Porotchkin (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) 114*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15 115*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \ 116*0ade8cd8SKonstantin Porotchkin (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET) 117*0ade8cd8SKonstantin Porotchkin 118*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG1_REG 0x4 119*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 120*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \ 121*0ade8cd8SKonstantin Porotchkin (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) 122*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4 123*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \ 124*0ade8cd8SKonstantin Porotchkin (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) 125*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5 126*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \ 127*0ade8cd8SKonstantin Porotchkin (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) 128*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 129*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \ 130*0ade8cd8SKonstantin Porotchkin (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) 131*0ade8cd8SKonstantin Porotchkin 132*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG2_REG 0x8 133*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 134*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \ 135*0ade8cd8SKonstantin Porotchkin (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) 136*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7 137*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \ 138*0ade8cd8SKonstantin Porotchkin (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET) 139*0ade8cd8SKonstantin Porotchkin 140*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_STATUS_REG 0xc 141*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET 7 142*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK \ 143*0ade8cd8SKonstantin Porotchkin (1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET) 144*0ade8cd8SKonstantin Porotchkin 145*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_STATUS0_REG 0x18 146*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 147*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_STATUS0_PLL_TX_MASK \ 148*0ade8cd8SKonstantin Porotchkin (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET) 149*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3 150*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_STATUS0_PLL_RX_MASK \ 151*0ade8cd8SKonstantin Porotchkin (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET) 152*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4 153*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_STATUS0_RX_INIT_MASK \ 154*0ade8cd8SKonstantin Porotchkin (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET) 155*0ade8cd8SKonstantin Porotchkin 156*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_STATAUS1_REG 0x1c 157*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_COMP_OFFSET 0 158*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_COMP_MASK \ 159*0ade8cd8SKonstantin Porotchkin (1 << SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_COMP_OFFSET) 160*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_FAILED_OFFSET 1 161*0ade8cd8SKonstantin Porotchkin #define SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_FAILED_MASK \ 162*0ade8cd8SKonstantin Porotchkin (1 << SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_FAILED_OFFSET) 163*0ade8cd8SKonstantin Porotchkin 164*0ade8cd8SKonstantin Porotchkin /* HPIPE registers */ 165*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_PLL_REG 0x4 166*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 167*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_PLL_REF_FREQ_MASK \ 168*0ade8cd8SKonstantin Porotchkin (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) 169*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 170*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_PLL_PHY_MODE_MASK \ 171*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) 172*0ade8cd8SKonstantin Porotchkin 173*0ade8cd8SKonstantin Porotchkin #define HPIPE_CAL_REG1_REG 0xc 174*0ade8cd8SKonstantin Porotchkin #define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10 175*0ade8cd8SKonstantin Porotchkin #define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \ 176*0ade8cd8SKonstantin Porotchkin (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) 177*0ade8cd8SKonstantin Porotchkin #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15 178*0ade8cd8SKonstantin Porotchkin #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \ 179*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET) 180*0ade8cd8SKonstantin Porotchkin 181*0ade8cd8SKonstantin Porotchkin #define HPIPE_SQUELCH_FFE_SETTING_REG 0x18 182*0ade8cd8SKonstantin Porotchkin #define HPIPE_SQUELCH_THRESH_IN_OFFSET 8 183*0ade8cd8SKonstantin Porotchkin #define HPIPE_SQUELCH_THRESH_IN_MASK \ 184*0ade8cd8SKonstantin Porotchkin (0xf << HPIPE_SQUELCH_THRESH_IN_OFFSET) 185*0ade8cd8SKonstantin Porotchkin #define HPIPE_SQUELCH_DETECTED_OFFSET 14 186*0ade8cd8SKonstantin Porotchkin #define HPIPE_SQUELCH_DETECTED_MASK \ 187*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_SQUELCH_DETECTED_OFFSET) 188*0ade8cd8SKonstantin Porotchkin 189*0ade8cd8SKonstantin Porotchkin #define HPIPE_DFE_REG0 0x1c 190*0ade8cd8SKonstantin Porotchkin #define HPIPE_DFE_RES_FORCE_OFFSET 15 191*0ade8cd8SKonstantin Porotchkin #define HPIPE_DFE_RES_FORCE_MASK \ 192*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) 193*0ade8cd8SKonstantin Porotchkin 194*0ade8cd8SKonstantin Porotchkin #define HPIPE_DFE_F3_F5_REG 0x28 195*0ade8cd8SKonstantin Porotchkin #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14 196*0ade8cd8SKonstantin Porotchkin #define HPIPE_DFE_F3_F5_DFE_EN_MASK \ 197*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) 198*0ade8cd8SKonstantin Porotchkin #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 199*0ade8cd8SKonstantin Porotchkin #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \ 200*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) 201*0ade8cd8SKonstantin Porotchkin 202*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_0_REG 0x34 203*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1 204*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_0_G1_TX_AMP_MASK \ 205*0ade8cd8SKonstantin Porotchkin (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET) 206*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6 207*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \ 208*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET) 209*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 210*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \ 211*0ade8cd8SKonstantin Porotchkin (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) 212*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11 213*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \ 214*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET) 215*0ade8cd8SKonstantin Porotchkin 216*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_1_REG 0x38 217*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 218*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \ 219*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) 220*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 221*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \ 222*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) 223*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6 224*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \ 225*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET) 226*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8 227*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \ 228*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET) 229*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 230*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \ 231*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) 232*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11 233*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \ 234*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET) 235*0ade8cd8SKonstantin Porotchkin 236*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_0_REG 0x3c 237*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1 238*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_0_G2_TX_AMP_MASK \ 239*0ade8cd8SKonstantin Porotchkin (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET) 240*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6 241*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \ 242*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET) 243*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7 244*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \ 245*0ade8cd8SKonstantin Porotchkin (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET) 246*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11 247*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \ 248*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET) 249*0ade8cd8SKonstantin Porotchkin 250*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_1_REG 0x40 251*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 252*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \ 253*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) 254*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3 255*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \ 256*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) 257*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 258*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \ 259*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) 260*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8 261*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \ 262*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET) 263*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10 264*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \ 265*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET) 266*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11 267*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \ 268*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET) 269*0ade8cd8SKonstantin Porotchkin 270*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_0_REG 0x44 271*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1 272*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_0_G3_TX_AMP_MASK \ 273*0ade8cd8SKonstantin Porotchkin (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET) 274*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6 275*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \ 276*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET) 277*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7 278*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \ 279*0ade8cd8SKonstantin Porotchkin (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET) 280*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11 281*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \ 282*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET) 283*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12 284*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \ 285*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET) 286*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15 287*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \ 288*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET) 289*0ade8cd8SKonstantin Porotchkin 290*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_1_REG 0x48 291*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0 292*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \ 293*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET) 294*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3 295*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \ 296*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET) 297*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6 298*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \ 299*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET) 300*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8 301*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \ 302*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET) 303*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10 304*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \ 305*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET) 306*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11 307*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \ 308*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET) 309*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13 310*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \ 311*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET) 312*0ade8cd8SKonstantin Porotchkin 313*0ade8cd8SKonstantin Porotchkin #define HPIPE_PHY_TEST_CONTROL_REG 0x54 314*0ade8cd8SKonstantin Porotchkin #define HPIPE_PHY_TEST_PATTERN_SEL_OFFSET 4 315*0ade8cd8SKonstantin Porotchkin #define HPIPE_PHY_TEST_PATTERN_SEL_MASK \ 316*0ade8cd8SKonstantin Porotchkin (0xf << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET) 317*0ade8cd8SKonstantin Porotchkin #define HPIPE_PHY_TEST_RESET_OFFSET 14 318*0ade8cd8SKonstantin Porotchkin #define HPIPE_PHY_TEST_RESET_MASK \ 319*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_PHY_TEST_RESET_OFFSET) 320*0ade8cd8SKonstantin Porotchkin #define HPIPE_PHY_TEST_EN_OFFSET 15 321*0ade8cd8SKonstantin Porotchkin #define HPIPE_PHY_TEST_EN_MASK \ 322*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_PHY_TEST_EN_OFFSET) 323*0ade8cd8SKonstantin Porotchkin 324*0ade8cd8SKonstantin Porotchkin #define HPIPE_PHY_TEST_DATA_REG 0x6c 325*0ade8cd8SKonstantin Porotchkin #define HPIPE_PHY_TEST_DATA_OFFSET 0 326*0ade8cd8SKonstantin Porotchkin #define HPIPE_PHY_TEST_DATA_MASK \ 327*0ade8cd8SKonstantin Porotchkin (0xffff << HPIPE_PHY_TEST_DATA_OFFSET) 328*0ade8cd8SKonstantin Porotchkin 329*0ade8cd8SKonstantin Porotchkin #define HPIPE_LOOPBACK_REG 0x8c 330*0ade8cd8SKonstantin Porotchkin #define HPIPE_LOOPBACK_SEL_OFFSET 1 331*0ade8cd8SKonstantin Porotchkin #define HPIPE_LOOPBACK_SEL_MASK \ 332*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) 333*0ade8cd8SKonstantin Porotchkin #define HPIPE_CDR_LOCK_OFFSET 7 334*0ade8cd8SKonstantin Porotchkin #define HPIPE_CDR_LOCK_MASK \ 335*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_CDR_LOCK_OFFSET) 336*0ade8cd8SKonstantin Porotchkin #define HPIPE_CDR_LOCK_DET_EN_OFFSET 8 337*0ade8cd8SKonstantin Porotchkin #define HPIPE_CDR_LOCK_DET_EN_MASK \ 338*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET) 339*0ade8cd8SKonstantin Porotchkin 340*0ade8cd8SKonstantin Porotchkin #define HPIPE_INTERFACE_REG 0x94 341*0ade8cd8SKonstantin Porotchkin #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 342*0ade8cd8SKonstantin Porotchkin #define HPIPE_INTERFACE_GEN_MAX_MASK \ 343*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) 344*0ade8cd8SKonstantin Porotchkin #define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12 345*0ade8cd8SKonstantin Porotchkin #define HPIPE_INTERFACE_DET_BYPASS_MASK \ 346*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET) 347*0ade8cd8SKonstantin Porotchkin #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 348*0ade8cd8SKonstantin Porotchkin #define HPIPE_INTERFACE_LINK_TRAIN_MASK \ 349*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) 350*0ade8cd8SKonstantin Porotchkin 351*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_2_REG 0xf4 352*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0 353*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \ 354*0ade8cd8SKonstantin Porotchkin (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET) 355*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4 356*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \ 357*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET) 358*0ade8cd8SKonstantin Porotchkin 359*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SET_2_REG 0xf8 360*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_TX_SSC_AMP_OFFSET 9 361*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_TX_SSC_AMP_MASK \ 362*0ade8cd8SKonstantin Porotchkin (0x7f << HPIPE_G2_TX_SSC_AMP_OFFSET) 363*0ade8cd8SKonstantin Porotchkin 364*0ade8cd8SKonstantin Porotchkin #define HPIPE_VDD_CAL_0_REG 0x108 365*0ade8cd8SKonstantin Porotchkin #define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15 366*0ade8cd8SKonstantin Porotchkin #define HPIPE_CAL_VDD_CONT_MODE_MASK \ 367*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET) 368*0ade8cd8SKonstantin Porotchkin 369*0ade8cd8SKonstantin Porotchkin #define HPIPE_VDD_CAL_CTRL_REG 0x114 370*0ade8cd8SKonstantin Porotchkin #define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 371*0ade8cd8SKonstantin Porotchkin #define HPIPE_EXT_SELLV_RXSAMPL_MASK \ 372*0ade8cd8SKonstantin Porotchkin (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) 373*0ade8cd8SKonstantin Porotchkin 374*0ade8cd8SKonstantin Porotchkin #define HPIPE_PCIE_REG0 0x120 375*0ade8cd8SKonstantin Porotchkin #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 376*0ade8cd8SKonstantin Porotchkin #define HPIPE_PCIE_IDLE_SYNC_MASK \ 377*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) 378*0ade8cd8SKonstantin Porotchkin #define HPIPE_PCIE_SEL_BITS_OFFSET 13 379*0ade8cd8SKonstantin Porotchkin #define HPIPE_PCIE_SEL_BITS_MASK \ 380*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) 381*0ade8cd8SKonstantin Porotchkin 382*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_ALIGN_REG 0x124 383*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_ALIGN_OFF_OFFSET 12 384*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_ALIGN_OFF_MASK \ 385*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) 386*0ade8cd8SKonstantin Porotchkin 387*0ade8cd8SKonstantin Porotchkin #define HPIPE_MISC_REG 0x13C 388*0ade8cd8SKonstantin Porotchkin #define HPIPE_MISC_CLK100M_125M_OFFSET 4 389*0ade8cd8SKonstantin Porotchkin #define HPIPE_MISC_CLK100M_125M_MASK \ 390*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) 391*0ade8cd8SKonstantin Porotchkin #define HPIPE_MISC_ICP_FORCE_OFFSET 5 392*0ade8cd8SKonstantin Porotchkin #define HPIPE_MISC_ICP_FORCE_MASK \ 393*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) 394*0ade8cd8SKonstantin Porotchkin #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 395*0ade8cd8SKonstantin Porotchkin #define HPIPE_MISC_TXDCLK_2X_MASK \ 396*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) 397*0ade8cd8SKonstantin Porotchkin #define HPIPE_MISC_CLK500_EN_OFFSET 7 398*0ade8cd8SKonstantin Porotchkin #define HPIPE_MISC_CLK500_EN_MASK \ 399*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) 400*0ade8cd8SKonstantin Porotchkin #define HPIPE_MISC_REFCLK_SEL_OFFSET 10 401*0ade8cd8SKonstantin Porotchkin #define HPIPE_MISC_REFCLK_SEL_MASK \ 402*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) 403*0ade8cd8SKonstantin Porotchkin 404*0ade8cd8SKonstantin Porotchkin #define HPIPE_RX_CONTROL_1_REG 0x140 405*0ade8cd8SKonstantin Porotchkin #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11 406*0ade8cd8SKonstantin Porotchkin #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \ 407*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET) 408*0ade8cd8SKonstantin Porotchkin #define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12 409*0ade8cd8SKonstantin Porotchkin #define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \ 410*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET) 411*0ade8cd8SKonstantin Porotchkin 412*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_REG 0x148 413*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_RST_DFE_OFFSET 0 414*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_RST_DFE_MASK \ 415*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET) 416*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_SFT_RST_OFFSET 10 417*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_SFT_RST_MASK \ 418*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) 419*0ade8cd8SKonstantin Porotchkin 420*0ade8cd8SKonstantin Porotchkin #define HPIPE_SPD_DIV_FORCE_REG 0x154 421*0ade8cd8SKonstantin Porotchkin #define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7 422*0ade8cd8SKonstantin Porotchkin #define HPIPE_TXDIGCK_DIV_FORCE_MASK \ 423*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET) 424*0ade8cd8SKonstantin Porotchkin #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8 425*0ade8cd8SKonstantin Porotchkin #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \ 426*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) 427*0ade8cd8SKonstantin Porotchkin #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10 428*0ade8cd8SKonstantin Porotchkin #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \ 429*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) 430*0ade8cd8SKonstantin Porotchkin #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13 431*0ade8cd8SKonstantin Porotchkin #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \ 432*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) 433*0ade8cd8SKonstantin Porotchkin #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15 434*0ade8cd8SKonstantin Porotchkin #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \ 435*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET) 436*0ade8cd8SKonstantin Porotchkin 437*0ade8cd8SKonstantin Porotchkin #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C 438*0ade8cd8SKonstantin Porotchkin #define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 439*0ade8cd8SKonstantin Porotchkin #define HPIPE_RX_SAMPLER_OS_GAIN_MASK \ 440*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET) 441*0ade8cd8SKonstantin Porotchkin #define HPIPE_SMAPLER_OFFSET 12 442*0ade8cd8SKonstantin Porotchkin #define HPIPE_SMAPLER_MASK \ 443*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_SMAPLER_OFFSET) 444*0ade8cd8SKonstantin Porotchkin 445*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_REG1_REG 0x174 446*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 447*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_REG1_TX_EMPH_RES_MASK \ 448*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) 449*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_REG1_SLC_EN_OFFSET 10 450*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_REG1_SLC_EN_MASK \ 451*0ade8cd8SKonstantin Porotchkin (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET) 452*0ade8cd8SKonstantin Porotchkin 453*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_DTL_REG 0x184 454*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 455*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \ 456*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET) 457*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1 458*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \ 459*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) 460*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 461*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ 462*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) 463*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4 464*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \ 465*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) 466*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10 467*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \ 468*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) 469*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12 470*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \ 471*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) 472*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14 473*0ade8cd8SKonstantin Porotchkin #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \ 474*0ade8cd8SKonstantin Porotchkin (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET) 475*0ade8cd8SKonstantin Porotchkin 476*0ade8cd8SKonstantin Porotchkin #define HPIPE_PHASE_CONTROL_REG 0x188 477*0ade8cd8SKonstantin Porotchkin #define HPIPE_OS_PH_OFFSET_OFFSET 0 478*0ade8cd8SKonstantin Porotchkin #define HPIPE_OS_PH_OFFSET_MASK \ 479*0ade8cd8SKonstantin Porotchkin (0x7f << HPIPE_OS_PH_OFFSET_OFFSET) 480*0ade8cd8SKonstantin Porotchkin #define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7 481*0ade8cd8SKonstantin Porotchkin #define HPIPE_OS_PH_OFFSET_FORCE_MASK \ 482*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) 483*0ade8cd8SKonstantin Porotchkin #define HPIPE_OS_PH_VALID_OFFSET 8 484*0ade8cd8SKonstantin Porotchkin #define HPIPE_OS_PH_VALID_MASK \ 485*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_OS_PH_VALID_OFFSET) 486*0ade8cd8SKonstantin Porotchkin 487*0ade8cd8SKonstantin Porotchkin #define HPIPE_SQ_GLITCH_FILTER_CTRL 0x1c8 488*0ade8cd8SKonstantin Porotchkin #define HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET 0 489*0ade8cd8SKonstantin Porotchkin #define HPIPE_SQ_DEGLITCH_WIDTH_P_MASK \ 490*0ade8cd8SKonstantin Porotchkin (0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET) 491*0ade8cd8SKonstantin Porotchkin #define HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET 4 492*0ade8cd8SKonstantin Porotchkin #define HPIPE_SQ_DEGLITCH_WIDTH_N_MASK \ 493*0ade8cd8SKonstantin Porotchkin (0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET) 494*0ade8cd8SKonstantin Porotchkin #define HPIPE_SQ_DEGLITCH_EN_OFFSET 8 495*0ade8cd8SKonstantin Porotchkin #define HPIPE_SQ_DEGLITCH_EN_MASK \ 496*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET) 497*0ade8cd8SKonstantin Porotchkin 498*0ade8cd8SKonstantin Porotchkin #define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214 499*0ade8cd8SKonstantin Porotchkin #define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7 500*0ade8cd8SKonstantin Porotchkin #define HPIPE_TRAIN_PAT_NUM_MASK \ 501*0ade8cd8SKonstantin Porotchkin (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET) 502*0ade8cd8SKonstantin Porotchkin 503*0ade8cd8SKonstantin Porotchkin #define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220 504*0ade8cd8SKonstantin Porotchkin #define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12 505*0ade8cd8SKonstantin Porotchkin #define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \ 506*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET) 507*0ade8cd8SKonstantin Porotchkin 508*0ade8cd8SKonstantin Porotchkin #define HPIPE_DME_REG 0x228 509*0ade8cd8SKonstantin Porotchkin #define HPIPE_DME_ETHERNET_MODE_OFFSET 7 510*0ade8cd8SKonstantin Porotchkin #define HPIPE_DME_ETHERNET_MODE_MASK \ 511*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET) 512*0ade8cd8SKonstantin Porotchkin 513*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 514*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 515*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ 516*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) 517*0ade8cd8SKonstantin Porotchkin 518*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_CTRL_REG 0x26C 519*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 520*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_CTRL_G1_MASK \ 521*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) 522*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 523*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_CTRL_GN1_MASK \ 524*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) 525*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 526*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_CTRL_G0_MASK \ 527*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) 528*0ade8cd8SKonstantin Porotchkin 529*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 530*0ade8cd8SKonstantin Porotchkin #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 531*0ade8cd8SKonstantin Porotchkin #define HPIPE_TRX_TRAIN_TIMER_MASK \ 532*0ade8cd8SKonstantin Porotchkin (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) 533*0ade8cd8SKonstantin Porotchkin 534*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 535*0ade8cd8SKonstantin Porotchkin #define HPIPE_RX_TRAIN_TIMER_OFFSET 0 536*0ade8cd8SKonstantin Porotchkin #define HPIPE_RX_TRAIN_TIMER_MASK \ 537*0ade8cd8SKonstantin Porotchkin (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET) 538*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 539*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ 540*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) 541*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 542*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \ 543*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) 544*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 545*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \ 546*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) 547*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 548*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \ 549*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) 550*0ade8cd8SKonstantin Porotchkin 551*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_REG 0x31C 552*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 553*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_CHK_INIT_MASK \ 554*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) 555*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 556*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ 557*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) 558*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8 559*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \ 560*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET) 561*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9 562*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_PAT_SEL_MASK \ 563*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET) 564*0ade8cd8SKonstantin Porotchkin 565*0ade8cd8SKonstantin Porotchkin #define HPIPE_SAVED_DFE_VALUES_REG 0x328 566*0ade8cd8SKonstantin Porotchkin #define HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET 10 567*0ade8cd8SKonstantin Porotchkin #define HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK \ 568*0ade8cd8SKonstantin Porotchkin (0x3f << HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET) 569*0ade8cd8SKonstantin Porotchkin 570*0ade8cd8SKonstantin Porotchkin #define HPIPE_CDR_CONTROL_REG 0x418 571*0ade8cd8SKonstantin Porotchkin #define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET 14 572*0ade8cd8SKonstantin Porotchkin #define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK \ 573*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET) 574*0ade8cd8SKonstantin Porotchkin #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12 575*0ade8cd8SKonstantin Porotchkin #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \ 576*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET) 577*0ade8cd8SKonstantin Porotchkin #define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9 578*0ade8cd8SKonstantin Porotchkin #define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \ 579*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET) 580*0ade8cd8SKonstantin Porotchkin #define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6 581*0ade8cd8SKonstantin Porotchkin #define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \ 582*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET) 583*0ade8cd8SKonstantin Porotchkin 584*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 585*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 586*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \ 587*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) 588*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 589*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_NUM_OF_PRESET_MASK \ 590*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) 591*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 592*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_SWEEP_PRESET_EN_MASK \ 593*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) 594*0ade8cd8SKonstantin Porotchkin 595*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_3_REG 0x440 596*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0 597*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \ 598*0ade8cd8SKonstantin Porotchkin (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET) 599*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4 600*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \ 601*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET) 602*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7 603*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \ 604*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET) 605*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9 606*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \ 607*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET) 608*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12 609*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \ 610*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET) 611*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14 612*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \ 613*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET) 614*0ade8cd8SKonstantin Porotchkin 615*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_4_REG 0x444 616*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8 617*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \ 618*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET) 619*0ade8cd8SKonstantin Porotchkin 620*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_SETTINGS_4_REG 0x44c 621*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_DFE_RES_OFFSET 8 622*0ade8cd8SKonstantin Porotchkin #define HPIPE_G2_DFE_RES_MASK \ 623*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_G2_DFE_RES_OFFSET) 624*0ade8cd8SKonstantin Porotchkin 625*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SETTING_3_REG 0x450 626*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_FFE_CAP_SEL_OFFSET 0 627*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_FFE_CAP_SEL_MASK \ 628*0ade8cd8SKonstantin Porotchkin (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) 629*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_FFE_RES_SEL_OFFSET 4 630*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_FFE_RES_SEL_MASK \ 631*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) 632*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7 633*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_FFE_SETTING_FORCE_MASK \ 634*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) 635*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 636*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \ 637*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) 638*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14 639*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \ 640*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) 641*0ade8cd8SKonstantin Porotchkin 642*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SETTING_4_REG 0x454 643*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_DFE_RES_OFFSET 8 644*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_DFE_RES_MASK (0x3 << HPIPE_G3_DFE_RES_OFFSET) 645*0ade8cd8SKonstantin Porotchkin 646*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_PRESET_INDEX_REG 0x468 647*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_PRESET_INDEX_OFFSET 0 648*0ade8cd8SKonstantin Porotchkin #define HPIPE_TX_PRESET_INDEX_MASK \ 649*0ade8cd8SKonstantin Porotchkin (0xf << HPIPE_TX_PRESET_INDEX_OFFSET) 650*0ade8cd8SKonstantin Porotchkin 651*0ade8cd8SKonstantin Porotchkin #define HPIPE_DFE_CONTROL_REG 0x470 652*0ade8cd8SKonstantin Porotchkin #define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14 653*0ade8cd8SKonstantin Porotchkin #define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \ 654*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) 655*0ade8cd8SKonstantin Porotchkin 656*0ade8cd8SKonstantin Porotchkin #define HPIPE_DFE_CTRL_28_REG 0x49C 657*0ade8cd8SKonstantin Porotchkin #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 658*0ade8cd8SKonstantin Porotchkin #define HPIPE_DFE_CTRL_28_PIPE4_MASK \ 659*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) 660*0ade8cd8SKonstantin Porotchkin 661*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTING_5_REG 0x538 662*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0 663*0ade8cd8SKonstantin Porotchkin #define HPIPE_G1_SETTING_5_G1_ICP_MASK \ 664*0ade8cd8SKonstantin Porotchkin (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET) 665*0ade8cd8SKonstantin Porotchkin 666*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SETTING_5_REG 0x548 667*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0 668*0ade8cd8SKonstantin Porotchkin #define HPIPE_G3_SETTING_5_G3_ICP_MASK \ 669*0ade8cd8SKonstantin Porotchkin (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET) 670*0ade8cd8SKonstantin Porotchkin 671*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CONFIG0_REG 0x600 672*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0 673*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \ 674*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET) 675*0ade8cd8SKonstantin Porotchkin 676*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_STATUS1_REG 0x60C 677*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0 678*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_STATUS1_PCLK_EN_MASK \ 679*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) 680*0ade8cd8SKonstantin Porotchkin 681*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CFG4_REG 0x620 682*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 683*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CFG4_DFE_CTRL_MASK \ 684*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) 685*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3 686*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \ 687*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET) 688*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 689*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CFG4_DFE_OVER_MASK \ 690*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) 691*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7 692*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CFG4_SSC_CTRL_MASK \ 693*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET) 694*0ade8cd8SKonstantin Porotchkin 695*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8 696*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0 697*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \ 698*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) 699*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1 700*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \ 701*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) 702*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2 703*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \ 704*0ade8cd8SKonstantin Porotchkin (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET) 705*0ade8cd8SKonstantin Porotchkin 706*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C 707*0ade8cd8SKonstantin Porotchkin #define HPIPE_CFG_PHY_RC_EP_OFFSET 12 708*0ade8cd8SKonstantin Porotchkin #define HPIPE_CFG_PHY_RC_EP_MASK \ 709*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) 710*0ade8cd8SKonstantin Porotchkin 711*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_EQ_CFG1_REG 0x6a0 712*0ade8cd8SKonstantin Porotchkin #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 713*0ade8cd8SKonstantin Porotchkin #define HPIPE_CFG_UPDATE_POLARITY_MASK \ 714*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) 715*0ade8cd8SKonstantin Porotchkin 716*0ade8cd8SKonstantin Porotchkin #define HPIPE_LANE_EQ_CFG2_REG 0x6a4 717*0ade8cd8SKonstantin Porotchkin #define HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET 14 718*0ade8cd8SKonstantin Porotchkin #define HPIPE_CFG_EQ_BUNDLE_DIS_MASK \ 719*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET) 720*0ade8cd8SKonstantin Porotchkin 721*0ade8cd8SKonstantin Porotchkin #define HPIPE_RST_CLK_CTRL_REG 0x704 722*0ade8cd8SKonstantin Porotchkin #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 723*0ade8cd8SKonstantin Porotchkin #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \ 724*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) 725*0ade8cd8SKonstantin Porotchkin #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 726*0ade8cd8SKonstantin Porotchkin #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \ 727*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) 728*0ade8cd8SKonstantin Porotchkin #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 729*0ade8cd8SKonstantin Porotchkin #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \ 730*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) 731*0ade8cd8SKonstantin Porotchkin #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 732*0ade8cd8SKonstantin Porotchkin #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \ 733*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) 734*0ade8cd8SKonstantin Porotchkin 735*0ade8cd8SKonstantin Porotchkin #define HPIPE_TST_MODE_CTRL_REG 0x708 736*0ade8cd8SKonstantin Porotchkin #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2 737*0ade8cd8SKonstantin Porotchkin #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \ 738*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET) 739*0ade8cd8SKonstantin Porotchkin 740*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_LO_REG 0x70c 741*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 742*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \ 743*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) 744*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 745*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \ 746*0ade8cd8SKonstantin Porotchkin (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) 747*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 748*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \ 749*0ade8cd8SKonstantin Porotchkin (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) 750*0ade8cd8SKonstantin Porotchkin 751*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_HI_REG 0x710 752*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 753*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \ 754*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) 755*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 756*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \ 757*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) 758*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 759*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \ 760*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) 761*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 762*0ade8cd8SKonstantin Porotchkin #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \ 763*0ade8cd8SKonstantin Porotchkin (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) 764*0ade8cd8SKonstantin Porotchkin 765*0ade8cd8SKonstantin Porotchkin #define HPIPE_GLOBAL_MISC_CTRL 0x718 766*0ade8cd8SKonstantin Porotchkin #define HPIPE_GLOBAL_PM_CTRL 0x740 767*0ade8cd8SKonstantin Porotchkin #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 768*0ade8cd8SKonstantin Porotchkin #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \ 769*0ade8cd8SKonstantin Porotchkin (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) 770*0ade8cd8SKonstantin Porotchkin 771*0ade8cd8SKonstantin Porotchkin /* General defines */ 772*0ade8cd8SKonstantin Porotchkin #define PLL_LOCK_TIMEOUT 15000 773*0ade8cd8SKonstantin Porotchkin 774*0ade8cd8SKonstantin Porotchkin #endif /* _PHY_COMPHY_CP110_H */ 775*0ade8cd8SKonstantin Porotchkin 776