1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 /* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */ 9 10 #include <a8k_common.h> 11 #include <ccu.h> 12 #include <debug.h> 13 #include <mmio.h> 14 #include <mvebu.h> 15 #include <mvebu_def.h> 16 17 #if LOG_LEVEL >= LOG_LEVEL_INFO 18 #define DEBUG_ADDR_MAP 19 #endif 20 21 /* common defines */ 22 #define WIN_ENABLE_BIT (0x1) 23 /* Physical address of the base of the window = {AddrLow[19:0],20’h0} */ 24 #define ADDRESS_SHIFT (20 - 4) 25 #define ADDRESS_MASK (0xFFFFFFF0) 26 #define CCU_WIN_ALIGNMENT (0x100000) 27 28 #define IS_DRAM_TARGET(tgt) ((((tgt) == DRAM_0_TID) || \ 29 ((tgt) == DRAM_1_TID) || \ 30 ((tgt) == RAR_TID)) ? 1 : 0) 31 32 /* For storage of CR, SCR, ALR, AHR abd GCR */ 33 static uint32_t ccu_regs_save[MVEBU_CCU_MAX_WINS * 4 + 1]; 34 35 #ifdef DEBUG_ADDR_MAP 36 static void dump_ccu(int ap_index) 37 { 38 uint32_t win_id, win_cr, alr, ahr; 39 uint8_t target_id; 40 uint64_t start, end; 41 42 /* Dump all AP windows */ 43 tf_printf("\tbank target start end\n"); 44 tf_printf("\t----------------------------------------------------\n"); 45 for (win_id = 0; win_id < MVEBU_CCU_MAX_WINS; win_id++) { 46 win_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 47 if (win_cr & WIN_ENABLE_BIT) { 48 target_id = (win_cr >> CCU_TARGET_ID_OFFSET) & 49 CCU_TARGET_ID_MASK; 50 alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, 51 win_id)); 52 ahr = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_index, 53 win_id)); 54 start = ((uint64_t)alr << ADDRESS_SHIFT); 55 end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT); 56 tf_printf("\tccu %02x 0x%016llx 0x%016llx\n", 57 target_id, start, end); 58 } 59 } 60 win_cr = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_index)); 61 target_id = (win_cr >> CCU_GCR_TARGET_OFFSET) & CCU_GCR_TARGET_MASK; 62 tf_printf("\tccu GCR %d - all other transactions\n", target_id); 63 } 64 #endif 65 66 void ccu_win_check(struct addr_map_win *win) 67 { 68 /* check if address is aligned to 1M */ 69 if (IS_NOT_ALIGN(win->base_addr, CCU_WIN_ALIGNMENT)) { 70 win->base_addr = ALIGN_UP(win->base_addr, CCU_WIN_ALIGNMENT); 71 NOTICE("%s: Align up the base address to 0x%llx\n", 72 __func__, win->base_addr); 73 } 74 75 /* size parameter validity check */ 76 if (IS_NOT_ALIGN(win->win_size, CCU_WIN_ALIGNMENT)) { 77 win->win_size = ALIGN_UP(win->win_size, CCU_WIN_ALIGNMENT); 78 NOTICE("%s: Aligning size to 0x%llx\n", 79 __func__, win->win_size); 80 } 81 } 82 83 void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id) 84 { 85 uint32_t ccu_win_reg; 86 uint32_t alr, ahr; 87 uint64_t end_addr; 88 89 if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) { 90 ERROR("Enabling wrong CCU window %d!\n", win_id); 91 return; 92 } 93 94 end_addr = (win->base_addr + win->win_size - 1); 95 alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); 96 ahr = (uint32_t)((end_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); 97 98 mmio_write_32(CCU_WIN_ALR_OFFSET(ap_index, win_id), alr); 99 mmio_write_32(CCU_WIN_AHR_OFFSET(ap_index, win_id), ahr); 100 101 ccu_win_reg = WIN_ENABLE_BIT; 102 ccu_win_reg |= (win->target_id & CCU_TARGET_ID_MASK) 103 << CCU_TARGET_ID_OFFSET; 104 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), ccu_win_reg); 105 } 106 107 static void ccu_disable_win(int ap_index, uint32_t win_id) 108 { 109 uint32_t win_reg; 110 111 if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) { 112 ERROR("Disabling wrong CCU window %d!\n", win_id); 113 return; 114 } 115 116 win_reg = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 117 win_reg &= ~WIN_ENABLE_BIT; 118 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), win_reg); 119 } 120 121 /* Insert/Remove temporary window for using the out-of reset default 122 * CPx base address to access the CP configuration space prior to 123 * the further base address update in accordance with address mapping 124 * design. 125 * 126 * NOTE: Use the same window array for insertion and removal of 127 * temporary windows. 128 */ 129 void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size) 130 { 131 uint32_t win_id; 132 133 for (int i = 0; i < size; i++) { 134 win_id = MVEBU_CCU_MAX_WINS - 1 - i; 135 ccu_win_check(win); 136 ccu_enable_win(ap_index, win, win_id); 137 win++; 138 } 139 } 140 141 /* 142 * NOTE: Use the same window array for insertion and removal of 143 * temporary windows. 144 */ 145 void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size) 146 { 147 uint32_t win_id; 148 149 for (int i = 0; i < size; i++) { 150 uint64_t base; 151 uint32_t target; 152 153 win_id = MVEBU_CCU_MAX_WINS - 1 - i; 154 155 target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 156 target >>= CCU_TARGET_ID_OFFSET; 157 target &= CCU_TARGET_ID_MASK; 158 159 base = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, win_id)); 160 base <<= ADDRESS_SHIFT; 161 162 if ((win->target_id != target) || (win->base_addr != base)) { 163 ERROR("%s: Trying to remove bad window-%d!\n", 164 __func__, win_id); 165 continue; 166 } 167 ccu_disable_win(ap_index, win_id); 168 win++; 169 } 170 } 171 172 /* Returns current DRAM window target (DRAM_0_TID, DRAM_1_TID, RAR_TID) 173 * NOTE: Call only once for each AP. 174 * The AP0 DRAM window is located at index 2 only at the BL31 execution start. 175 * Then it relocated to index 1 for matching the rest of APs DRAM settings. 176 * Calling this function after relocation will produce wrong results on AP0 177 */ 178 static uint32_t ccu_dram_target_get(int ap_index) 179 { 180 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 181 * All the rest of detected APs will use window at index 1. 182 * The AP0 DRAM window is moved from index 2 to 1 during 183 * init_ccu() execution. 184 */ 185 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 186 uint32_t target; 187 188 target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 189 target >>= CCU_TARGET_ID_OFFSET; 190 target &= CCU_TARGET_ID_MASK; 191 192 return target; 193 } 194 195 void ccu_dram_target_set(int ap_index, uint32_t target) 196 { 197 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 198 * All the rest of detected APs will use window at index 1. 199 * The AP0 DRAM window is moved from index 2 to 1 200 * during init_ccu() execution. 201 */ 202 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 203 uint32_t dram_cr; 204 205 dram_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 206 dram_cr &= ~(CCU_TARGET_ID_MASK << CCU_TARGET_ID_OFFSET); 207 dram_cr |= (target & CCU_TARGET_ID_MASK) << CCU_TARGET_ID_OFFSET; 208 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), dram_cr); 209 } 210 211 /* Setup CCU DRAM window and enable it */ 212 void ccu_dram_win_config(int ap_index, struct addr_map_win *win) 213 { 214 #if IMAGE_BLE /* BLE */ 215 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 216 * Since the BootROM is not accessing DRAM at BLE stage, 217 * the DRAM window can be temporarely disabled. 218 */ 219 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 220 #else /* end of BLE */ 221 /* At the ccu_init() execution stage, DRAM windows of all APs 222 * are arranged at index 1. 223 * The AP0 still has the old window BootROM DRAM at index 2, so 224 * the window-1 can be safely disabled without breaking the DRAM access. 225 */ 226 const uint32_t win_id = 1; 227 #endif 228 229 ccu_disable_win(ap_index, win_id); 230 /* enable write secure (and clear read secure) */ 231 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), 232 CCU_WIN_ENA_WRITE_SECURE); 233 ccu_win_check(win); 234 ccu_enable_win(ap_index, win, win_id); 235 } 236 237 /* Save content of CCU window + GCR */ 238 static void ccu_save_win_range(int ap_id, int win_first, 239 int win_last, uint32_t *buffer) 240 { 241 int win_id, idx; 242 /* Save CCU */ 243 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { 244 buffer[idx++] = mmio_read_32(CCU_WIN_CR_OFFSET(ap_id, win_id)); 245 buffer[idx++] = mmio_read_32(CCU_WIN_SCR_OFFSET(ap_id, win_id)); 246 buffer[idx++] = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_id, win_id)); 247 buffer[idx++] = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_id, win_id)); 248 } 249 buffer[idx] = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_id)); 250 } 251 252 /* Restore content of CCU window + GCR */ 253 static void ccu_restore_win_range(int ap_id, int win_first, 254 int win_last, uint32_t *buffer) 255 { 256 int win_id, idx; 257 /* Restore CCU */ 258 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { 259 mmio_write_32(CCU_WIN_CR_OFFSET(ap_id, win_id), buffer[idx++]); 260 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_id, win_id), buffer[idx++]); 261 mmio_write_32(CCU_WIN_ALR_OFFSET(ap_id, win_id), buffer[idx++]); 262 mmio_write_32(CCU_WIN_AHR_OFFSET(ap_id, win_id), buffer[idx++]); 263 } 264 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_id), buffer[idx]); 265 } 266 267 void ccu_save_win_all(int ap_id) 268 { 269 ccu_save_win_range(ap_id, 0, MVEBU_CCU_MAX_WINS - 1, ccu_regs_save); 270 } 271 272 void ccu_restore_win_all(int ap_id) 273 { 274 ccu_restore_win_range(ap_id, 0, MVEBU_CCU_MAX_WINS - 1, ccu_regs_save); 275 } 276 277 int init_ccu(int ap_index) 278 { 279 struct addr_map_win *win, *dram_win; 280 uint32_t win_id, win_reg; 281 uint32_t win_count, array_id; 282 uint32_t dram_target; 283 #if IMAGE_BLE 284 /* In BootROM context CCU Window-1 285 * has SRAM_TID target and should not be disabled 286 */ 287 const uint32_t win_start = 2; 288 #else 289 const uint32_t win_start = 1; 290 #endif 291 292 INFO("Initializing CCU Address decoding\n"); 293 294 /* Get the array of the windows and fill the map data */ 295 marvell_get_ccu_memory_map(ap_index, &win, &win_count); 296 if (win_count <= 0) { 297 INFO("No windows configurations found\n"); 298 } else if (win_count > (MVEBU_CCU_MAX_WINS - 1)) { 299 ERROR("CCU mem map array > than max available windows (%d)\n", 300 MVEBU_CCU_MAX_WINS); 301 win_count = MVEBU_CCU_MAX_WINS; 302 } 303 304 /* Need to set GCR to DRAM before all CCU windows are disabled for 305 * securing the normal access to DRAM location, which the ATF is running 306 * from. Once all CCU windows are set, which have to include the 307 * dedicated DRAM window as well, the GCR can be switched to the target 308 * defined by the platform configuration. 309 */ 310 dram_target = ccu_dram_target_get(ap_index); 311 win_reg = (dram_target & CCU_GCR_TARGET_MASK) << CCU_GCR_TARGET_OFFSET; 312 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); 313 314 /* If the DRAM window was already configured at the BLE stage, 315 * only the window target considered valid, the address range should be 316 * updated according to the platform configuration. 317 */ 318 for (dram_win = win, array_id = 0; array_id < win_count; 319 array_id++, dram_win++) { 320 if (IS_DRAM_TARGET(dram_win->target_id)) { 321 dram_win->target_id = dram_target; 322 break; 323 } 324 } 325 326 /* Disable all AP CCU windows 327 * Window-0 is always bypassed since it already contains 328 * data allowing the internal configuration space access 329 */ 330 for (win_id = win_start; win_id < MVEBU_CCU_MAX_WINS; win_id++) { 331 ccu_disable_win(ap_index, win_id); 332 /* enable write secure (and clear read secure) */ 333 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), 334 CCU_WIN_ENA_WRITE_SECURE); 335 } 336 337 /* win_id is the index of the current ccu window 338 * array_id is the index of the current memory map window entry 339 */ 340 for (win_id = win_start, array_id = 0; 341 ((win_id < MVEBU_CCU_MAX_WINS) && (array_id < win_count)); 342 win_id++) { 343 ccu_win_check(win); 344 ccu_enable_win(ap_index, win, win_id); 345 win++; 346 array_id++; 347 } 348 349 /* Get & set the default target according to board topology */ 350 win_reg = (marvell_get_ccu_gcr_target(ap_index) & CCU_GCR_TARGET_MASK) 351 << CCU_GCR_TARGET_OFFSET; 352 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); 353 354 #ifdef DEBUG_ADDR_MAP 355 dump_ccu(ap_index); 356 #endif 357 358 INFO("Done CCU Address decoding Initializing\n"); 359 360 return 0; 361 } 362