1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 /* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */ 9 10 #include <common/debug.h> 11 #include <drivers/marvell/ccu.h> 12 #include <lib/mmio.h> 13 14 #include <armada_common.h> 15 #include <mvebu.h> 16 #include <mvebu_def.h> 17 18 #if LOG_LEVEL >= LOG_LEVEL_INFO 19 #define DEBUG_ADDR_MAP 20 #endif 21 22 /* common defines */ 23 #define WIN_ENABLE_BIT (0x1) 24 /* Physical address of the base of the window = {AddrLow[19:0],20'h0} */ 25 #define ADDRESS_SHIFT (20 - 4) 26 #define ADDRESS_MASK (0xFFFFFFF0) 27 #define CCU_WIN_ALIGNMENT (0x100000) 28 29 /* 30 * Physical address of the highest address of window bits[31:19] = 0x6FF 31 * Physical address of the lowest address of window bits[18:6] = 0x6E0 32 * Unit Id bits [5:2] = 2 33 * RGF Window Enable bit[0] = 1 34 * 0x37f9b809 - 11011111111 0011011100000 0010 0 1 35 */ 36 #define ERRATA_WA_CCU_WIN4 0x37f9b809U 37 38 /* 39 * Physical address of the highest address of window bits[31:19] = 0xFFF 40 * Physical address of the lowest address of window bits[18:6] = 0x800 41 * Unit Id bits [5:2] = 2 42 * RGF Window Enable bit[0] = 1 43 * 0x7ffa0009 - 111111111111 0100000000000 0010 0 1 44 */ 45 #define ERRATA_WA_CCU_WIN5 0x7ffa0009U 46 47 /* 48 * Physical address of the highest address of window bits[31:19] = 0x1FFF 49 * Physical address of the lowest address of window bits[18:6] = 0x1000 50 * Unit Id bits [5:2] = 2 51 * RGF Window Enable bit[0] = 1 52 * 0xfffc000d - 1111111111111 1000000000000 0011 0 1 53 */ 54 #define ERRATA_WA_CCU_WIN6 0xfffc000dU 55 56 #define IS_DRAM_TARGET(tgt) ((((tgt) == DRAM_0_TID) || \ 57 ((tgt) == DRAM_1_TID) || \ 58 ((tgt) == RAR_TID)) ? 1 : 0) 59 60 #define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \ 61 0x90 + 4 * (win)) 62 63 /* For storage of CR, SCR, ALR, AHR abd GCR */ 64 static uint32_t ccu_regs_save[MVEBU_CCU_MAX_WINS * 4 + 1]; 65 66 #ifdef DEBUG_ADDR_MAP 67 static void dump_ccu(int ap_index) 68 { 69 uint32_t win_id, win_cr, alr, ahr; 70 uint8_t target_id; 71 uint64_t start, end; 72 73 /* Dump all AP windows */ 74 printf("\tbank target start end\n"); 75 printf("\t----------------------------------------------------\n"); 76 for (win_id = 0; win_id < MVEBU_CCU_MAX_WINS; win_id++) { 77 win_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 78 if (win_cr & WIN_ENABLE_BIT) { 79 target_id = (win_cr >> CCU_TARGET_ID_OFFSET) & 80 CCU_TARGET_ID_MASK; 81 alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, 82 win_id)); 83 ahr = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_index, 84 win_id)); 85 start = ((uint64_t)alr << ADDRESS_SHIFT); 86 end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT); 87 printf("\tccu%d %02x 0x%016llx 0x%016llx\n", 88 win_id, target_id, start, end); 89 } 90 } 91 win_cr = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_index)); 92 target_id = (win_cr >> CCU_GCR_TARGET_OFFSET) & CCU_GCR_TARGET_MASK; 93 printf("\tccu GCR %d - all other transactions\n", target_id); 94 } 95 #endif 96 97 void ccu_win_check(struct addr_map_win *win) 98 { 99 /* check if address is aligned to 1M */ 100 if (IS_NOT_ALIGN(win->base_addr, CCU_WIN_ALIGNMENT)) { 101 win->base_addr = ALIGN_UP(win->base_addr, CCU_WIN_ALIGNMENT); 102 NOTICE("%s: Align up the base address to 0x%llx\n", 103 __func__, win->base_addr); 104 } 105 106 /* size parameter validity check */ 107 if (IS_NOT_ALIGN(win->win_size, CCU_WIN_ALIGNMENT)) { 108 win->win_size = ALIGN_UP(win->win_size, CCU_WIN_ALIGNMENT); 109 NOTICE("%s: Aligning size to 0x%llx\n", 110 __func__, win->win_size); 111 } 112 } 113 114 int ccu_is_win_enabled(int ap_index, uint32_t win_id) 115 { 116 return mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)) & 117 WIN_ENABLE_BIT; 118 } 119 120 void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id) 121 { 122 uint32_t ccu_win_reg; 123 uint32_t alr, ahr; 124 uint64_t end_addr; 125 126 if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) { 127 ERROR("Enabling wrong CCU window %d!\n", win_id); 128 return; 129 } 130 131 end_addr = (win->base_addr + win->win_size - 1); 132 alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); 133 ahr = (uint32_t)((end_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); 134 135 mmio_write_32(CCU_WIN_ALR_OFFSET(ap_index, win_id), alr); 136 mmio_write_32(CCU_WIN_AHR_OFFSET(ap_index, win_id), ahr); 137 138 ccu_win_reg = WIN_ENABLE_BIT; 139 ccu_win_reg |= (win->target_id & CCU_TARGET_ID_MASK) 140 << CCU_TARGET_ID_OFFSET; 141 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), ccu_win_reg); 142 } 143 144 static void ccu_disable_win(int ap_index, uint32_t win_id) 145 { 146 uint32_t win_reg; 147 148 if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) { 149 ERROR("Disabling wrong CCU window %d!\n", win_id); 150 return; 151 } 152 153 win_reg = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 154 win_reg &= ~WIN_ENABLE_BIT; 155 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), win_reg); 156 } 157 158 /* Insert/Remove temporary window for using the out-of reset default 159 * CPx base address to access the CP configuration space prior to 160 * the further base address update in accordance with address mapping 161 * design. 162 * 163 * NOTE: Use the same window array for insertion and removal of 164 * temporary windows. 165 */ 166 void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size) 167 { 168 uint32_t win_id; 169 170 for (int i = 0; i < size; i++) { 171 win_id = MVEBU_CCU_MAX_WINS - 1 - i; 172 ccu_win_check(win); 173 ccu_enable_win(ap_index, win, win_id); 174 win++; 175 } 176 } 177 178 /* 179 * NOTE: Use the same window array for insertion and removal of 180 * temporary windows. 181 */ 182 void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size) 183 { 184 uint32_t win_id; 185 186 for (int i = 0; i < size; i++) { 187 uint64_t base; 188 uint32_t target; 189 190 win_id = MVEBU_CCU_MAX_WINS - 1 - i; 191 192 target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 193 target >>= CCU_TARGET_ID_OFFSET; 194 target &= CCU_TARGET_ID_MASK; 195 196 base = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, win_id)); 197 base <<= ADDRESS_SHIFT; 198 199 if ((win->target_id != target) || (win->base_addr != base)) { 200 ERROR("%s: Trying to remove bad window-%d!\n", 201 __func__, win_id); 202 continue; 203 } 204 ccu_disable_win(ap_index, win_id); 205 win++; 206 } 207 } 208 209 /* Returns current DRAM window target (DRAM_0_TID, DRAM_1_TID, RAR_TID) 210 * NOTE: Call only once for each AP. 211 * The AP0 DRAM window is located at index 2 only at the BL31 execution start. 212 * Then it relocated to index 1 for matching the rest of APs DRAM settings. 213 * Calling this function after relocation will produce wrong results on AP0 214 */ 215 static uint32_t ccu_dram_target_get(int ap_index) 216 { 217 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 218 * All the rest of detected APs will use window at index 1. 219 * The AP0 DRAM window is moved from index 2 to 1 during 220 * init_ccu() execution. 221 */ 222 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 223 uint32_t target; 224 225 target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 226 target >>= CCU_TARGET_ID_OFFSET; 227 target &= CCU_TARGET_ID_MASK; 228 229 return target; 230 } 231 232 void ccu_dram_target_set(int ap_index, uint32_t target) 233 { 234 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 235 * All the rest of detected APs will use window at index 1. 236 * The AP0 DRAM window is moved from index 2 to 1 237 * during init_ccu() execution. 238 */ 239 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 240 uint32_t dram_cr; 241 242 dram_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 243 dram_cr &= ~(CCU_TARGET_ID_MASK << CCU_TARGET_ID_OFFSET); 244 dram_cr |= (target & CCU_TARGET_ID_MASK) << CCU_TARGET_ID_OFFSET; 245 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), dram_cr); 246 } 247 248 /* Setup CCU DRAM window and enable it */ 249 void ccu_dram_win_config(int ap_index, struct addr_map_win *win) 250 { 251 #if IMAGE_BLE /* BLE */ 252 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 253 * Since the BootROM is not accessing DRAM at BLE stage, 254 * the DRAM window can be temporarely disabled. 255 */ 256 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 257 #else /* end of BLE */ 258 /* At the ccu_init() execution stage, DRAM windows of all APs 259 * are arranged at index 1. 260 * The AP0 still has the old window BootROM DRAM at index 2, so 261 * the window-1 can be safely disabled without breaking the DRAM access. 262 */ 263 const uint32_t win_id = 1; 264 #endif 265 266 ccu_disable_win(ap_index, win_id); 267 /* enable write secure (and clear read secure) */ 268 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), 269 CCU_WIN_ENA_WRITE_SECURE); 270 ccu_win_check(win); 271 ccu_enable_win(ap_index, win, win_id); 272 } 273 274 /* Save content of CCU window + GCR */ 275 static void ccu_save_win_range(int ap_id, int win_first, 276 int win_last, uint32_t *buffer) 277 { 278 int win_id, idx; 279 /* Save CCU */ 280 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { 281 buffer[idx++] = mmio_read_32(CCU_WIN_CR_OFFSET(ap_id, win_id)); 282 buffer[idx++] = mmio_read_32(CCU_WIN_SCR_OFFSET(ap_id, win_id)); 283 buffer[idx++] = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_id, win_id)); 284 buffer[idx++] = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_id, win_id)); 285 } 286 buffer[idx] = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_id)); 287 } 288 289 /* Restore content of CCU window + GCR */ 290 static void ccu_restore_win_range(int ap_id, int win_first, 291 int win_last, uint32_t *buffer) 292 { 293 int win_id, idx; 294 /* Restore CCU */ 295 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { 296 mmio_write_32(CCU_WIN_CR_OFFSET(ap_id, win_id), buffer[idx++]); 297 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_id, win_id), buffer[idx++]); 298 mmio_write_32(CCU_WIN_ALR_OFFSET(ap_id, win_id), buffer[idx++]); 299 mmio_write_32(CCU_WIN_AHR_OFFSET(ap_id, win_id), buffer[idx++]); 300 } 301 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_id), buffer[idx]); 302 } 303 304 void ccu_save_win_all(int ap_id) 305 { 306 ccu_save_win_range(ap_id, 0, MVEBU_CCU_MAX_WINS - 1, ccu_regs_save); 307 } 308 309 void ccu_restore_win_all(int ap_id) 310 { 311 ccu_restore_win_range(ap_id, 0, MVEBU_CCU_MAX_WINS - 1, ccu_regs_save); 312 } 313 314 int init_ccu(int ap_index) 315 { 316 struct addr_map_win *win, *dram_win; 317 uint32_t win_id, win_reg; 318 uint32_t win_count, array_id; 319 uint32_t dram_target; 320 #if IMAGE_BLE 321 /* In BootROM context CCU Window-1 322 * has SRAM_TID target and should not be disabled 323 */ 324 const uint32_t win_start = 2; 325 #else 326 const uint32_t win_start = 1; 327 #endif 328 329 INFO("Initializing CCU Address decoding\n"); 330 331 /* Get the array of the windows and fill the map data */ 332 marvell_get_ccu_memory_map(ap_index, &win, &win_count); 333 if (win_count <= 0) { 334 INFO("No windows configurations found\n"); 335 } else if (win_count > (MVEBU_CCU_MAX_WINS - 1)) { 336 ERROR("CCU mem map array > than max available windows (%d)\n", 337 MVEBU_CCU_MAX_WINS); 338 win_count = MVEBU_CCU_MAX_WINS; 339 } 340 341 /* Need to set GCR to DRAM before all CCU windows are disabled for 342 * securing the normal access to DRAM location, which the ATF is running 343 * from. Once all CCU windows are set, which have to include the 344 * dedicated DRAM window as well, the GCR can be switched to the target 345 * defined by the platform configuration. 346 */ 347 dram_target = ccu_dram_target_get(ap_index); 348 win_reg = (dram_target & CCU_GCR_TARGET_MASK) << CCU_GCR_TARGET_OFFSET; 349 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); 350 351 /* If the DRAM window was already configured at the BLE stage, 352 * only the window target considered valid, the address range should be 353 * updated according to the platform configuration. 354 */ 355 for (dram_win = win, array_id = 0; array_id < win_count; 356 array_id++, dram_win++) { 357 if (IS_DRAM_TARGET(dram_win->target_id)) { 358 dram_win->target_id = dram_target; 359 break; 360 } 361 } 362 363 /* Disable all AP CCU windows 364 * Window-0 is always bypassed since it already contains 365 * data allowing the internal configuration space access 366 */ 367 for (win_id = win_start; win_id < MVEBU_CCU_MAX_WINS; win_id++) { 368 ccu_disable_win(ap_index, win_id); 369 /* enable write secure (and clear read secure) */ 370 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), 371 CCU_WIN_ENA_WRITE_SECURE); 372 } 373 374 /* win_id is the index of the current ccu window 375 * array_id is the index of the current memory map window entry 376 */ 377 for (win_id = win_start, array_id = 0; 378 ((win_id < MVEBU_CCU_MAX_WINS) && (array_id < win_count)); 379 win_id++) { 380 ccu_win_check(win); 381 ccu_enable_win(ap_index, win, win_id); 382 win++; 383 array_id++; 384 } 385 386 /* Get & set the default target according to board topology */ 387 win_reg = (marvell_get_ccu_gcr_target(ap_index) & CCU_GCR_TARGET_MASK) 388 << CCU_GCR_TARGET_OFFSET; 389 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); 390 391 #ifdef DEBUG_ADDR_MAP 392 dump_ccu(ap_index); 393 #endif 394 395 INFO("Done CCU Address decoding Initializing\n"); 396 397 return 0; 398 } 399 400 void errata_wa_init(void) 401 { 402 /* 403 * EERATA ID: RES-3033912 - Internal Address Space Init state causes 404 * a hang upon accesses to [0xf070_0000, 0xf07f_ffff] 405 * Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to 406 * split [0x6e_0000, 0x1ff_ffff] to values [0x6e_0000, 0x6f_ffff] and 407 * [0x80_0000, 0xff_ffff] and [0x100_0000, 0x1ff_ffff],that cause 408 * accesses to the segment of [0xf070_0000, 0xf1ff_ffff] 409 * to act as RAZWI. 410 */ 411 mmio_write_32(CCU_RGF(4), ERRATA_WA_CCU_WIN4); 412 mmio_write_32(CCU_RGF(5), ERRATA_WA_CCU_WIN5); 413 mmio_write_32(CCU_RGF(6), ERRATA_WA_CCU_WIN6); 414 } 415