1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 /* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */ 9 10 #include <common/debug.h> 11 #include <drivers/marvell/ccu.h> 12 #include <lib/mmio.h> 13 14 #include <armada_common.h> 15 #include <mvebu.h> 16 #include <mvebu_def.h> 17 18 #if LOG_LEVEL >= LOG_LEVEL_INFO 19 #define DEBUG_ADDR_MAP 20 #endif 21 22 /* common defines */ 23 #define WIN_ENABLE_BIT (0x1) 24 /* Physical address of the base of the window = {AddrLow[19:0],20'h0} */ 25 #define ADDRESS_SHIFT (20 - 4) 26 #define ADDRESS_MASK (0xFFFFFFF0) 27 #define CCU_WIN_ALIGNMENT (0x100000) 28 29 #define IS_DRAM_TARGET(tgt) ((((tgt) == DRAM_0_TID) || \ 30 ((tgt) == DRAM_1_TID) || \ 31 ((tgt) == RAR_TID)) ? 1 : 0) 32 33 /* For storage of CR, SCR, ALR, AHR abd GCR */ 34 static uint32_t ccu_regs_save[MVEBU_CCU_MAX_WINS * 4 + 1]; 35 36 #ifdef DEBUG_ADDR_MAP 37 static void dump_ccu(int ap_index) 38 { 39 uint32_t win_id, win_cr, alr, ahr; 40 uint8_t target_id; 41 uint64_t start, end; 42 43 /* Dump all AP windows */ 44 printf("\tbank target start end\n"); 45 printf("\t----------------------------------------------------\n"); 46 for (win_id = 0; win_id < MVEBU_CCU_MAX_WINS; win_id++) { 47 win_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 48 if (win_cr & WIN_ENABLE_BIT) { 49 target_id = (win_cr >> CCU_TARGET_ID_OFFSET) & 50 CCU_TARGET_ID_MASK; 51 alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, 52 win_id)); 53 ahr = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_index, 54 win_id)); 55 start = ((uint64_t)alr << ADDRESS_SHIFT); 56 end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT); 57 printf("\tccu%d %02x 0x%016llx 0x%016llx\n", 58 win_id, target_id, start, end); 59 } 60 } 61 win_cr = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_index)); 62 target_id = (win_cr >> CCU_GCR_TARGET_OFFSET) & CCU_GCR_TARGET_MASK; 63 printf("\tccu GCR %d - all other transactions\n", target_id); 64 } 65 #endif 66 67 void ccu_win_check(struct addr_map_win *win) 68 { 69 /* check if address is aligned to 1M */ 70 if (IS_NOT_ALIGN(win->base_addr, CCU_WIN_ALIGNMENT)) { 71 win->base_addr = ALIGN_UP(win->base_addr, CCU_WIN_ALIGNMENT); 72 NOTICE("%s: Align up the base address to 0x%llx\n", 73 __func__, win->base_addr); 74 } 75 76 /* size parameter validity check */ 77 if (IS_NOT_ALIGN(win->win_size, CCU_WIN_ALIGNMENT)) { 78 win->win_size = ALIGN_UP(win->win_size, CCU_WIN_ALIGNMENT); 79 NOTICE("%s: Aligning size to 0x%llx\n", 80 __func__, win->win_size); 81 } 82 } 83 84 int ccu_is_win_enabled(int ap_index, uint32_t win_id) 85 { 86 return mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)) & 87 WIN_ENABLE_BIT; 88 } 89 90 void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id) 91 { 92 uint32_t ccu_win_reg; 93 uint32_t alr, ahr; 94 uint64_t end_addr; 95 96 if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) { 97 ERROR("Enabling wrong CCU window %d!\n", win_id); 98 return; 99 } 100 101 end_addr = (win->base_addr + win->win_size - 1); 102 alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); 103 ahr = (uint32_t)((end_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); 104 105 mmio_write_32(CCU_WIN_ALR_OFFSET(ap_index, win_id), alr); 106 mmio_write_32(CCU_WIN_AHR_OFFSET(ap_index, win_id), ahr); 107 108 ccu_win_reg = WIN_ENABLE_BIT; 109 ccu_win_reg |= (win->target_id & CCU_TARGET_ID_MASK) 110 << CCU_TARGET_ID_OFFSET; 111 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), ccu_win_reg); 112 } 113 114 static void ccu_disable_win(int ap_index, uint32_t win_id) 115 { 116 uint32_t win_reg; 117 118 if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) { 119 ERROR("Disabling wrong CCU window %d!\n", win_id); 120 return; 121 } 122 123 win_reg = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 124 win_reg &= ~WIN_ENABLE_BIT; 125 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), win_reg); 126 } 127 128 /* Insert/Remove temporary window for using the out-of reset default 129 * CPx base address to access the CP configuration space prior to 130 * the further base address update in accordance with address mapping 131 * design. 132 * 133 * NOTE: Use the same window array for insertion and removal of 134 * temporary windows. 135 */ 136 void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size) 137 { 138 uint32_t win_id; 139 140 for (int i = 0; i < size; i++) { 141 win_id = MVEBU_CCU_MAX_WINS - 1 - i; 142 ccu_win_check(win); 143 ccu_enable_win(ap_index, win, win_id); 144 win++; 145 } 146 } 147 148 /* 149 * NOTE: Use the same window array for insertion and removal of 150 * temporary windows. 151 */ 152 void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size) 153 { 154 uint32_t win_id; 155 156 for (int i = 0; i < size; i++) { 157 uint64_t base; 158 uint32_t target; 159 160 win_id = MVEBU_CCU_MAX_WINS - 1 - i; 161 162 target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 163 target >>= CCU_TARGET_ID_OFFSET; 164 target &= CCU_TARGET_ID_MASK; 165 166 base = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, win_id)); 167 base <<= ADDRESS_SHIFT; 168 169 if ((win->target_id != target) || (win->base_addr != base)) { 170 ERROR("%s: Trying to remove bad window-%d!\n", 171 __func__, win_id); 172 continue; 173 } 174 ccu_disable_win(ap_index, win_id); 175 win++; 176 } 177 } 178 179 /* Returns current DRAM window target (DRAM_0_TID, DRAM_1_TID, RAR_TID) 180 * NOTE: Call only once for each AP. 181 * The AP0 DRAM window is located at index 2 only at the BL31 execution start. 182 * Then it relocated to index 1 for matching the rest of APs DRAM settings. 183 * Calling this function after relocation will produce wrong results on AP0 184 */ 185 static uint32_t ccu_dram_target_get(int ap_index) 186 { 187 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 188 * All the rest of detected APs will use window at index 1. 189 * The AP0 DRAM window is moved from index 2 to 1 during 190 * init_ccu() execution. 191 */ 192 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 193 uint32_t target; 194 195 target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 196 target >>= CCU_TARGET_ID_OFFSET; 197 target &= CCU_TARGET_ID_MASK; 198 199 return target; 200 } 201 202 void ccu_dram_target_set(int ap_index, uint32_t target) 203 { 204 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 205 * All the rest of detected APs will use window at index 1. 206 * The AP0 DRAM window is moved from index 2 to 1 207 * during init_ccu() execution. 208 */ 209 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 210 uint32_t dram_cr; 211 212 dram_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 213 dram_cr &= ~(CCU_TARGET_ID_MASK << CCU_TARGET_ID_OFFSET); 214 dram_cr |= (target & CCU_TARGET_ID_MASK) << CCU_TARGET_ID_OFFSET; 215 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), dram_cr); 216 } 217 218 /* Setup CCU DRAM window and enable it */ 219 void ccu_dram_win_config(int ap_index, struct addr_map_win *win) 220 { 221 #if IMAGE_BLE /* BLE */ 222 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 223 * Since the BootROM is not accessing DRAM at BLE stage, 224 * the DRAM window can be temporarely disabled. 225 */ 226 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 227 #else /* end of BLE */ 228 /* At the ccu_init() execution stage, DRAM windows of all APs 229 * are arranged at index 1. 230 * The AP0 still has the old window BootROM DRAM at index 2, so 231 * the window-1 can be safely disabled without breaking the DRAM access. 232 */ 233 const uint32_t win_id = 1; 234 #endif 235 236 ccu_disable_win(ap_index, win_id); 237 /* enable write secure (and clear read secure) */ 238 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), 239 CCU_WIN_ENA_WRITE_SECURE); 240 ccu_win_check(win); 241 ccu_enable_win(ap_index, win, win_id); 242 } 243 244 /* Save content of CCU window + GCR */ 245 static void ccu_save_win_range(int ap_id, int win_first, 246 int win_last, uint32_t *buffer) 247 { 248 int win_id, idx; 249 /* Save CCU */ 250 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { 251 buffer[idx++] = mmio_read_32(CCU_WIN_CR_OFFSET(ap_id, win_id)); 252 buffer[idx++] = mmio_read_32(CCU_WIN_SCR_OFFSET(ap_id, win_id)); 253 buffer[idx++] = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_id, win_id)); 254 buffer[idx++] = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_id, win_id)); 255 } 256 buffer[idx] = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_id)); 257 } 258 259 /* Restore content of CCU window + GCR */ 260 static void ccu_restore_win_range(int ap_id, int win_first, 261 int win_last, uint32_t *buffer) 262 { 263 int win_id, idx; 264 /* Restore CCU */ 265 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { 266 mmio_write_32(CCU_WIN_CR_OFFSET(ap_id, win_id), buffer[idx++]); 267 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_id, win_id), buffer[idx++]); 268 mmio_write_32(CCU_WIN_ALR_OFFSET(ap_id, win_id), buffer[idx++]); 269 mmio_write_32(CCU_WIN_AHR_OFFSET(ap_id, win_id), buffer[idx++]); 270 } 271 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_id), buffer[idx]); 272 } 273 274 void ccu_save_win_all(int ap_id) 275 { 276 ccu_save_win_range(ap_id, 0, MVEBU_CCU_MAX_WINS - 1, ccu_regs_save); 277 } 278 279 void ccu_restore_win_all(int ap_id) 280 { 281 ccu_restore_win_range(ap_id, 0, MVEBU_CCU_MAX_WINS - 1, ccu_regs_save); 282 } 283 284 int init_ccu(int ap_index) 285 { 286 struct addr_map_win *win, *dram_win; 287 uint32_t win_id, win_reg; 288 uint32_t win_count, array_id; 289 uint32_t dram_target; 290 #if IMAGE_BLE 291 /* In BootROM context CCU Window-1 292 * has SRAM_TID target and should not be disabled 293 */ 294 const uint32_t win_start = 2; 295 #else 296 const uint32_t win_start = 1; 297 #endif 298 299 INFO("Initializing CCU Address decoding\n"); 300 301 /* Get the array of the windows and fill the map data */ 302 marvell_get_ccu_memory_map(ap_index, &win, &win_count); 303 if (win_count <= 0) { 304 INFO("No windows configurations found\n"); 305 } else if (win_count > (MVEBU_CCU_MAX_WINS - 1)) { 306 ERROR("CCU mem map array > than max available windows (%d)\n", 307 MVEBU_CCU_MAX_WINS); 308 win_count = MVEBU_CCU_MAX_WINS; 309 } 310 311 /* Need to set GCR to DRAM before all CCU windows are disabled for 312 * securing the normal access to DRAM location, which the ATF is running 313 * from. Once all CCU windows are set, which have to include the 314 * dedicated DRAM window as well, the GCR can be switched to the target 315 * defined by the platform configuration. 316 */ 317 dram_target = ccu_dram_target_get(ap_index); 318 win_reg = (dram_target & CCU_GCR_TARGET_MASK) << CCU_GCR_TARGET_OFFSET; 319 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); 320 321 /* If the DRAM window was already configured at the BLE stage, 322 * only the window target considered valid, the address range should be 323 * updated according to the platform configuration. 324 */ 325 for (dram_win = win, array_id = 0; array_id < win_count; 326 array_id++, dram_win++) { 327 if (IS_DRAM_TARGET(dram_win->target_id)) { 328 dram_win->target_id = dram_target; 329 break; 330 } 331 } 332 333 /* Disable all AP CCU windows 334 * Window-0 is always bypassed since it already contains 335 * data allowing the internal configuration space access 336 */ 337 for (win_id = win_start; win_id < MVEBU_CCU_MAX_WINS; win_id++) { 338 ccu_disable_win(ap_index, win_id); 339 /* enable write secure (and clear read secure) */ 340 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), 341 CCU_WIN_ENA_WRITE_SECURE); 342 } 343 344 /* win_id is the index of the current ccu window 345 * array_id is the index of the current memory map window entry 346 */ 347 for (win_id = win_start, array_id = 0; 348 ((win_id < MVEBU_CCU_MAX_WINS) && (array_id < win_count)); 349 win_id++) { 350 ccu_win_check(win); 351 ccu_enable_win(ap_index, win, win_id); 352 win++; 353 array_id++; 354 } 355 356 /* Get & set the default target according to board topology */ 357 win_reg = (marvell_get_ccu_gcr_target(ap_index) & CCU_GCR_TARGET_MASK) 358 << CCU_GCR_TARGET_OFFSET; 359 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); 360 361 #ifdef DEBUG_ADDR_MAP 362 dump_ccu(ap_index); 363 #endif 364 365 INFO("Done CCU Address decoding Initializing\n"); 366 367 return 0; 368 } 369