1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 /* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */ 9 10 #include <inttypes.h> 11 #include <stdint.h> 12 13 #include <common/debug.h> 14 #include <drivers/marvell/ccu.h> 15 #include <lib/mmio.h> 16 17 #include <armada_common.h> 18 #include <mvebu.h> 19 #include <mvebu_def.h> 20 21 #if LOG_LEVEL >= LOG_LEVEL_INFO 22 #define DEBUG_ADDR_MAP 23 #endif 24 25 /* common defines */ 26 #define WIN_ENABLE_BIT (0x1) 27 /* Physical address of the base of the window = {AddrLow[19:0],20'h0} */ 28 #define ADDRESS_SHIFT (20 - 4) 29 #define ADDRESS_MASK (0xFFFFFFF0) 30 #define CCU_WIN_ALIGNMENT (0x100000) 31 32 /* 33 * Physical address of the highest address of window bits[31:19] = 0x6FF 34 * Physical address of the lowest address of window bits[18:6] = 0x6E0 35 * Unit Id bits [5:2] = 2 36 * RGF Window Enable bit[0] = 1 37 * 0x37f9b809 - 11011111111 0011011100000 0010 0 1 38 */ 39 #define ERRATA_WA_CCU_WIN4 0x37f9b809U 40 41 /* 42 * Physical address of the highest address of window bits[31:19] = 0xFFF 43 * Physical address of the lowest address of window bits[18:6] = 0x800 44 * Unit Id bits [5:2] = 2 45 * RGF Window Enable bit[0] = 1 46 * 0x7ffa0009 - 111111111111 0100000000000 0010 0 1 47 */ 48 #define ERRATA_WA_CCU_WIN5 0x7ffa0009U 49 50 /* 51 * Physical address of the highest address of window bits[31:19] = 0x1FFF 52 * Physical address of the lowest address of window bits[18:6] = 0x1000 53 * Unit Id bits [5:2] = 2 54 * RGF Window Enable bit[0] = 1 55 * 0xfffc000d - 1111111111111 1000000000000 0011 0 1 56 */ 57 #define ERRATA_WA_CCU_WIN6 0xfffc000dU 58 59 #define IS_DRAM_TARGET(tgt) ((((tgt) == DRAM_0_TID) || \ 60 ((tgt) == DRAM_1_TID) || \ 61 ((tgt) == RAR_TID)) ? 1 : 0) 62 63 #define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \ 64 0x90 + 4 * (win)) 65 66 /* For storage of CR, SCR, ALR, AHR abd GCR */ 67 static uint32_t ccu_regs_save[MVEBU_CCU_MAX_WINS * 4 + 1]; 68 69 #ifdef DEBUG_ADDR_MAP 70 static void dump_ccu(int ap_index) 71 { 72 uint32_t win_id, win_cr, alr, ahr; 73 uint8_t target_id; 74 uint64_t start, end; 75 76 /* Dump all AP windows */ 77 printf("\tbank target start end\n"); 78 printf("\t----------------------------------------------------\n"); 79 for (win_id = 0; win_id < MVEBU_CCU_MAX_WINS; win_id++) { 80 win_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 81 if (win_cr & WIN_ENABLE_BIT) { 82 target_id = (win_cr >> CCU_TARGET_ID_OFFSET) & 83 CCU_TARGET_ID_MASK; 84 alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, 85 win_id)); 86 ahr = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_index, 87 win_id)); 88 start = ((uint64_t)alr << ADDRESS_SHIFT); 89 end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT); 90 printf("\tccu%d %02x 0x%016" PRIx64 " 0x%016" PRIx64 "\n", 91 win_id, target_id, start, end); 92 } 93 } 94 win_cr = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_index)); 95 target_id = (win_cr >> CCU_GCR_TARGET_OFFSET) & CCU_GCR_TARGET_MASK; 96 printf("\tccu GCR %d - all other transactions\n", target_id); 97 } 98 #endif 99 100 void ccu_win_check(struct addr_map_win *win) 101 { 102 /* check if address is aligned to 1M */ 103 if (IS_NOT_ALIGN(win->base_addr, CCU_WIN_ALIGNMENT)) { 104 win->base_addr = ALIGN_UP(win->base_addr, CCU_WIN_ALIGNMENT); 105 NOTICE("%s: Align up the base address to 0x%" PRIx64 "\n", 106 __func__, win->base_addr); 107 } 108 109 /* size parameter validity check */ 110 if (IS_NOT_ALIGN(win->win_size, CCU_WIN_ALIGNMENT)) { 111 win->win_size = ALIGN_UP(win->win_size, CCU_WIN_ALIGNMENT); 112 NOTICE("%s: Aligning size to 0x%" PRIx64 "\n", 113 __func__, win->win_size); 114 } 115 } 116 117 int ccu_is_win_enabled(int ap_index, uint32_t win_id) 118 { 119 return mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)) & 120 WIN_ENABLE_BIT; 121 } 122 123 void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id) 124 { 125 uint32_t ccu_win_reg; 126 uint32_t alr, ahr; 127 uint64_t end_addr; 128 129 if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) { 130 ERROR("Enabling wrong CCU window %d!\n", win_id); 131 return; 132 } 133 134 end_addr = (win->base_addr + win->win_size - 1); 135 alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); 136 ahr = (uint32_t)((end_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); 137 138 mmio_write_32(CCU_WIN_ALR_OFFSET(ap_index, win_id), alr); 139 mmio_write_32(CCU_WIN_AHR_OFFSET(ap_index, win_id), ahr); 140 141 ccu_win_reg = WIN_ENABLE_BIT; 142 ccu_win_reg |= (win->target_id & CCU_TARGET_ID_MASK) 143 << CCU_TARGET_ID_OFFSET; 144 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), ccu_win_reg); 145 } 146 147 static void ccu_disable_win(int ap_index, uint32_t win_id) 148 { 149 uint32_t win_reg; 150 151 if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) { 152 ERROR("Disabling wrong CCU window %d!\n", win_id); 153 return; 154 } 155 156 win_reg = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 157 win_reg &= ~WIN_ENABLE_BIT; 158 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), win_reg); 159 } 160 161 /* Insert/Remove temporary window for using the out-of reset default 162 * CPx base address to access the CP configuration space prior to 163 * the further base address update in accordance with address mapping 164 * design. 165 * 166 * NOTE: Use the same window array for insertion and removal of 167 * temporary windows. 168 */ 169 void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size) 170 { 171 uint32_t win_id; 172 173 for (int i = 0; i < size; i++) { 174 win_id = MVEBU_CCU_MAX_WINS - 1 - i; 175 ccu_win_check(win); 176 ccu_enable_win(ap_index, win, win_id); 177 win++; 178 } 179 } 180 181 /* 182 * NOTE: Use the same window array for insertion and removal of 183 * temporary windows. 184 */ 185 void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size) 186 { 187 uint32_t win_id; 188 189 for (int i = 0; i < size; i++) { 190 uint64_t base; 191 uint32_t target; 192 193 win_id = MVEBU_CCU_MAX_WINS - 1 - i; 194 195 target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 196 target >>= CCU_TARGET_ID_OFFSET; 197 target &= CCU_TARGET_ID_MASK; 198 199 base = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, win_id)); 200 base <<= ADDRESS_SHIFT; 201 202 if ((win->target_id != target) || (win->base_addr != base)) { 203 ERROR("%s: Trying to remove bad window-%d!\n", 204 __func__, win_id); 205 continue; 206 } 207 ccu_disable_win(ap_index, win_id); 208 win++; 209 } 210 } 211 212 /* Returns current DRAM window target (DRAM_0_TID, DRAM_1_TID, RAR_TID) 213 * NOTE: Call only once for each AP. 214 * The AP0 DRAM window is located at index 2 only at the BL31 execution start. 215 * Then it relocated to index 1 for matching the rest of APs DRAM settings. 216 * Calling this function after relocation will produce wrong results on AP0 217 */ 218 static uint32_t ccu_dram_target_get(int ap_index) 219 { 220 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 221 * All the rest of detected APs will use window at index 1. 222 * The AP0 DRAM window is moved from index 2 to 1 during 223 * init_ccu() execution. 224 */ 225 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 226 uint32_t target; 227 228 target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 229 target >>= CCU_TARGET_ID_OFFSET; 230 target &= CCU_TARGET_ID_MASK; 231 232 return target; 233 } 234 235 void ccu_dram_target_set(int ap_index, uint32_t target) 236 { 237 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 238 * All the rest of detected APs will use window at index 1. 239 * The AP0 DRAM window is moved from index 2 to 1 240 * during init_ccu() execution. 241 */ 242 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 243 uint32_t dram_cr; 244 245 dram_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 246 dram_cr &= ~(CCU_TARGET_ID_MASK << CCU_TARGET_ID_OFFSET); 247 dram_cr |= (target & CCU_TARGET_ID_MASK) << CCU_TARGET_ID_OFFSET; 248 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), dram_cr); 249 } 250 251 /* Setup CCU DRAM window and enable it */ 252 void ccu_dram_win_config(int ap_index, struct addr_map_win *win) 253 { 254 #if IMAGE_BLE /* BLE */ 255 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 256 * Since the BootROM is not accessing DRAM at BLE stage, 257 * the DRAM window can be temporarely disabled. 258 */ 259 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 260 #else /* end of BLE */ 261 /* At the ccu_init() execution stage, DRAM windows of all APs 262 * are arranged at index 1. 263 * The AP0 still has the old window BootROM DRAM at index 2, so 264 * the window-1 can be safely disabled without breaking the DRAM access. 265 */ 266 const uint32_t win_id = 1; 267 #endif 268 269 ccu_disable_win(ap_index, win_id); 270 /* enable write secure (and clear read secure) */ 271 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), 272 CCU_WIN_ENA_WRITE_SECURE); 273 ccu_win_check(win); 274 ccu_enable_win(ap_index, win, win_id); 275 } 276 277 /* Save content of CCU window + GCR */ 278 static void ccu_save_win_range(int ap_id, int win_first, 279 int win_last, uint32_t *buffer) 280 { 281 int win_id, idx; 282 /* Save CCU */ 283 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { 284 buffer[idx++] = mmio_read_32(CCU_WIN_CR_OFFSET(ap_id, win_id)); 285 buffer[idx++] = mmio_read_32(CCU_WIN_SCR_OFFSET(ap_id, win_id)); 286 buffer[idx++] = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_id, win_id)); 287 buffer[idx++] = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_id, win_id)); 288 } 289 buffer[idx] = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_id)); 290 } 291 292 /* Restore content of CCU window + GCR */ 293 static void ccu_restore_win_range(int ap_id, int win_first, 294 int win_last, uint32_t *buffer) 295 { 296 int win_id, idx; 297 /* Restore CCU */ 298 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { 299 mmio_write_32(CCU_WIN_CR_OFFSET(ap_id, win_id), buffer[idx++]); 300 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_id, win_id), buffer[idx++]); 301 mmio_write_32(CCU_WIN_ALR_OFFSET(ap_id, win_id), buffer[idx++]); 302 mmio_write_32(CCU_WIN_AHR_OFFSET(ap_id, win_id), buffer[idx++]); 303 } 304 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_id), buffer[idx]); 305 } 306 307 void ccu_save_win_all(int ap_id) 308 { 309 ccu_save_win_range(ap_id, 0, MVEBU_CCU_MAX_WINS - 1, ccu_regs_save); 310 } 311 312 void ccu_restore_win_all(int ap_id) 313 { 314 ccu_restore_win_range(ap_id, 0, MVEBU_CCU_MAX_WINS - 1, ccu_regs_save); 315 } 316 317 int init_ccu(int ap_index) 318 { 319 struct addr_map_win *win, *dram_win; 320 uint32_t win_id, win_reg; 321 uint32_t win_count, array_id; 322 uint32_t dram_target; 323 #if IMAGE_BLE 324 /* In BootROM context CCU Window-1 325 * has SRAM_TID target and should not be disabled 326 */ 327 const uint32_t win_start = 2; 328 #else 329 const uint32_t win_start = 1; 330 #endif 331 332 INFO("Initializing CCU Address decoding\n"); 333 334 /* Get the array of the windows and fill the map data */ 335 marvell_get_ccu_memory_map(ap_index, &win, &win_count); 336 if (win_count <= 0) { 337 INFO("No windows configurations found\n"); 338 } else if (win_count > (MVEBU_CCU_MAX_WINS - 1)) { 339 ERROR("CCU mem map array > than max available windows (%d)\n", 340 MVEBU_CCU_MAX_WINS); 341 win_count = MVEBU_CCU_MAX_WINS; 342 } 343 344 /* Need to set GCR to DRAM before all CCU windows are disabled for 345 * securing the normal access to DRAM location, which the ATF is running 346 * from. Once all CCU windows are set, which have to include the 347 * dedicated DRAM window as well, the GCR can be switched to the target 348 * defined by the platform configuration. 349 */ 350 dram_target = ccu_dram_target_get(ap_index); 351 win_reg = (dram_target & CCU_GCR_TARGET_MASK) << CCU_GCR_TARGET_OFFSET; 352 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); 353 354 /* If the DRAM window was already configured at the BLE stage, 355 * only the window target considered valid, the address range should be 356 * updated according to the platform configuration. 357 */ 358 for (dram_win = win, array_id = 0; array_id < win_count; 359 array_id++, dram_win++) { 360 if (IS_DRAM_TARGET(dram_win->target_id)) { 361 dram_win->target_id = dram_target; 362 break; 363 } 364 } 365 366 /* Disable all AP CCU windows 367 * Window-0 is always bypassed since it already contains 368 * data allowing the internal configuration space access 369 */ 370 for (win_id = win_start; win_id < MVEBU_CCU_MAX_WINS; win_id++) { 371 ccu_disable_win(ap_index, win_id); 372 /* enable write secure (and clear read secure) */ 373 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), 374 CCU_WIN_ENA_WRITE_SECURE); 375 } 376 377 /* win_id is the index of the current ccu window 378 * array_id is the index of the current memory map window entry 379 */ 380 for (win_id = win_start, array_id = 0; 381 ((win_id < MVEBU_CCU_MAX_WINS) && (array_id < win_count)); 382 win_id++) { 383 ccu_win_check(win); 384 ccu_enable_win(ap_index, win, win_id); 385 win++; 386 array_id++; 387 } 388 389 /* Get & set the default target according to board topology */ 390 win_reg = (marvell_get_ccu_gcr_target(ap_index) & CCU_GCR_TARGET_MASK) 391 << CCU_GCR_TARGET_OFFSET; 392 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); 393 394 #ifdef DEBUG_ADDR_MAP 395 dump_ccu(ap_index); 396 #endif 397 398 INFO("Done CCU Address decoding Initializing\n"); 399 400 return 0; 401 } 402 403 void errata_wa_init(void) 404 { 405 /* 406 * EERATA ID: RES-3033912 - Internal Address Space Init state causes 407 * a hang upon accesses to [0xf070_0000, 0xf07f_ffff] 408 * Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to 409 * split [0x6e_0000, 0x1ff_ffff] to values [0x6e_0000, 0x6f_ffff] and 410 * [0x80_0000, 0xff_ffff] and [0x100_0000, 0x1ff_ffff],that cause 411 * accesses to the segment of [0xf070_0000, 0xf1ff_ffff] 412 * to act as RAZWI. 413 */ 414 mmio_write_32(CCU_RGF(4), ERRATA_WA_CCU_WIN4); 415 mmio_write_32(CCU_RGF(5), ERRATA_WA_CCU_WIN5); 416 mmio_write_32(CCU_RGF(6), ERRATA_WA_CCU_WIN6); 417 } 418