1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <drivers/delay_timer.h> 9 #include <drivers/marvell/aro.h> 10 #include <lib/mmio.h> 11 12 #include <a8k_plat_def.h> 13 14 /* Notify bootloader on DRAM setup */ 15 #define AP807_CPU_ARO_CTRL(cluster) \ 16 (MVEBU_RFU_BASE + 0x82A8 + (0xA58 * (cluster))) 17 18 /* 0 - ARO clock is enabled, 1 - ARO clock is disabled */ 19 #define AP807_CPU_ARO_CLK_EN_OFFSET 0 20 #define AP807_CPU_ARO_CLK_EN_MASK (0x1 << AP807_CPU_ARO_CLK_EN_OFFSET) 21 22 /* 0 - ARO is the clock source, 1 - PLL is the clock source */ 23 #define AP807_CPU_ARO_SEL_PLL_OFFSET 5 24 #define AP807_CPU_ARO_SEL_PLL_MASK (0x1 << AP807_CPU_ARO_SEL_PLL_OFFSET) 25 26 /* AP807 clusters count */ 27 #define AP807_CLUSTER_NUM 2 28 29 /* PLL frequency values */ 30 #define PLL_FREQ_1200 0x2AE5F002 /* 1200 */ 31 #define PLL_FREQ_2000 0x2FC9F002 /* 2000 */ 32 #define PLL_FREQ_2200 0x2AC57001 /* 2200 */ 33 #define PLL_FREQ_2400 0x2AE5F001 /* 2400 */ 34 35 /* CPU PLL control registers */ 36 #define AP807_CPU_PLL_CTRL(cluster) \ 37 (MVEBU_RFU_BASE + 0x82E0 + (0x8 * (cluster))) 38 39 #define AP807_CPU_PLL_PARAM(cluster) AP807_CPU_PLL_CTRL(cluster) 40 #define AP807_CPU_PLL_CFG(cluster) (AP807_CPU_PLL_CTRL(cluster) + 0x4) 41 #define AP807_CPU_PLL_CFG_BYPASS_MODE (0x1) 42 #define AP807_CPU_PLL_CFG_USE_REG_FILE (0x1 << 9) 43 44 static void pll_set_freq(unsigned int freq_val) 45 { 46 int i; 47 48 for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) { 49 mmio_write_32(AP807_CPU_PLL_CFG(i), 50 AP807_CPU_PLL_CFG_USE_REG_FILE); 51 mmio_write_32(AP807_CPU_PLL_CFG(i), 52 AP807_CPU_PLL_CFG_USE_REG_FILE | 53 AP807_CPU_PLL_CFG_BYPASS_MODE); 54 mmio_write_32(AP807_CPU_PLL_PARAM(i), freq_val); 55 mmio_write_32(AP807_CPU_PLL_CFG(i), 56 AP807_CPU_PLL_CFG_USE_REG_FILE); 57 } 58 } 59 60 /* Switch to ARO from PLL in ap807 */ 61 static void aro_to_pll(void) 62 { 63 unsigned int reg; 64 int i; 65 66 for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) { 67 /* switch from ARO to PLL */ 68 reg = mmio_read_32(AP807_CPU_ARO_CTRL(i)); 69 reg |= AP807_CPU_ARO_SEL_PLL_MASK; 70 mmio_write_32(AP807_CPU_ARO_CTRL(i), reg); 71 72 mdelay(100); 73 74 /* disable ARO clk driver */ 75 reg = mmio_read_32(AP807_CPU_ARO_CTRL(i)); 76 reg |= (AP807_CPU_ARO_CLK_EN_MASK); 77 mmio_write_32(AP807_CPU_ARO_CTRL(i), reg); 78 } 79 } 80 81 /* switch from ARO to PLL 82 * in case of default frequency option, configure PLL registers 83 * to be aligned with new default frequency. 84 */ 85 void ap807_clocks_init(unsigned int freq_option) 86 { 87 /* Switch from ARO to PLL */ 88 aro_to_pll(); 89 90 /* Modifications in frequency table: 91 * 0x0: 764x: change to 2000 MHz. 92 * 0x2: 744x change to 1800 MHz, 764x change to 2200/2400. 93 * 0x3: 3900/744x/764x change to 1200 MHz. 94 */ 95 switch (freq_option) { 96 case CPU_2000_DDR_1200_RCLK_1200: 97 pll_set_freq(PLL_FREQ_2000); 98 break; 99 default: 100 break; 101 } 102 } 103