1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright 2025 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 #include <string.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/debug.h> 15 #include <drivers/delay_timer.h> 16 #include <drivers/mmc.h> 17 #include <lib/mmio.h> 18 19 #include <imx_usdhc.h> 20 21 /* These masks represent the commands which involve a data transfer. */ 22 #define ADTC_MASK_SD (BIT_32(6U) | BIT_32(17U) | BIT_32(18U) |\ 23 BIT_32(24U) | BIT_32(25U)) 24 #define ADTC_MASK_ACMD (BIT_64(51U)) 25 26 static void imx_usdhc_initialize(void); 27 static int imx_usdhc_send_cmd(struct mmc_cmd *cmd); 28 static int imx_usdhc_set_ios(unsigned int clk, unsigned int width); 29 static int imx_usdhc_prepare(int lba, uintptr_t buf, size_t size); 30 static int imx_usdhc_read(int lba, uintptr_t buf, size_t size); 31 static int imx_usdhc_write(int lba, uintptr_t buf, size_t size); 32 33 static const struct mmc_ops imx_usdhc_ops = { 34 .init = imx_usdhc_initialize, 35 .send_cmd = imx_usdhc_send_cmd, 36 .set_ios = imx_usdhc_set_ios, 37 .prepare = imx_usdhc_prepare, 38 .read = imx_usdhc_read, 39 .write = imx_usdhc_write, 40 }; 41 42 static imx_usdhc_params_t imx_usdhc_params; 43 44 #define IMX7_MMC_SRC_CLK_RATE (200 * 1000 * 1000) 45 static void imx_usdhc_set_clk(int clk) 46 { 47 int div = 1; 48 int pre_div = 1; 49 unsigned int sdhc_clk = IMX7_MMC_SRC_CLK_RATE; 50 uintptr_t reg_base = imx_usdhc_params.reg_base; 51 52 assert(clk > 0); 53 54 while (sdhc_clk / (16 * pre_div) > clk && pre_div < 256) 55 pre_div *= 2; 56 57 while (sdhc_clk / div > clk && div < 16) 58 div++; 59 60 pre_div >>= 1; 61 div -= 1; 62 clk = (pre_div << 8) | (div << 4); 63 64 mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN); 65 mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk); 66 udelay(10000); 67 68 mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_PER_CLKEN | VENDSPEC_CARD_CLKEN); 69 } 70 71 static void imx_usdhc_initialize(void) 72 { 73 unsigned int timeout = 10000; 74 uintptr_t reg_base = imx_usdhc_params.reg_base; 75 76 assert((imx_usdhc_params.reg_base & MMC_BLOCK_MASK) == 0); 77 78 /* reset the controller */ 79 mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTA); 80 81 /* wait for reset done */ 82 while ((mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTA)) { 83 if (!timeout) 84 ERROR("IMX MMC reset timeout.\n"); 85 timeout--; 86 } 87 88 mmio_write_32(reg_base + MMCBOOT, 0); 89 mmio_write_32(reg_base + MIXCTRL, 0); 90 mmio_write_32(reg_base + CLKTUNECTRLSTS, 0); 91 92 mmio_write_32(reg_base + VENDSPEC, VENDSPEC_INIT); 93 mmio_write_32(reg_base + DLLCTRL, 0); 94 mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_IPG_CLKEN | VENDSPEC_PER_CLKEN); 95 96 /* Set the initial boot clock rate */ 97 imx_usdhc_set_clk(MMC_BOOT_CLK_RATE); 98 udelay(100); 99 100 /* Clear read/write ready status */ 101 mmio_clrbits32(reg_base + INTSTATEN, INTSTATEN_BRR | INTSTATEN_BWR); 102 103 /* configure as little endian */ 104 mmio_write_32(reg_base + PROTCTRL, PROTCTRL_LE); 105 106 /* Set timeout to the maximum value */ 107 mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_TIMEOUT_MASK, 108 SYSCTRL_TIMEOUT(15)); 109 110 /* set wartermark level as 16 for safe for MMC */ 111 mmio_clrsetbits32(reg_base + WATERMARKLEV, WMKLV_MASK, 16 | (16 << 16)); 112 } 113 114 #define FSL_CMD_RETRIES 1000 115 116 static bool is_data_transfer_cmd(const struct mmc_cmd *cmd) 117 { 118 uintptr_t reg_base = imx_usdhc_params.reg_base; 119 unsigned int cmd_idx = cmd->cmd_idx; 120 uint32_t xfer_type; 121 122 xfer_type = mmio_read_32(reg_base + XFERTYPE); 123 124 if (XFERTYPE_GET_CMD(xfer_type) == MMC_CMD(55)) { 125 return (ADTC_MASK_ACMD & BIT_64(cmd_idx)) != 0ULL; 126 } 127 128 if ((ADTC_MASK_SD & BIT_32(cmd->cmd_idx)) != 0U) { 129 return true; 130 } 131 132 return false; 133 } 134 135 static int get_xfr_type(const struct mmc_cmd *cmd, bool data, uint32_t *xfertype) 136 { 137 *xfertype = XFERTYPE_CMD(cmd->cmd_idx); 138 139 switch (cmd->resp_type) { 140 case MMC_RESPONSE_R2: 141 *xfertype |= XFERTYPE_RSPTYP_136; 142 *xfertype |= XFERTYPE_CCCEN; 143 break; 144 case MMC_RESPONSE_R4: 145 *xfertype |= XFERTYPE_RSPTYP_48; 146 break; 147 case MMC_RESPONSE_R6: 148 *xfertype |= XFERTYPE_RSPTYP_48; 149 *xfertype |= XFERTYPE_CICEN; 150 *xfertype |= XFERTYPE_CCCEN; 151 break; 152 case MMC_RESPONSE_R1B: 153 *xfertype |= XFERTYPE_RSPTYP_48_BUSY; 154 *xfertype |= XFERTYPE_CICEN; 155 *xfertype |= XFERTYPE_CCCEN; 156 break; 157 default: 158 ERROR("Invalid CMD response: %u\n", cmd->resp_type); 159 return -EINVAL; 160 } 161 162 if (data) { 163 *xfertype |= XFERTYPE_DPSEL; 164 } 165 166 return 0; 167 } 168 169 static int imx_usdhc_send_cmd(struct mmc_cmd *cmd) 170 { 171 uintptr_t reg_base = imx_usdhc_params.reg_base; 172 unsigned int state, flags = INTSTATEN_CC | INTSTATEN_CTOE; 173 unsigned int mixctl = 0, multiple = 0; 174 unsigned int cmd_retries = 0; 175 uint32_t xfertype; 176 bool data; 177 int err = 0; 178 179 assert(cmd); 180 181 data = is_data_transfer_cmd(cmd); 182 183 err = get_xfr_type(cmd, data, &xfertype); 184 if (err != 0) { 185 return err; 186 } 187 188 /* clear all irq status */ 189 mmio_write_32(reg_base + INTSTAT, 0xffffffff); 190 191 /* Wait for the bus to be idle */ 192 do { 193 state = mmio_read_32(reg_base + PSTATE); 194 } while (state & (PSTATE_CDIHB | PSTATE_CIHB)); 195 196 while (mmio_read_32(reg_base + PSTATE) & PSTATE_DLA) 197 ; 198 199 mmio_write_32(reg_base + INTSIGEN, 0); 200 udelay(1000); 201 202 switch (cmd->cmd_idx) { 203 case MMC_CMD(18): 204 multiple = 1; 205 /* for read op */ 206 /* fallthrough */ 207 case MMC_CMD(17): 208 case MMC_CMD(8): 209 mixctl |= MIXCTRL_DTDSEL; 210 break; 211 case MMC_CMD(25): 212 multiple = 1; 213 /* for data op flag */ 214 /* fallthrough */ 215 break; 216 default: 217 break; 218 } 219 220 if (multiple) { 221 mixctl |= MIXCTRL_MSBSEL; 222 mixctl |= MIXCTRL_BCEN; 223 } 224 225 if (data) { 226 mixctl |= MIXCTRL_DMAEN; 227 } 228 229 /* Send the command */ 230 mmio_write_32(reg_base + CMDARG, cmd->cmd_arg); 231 mmio_clrsetbits32(reg_base + MIXCTRL, MIXCTRL_DATMASK, mixctl); 232 mmio_write_32(reg_base + XFERTYPE, xfertype); 233 234 /* Wait for the command done */ 235 do { 236 state = mmio_read_32(reg_base + INTSTAT); 237 if (cmd_retries) 238 udelay(1); 239 } while ((!(state & flags)) && ++cmd_retries < FSL_CMD_RETRIES); 240 241 if ((state & (INTSTATEN_CTOE | CMD_ERR)) || cmd_retries == FSL_CMD_RETRIES) { 242 if (cmd_retries == FSL_CMD_RETRIES) 243 err = -ETIMEDOUT; 244 else 245 err = -EIO; 246 ERROR("imx_usdhc mmc cmd %d state 0x%x errno=%d\n", 247 cmd->cmd_idx, state, err); 248 goto out; 249 } 250 251 /* Copy the response to the response buffer */ 252 if (cmd->resp_type & MMC_RSP_136) { 253 unsigned int cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 254 255 cmdrsp3 = mmio_read_32(reg_base + CMDRSP3); 256 cmdrsp2 = mmio_read_32(reg_base + CMDRSP2); 257 cmdrsp1 = mmio_read_32(reg_base + CMDRSP1); 258 cmdrsp0 = mmio_read_32(reg_base + CMDRSP0); 259 cmd->resp_data[3] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 260 cmd->resp_data[2] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 261 cmd->resp_data[1] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 262 cmd->resp_data[0] = (cmdrsp0 << 8); 263 } else { 264 cmd->resp_data[0] = mmio_read_32(reg_base + CMDRSP0); 265 } 266 267 /* Wait until all of the blocks are transferred */ 268 if (data) { 269 flags = DATA_COMPLETE; 270 do { 271 state = mmio_read_32(reg_base + INTSTAT); 272 273 if (state & (INTSTATEN_DTOE | DATA_ERR)) { 274 err = -EIO; 275 ERROR("imx_usdhc mmc data state 0x%x\n", state); 276 goto out; 277 } 278 } while ((state & flags) != flags); 279 } 280 281 out: 282 /* Reset CMD and DATA on error */ 283 if (err) { 284 mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTC); 285 while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTC) 286 ; 287 288 if (data) { 289 mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTD); 290 while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTD) 291 ; 292 } 293 } 294 295 /* clear all irq status */ 296 mmio_write_32(reg_base + INTSTAT, 0xffffffff); 297 298 return err; 299 } 300 301 static int imx_usdhc_set_ios(unsigned int clk, unsigned int width) 302 { 303 uintptr_t reg_base = imx_usdhc_params.reg_base; 304 305 imx_usdhc_set_clk(clk); 306 307 if (width == MMC_BUS_WIDTH_4) 308 mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK, 309 PROTCTRL_WIDTH_4); 310 else if (width == MMC_BUS_WIDTH_8) 311 mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK, 312 PROTCTRL_WIDTH_8); 313 314 return 0; 315 } 316 317 static int imx_usdhc_prepare(int lba, uintptr_t buf, size_t size) 318 { 319 uintptr_t reg_base = imx_usdhc_params.reg_base; 320 321 mmio_write_32(reg_base + DSADDR, buf); 322 mmio_write_32(reg_base + BLKATT, 323 (size / MMC_BLOCK_SIZE) << 16 | MMC_BLOCK_SIZE); 324 325 return 0; 326 } 327 328 static int imx_usdhc_read(int lba, uintptr_t buf, size_t size) 329 { 330 return 0; 331 } 332 333 static int imx_usdhc_write(int lba, uintptr_t buf, size_t size) 334 { 335 return 0; 336 } 337 338 void imx_usdhc_init(imx_usdhc_params_t *params, 339 struct mmc_device_info *mmc_dev_info) 340 { 341 assert((params != 0) && 342 ((params->reg_base & MMC_BLOCK_MASK) == 0) && 343 ((params->bus_width == MMC_BUS_WIDTH_1) || 344 (params->bus_width == MMC_BUS_WIDTH_4) || 345 (params->bus_width == MMC_BUS_WIDTH_8))); 346 347 memcpy(&imx_usdhc_params, params, sizeof(imx_usdhc_params_t)); 348 mmc_init(&imx_usdhc_ops, params->clk_rate, params->bus_width, 349 params->flags, mmc_dev_info); 350 } 351