1*598cee48SBryan O'Donoghue /* 2*598cee48SBryan O'Donoghue * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved. 3*598cee48SBryan O'Donoghue * 4*598cee48SBryan O'Donoghue * SPDX-License-Identifier: BSD-3-Clause 5*598cee48SBryan O'Donoghue */ 6*598cee48SBryan O'Donoghue #ifndef __IMX_CONSOLE_H__ 7*598cee48SBryan O'Donoghue #define __IMX_CONSOLE_H__ 8*598cee48SBryan O'Donoghue 9*598cee48SBryan O'Donoghue #define IMX_UART_RXD_OFFSET 0x00 10*598cee48SBryan O'Donoghue #define IMX_UART_RXD_CHARRDY BIT(15) 11*598cee48SBryan O'Donoghue #define IMX_UART_RXD_ERR BIT(14) 12*598cee48SBryan O'Donoghue #define IMX_UART_RXD_OVERRUN BIT(13) 13*598cee48SBryan O'Donoghue #define IMX_UART_RXD_FRMERR BIT(12) 14*598cee48SBryan O'Donoghue #define IMX_UART_RXD_BRK BIT(11) 15*598cee48SBryan O'Donoghue #define IMX_UART_RXD_PRERR BIT(10) 16*598cee48SBryan O'Donoghue 17*598cee48SBryan O'Donoghue #define IMX_UART_TXD_OFFSET 0x40 18*598cee48SBryan O'Donoghue 19*598cee48SBryan O'Donoghue #define IMX_UART_CR1_OFFSET 0x80 20*598cee48SBryan O'Donoghue #define IMX_UART_CR1_ADEN BIT(15) 21*598cee48SBryan O'Donoghue #define IMX_UART_CR1_ADBR BIT(14) 22*598cee48SBryan O'Donoghue #define IMX_UART_CR1_TRDYEN BIT(13) 23*598cee48SBryan O'Donoghue #define IMX_UART_CR1_IDEN BIT(12) 24*598cee48SBryan O'Donoghue #define IMX_UART_CR1_RRDYEN BIT(9) 25*598cee48SBryan O'Donoghue #define IMX_UART_CR1_RXDMAEN BIT(8) 26*598cee48SBryan O'Donoghue #define IMX_UART_CR1_IREN BIT(7) 27*598cee48SBryan O'Donoghue #define IMX_UART_CR1_TXMPTYEN BIT(6) 28*598cee48SBryan O'Donoghue #define IMX_UART_CR1_RTSDEN BIT(5) 29*598cee48SBryan O'Donoghue #define IMX_UART_CR1_SNDBRK BIT(4) 30*598cee48SBryan O'Donoghue #define IMX_UART_CR1_TXDMAEN BIT(3) 31*598cee48SBryan O'Donoghue #define IMX_UART_CR1_ATDMAEN BIT(2) 32*598cee48SBryan O'Donoghue #define IMX_UART_CR1_DOZE BIT(1) 33*598cee48SBryan O'Donoghue #define IMX_UART_CR1_UARTEN BIT(0) 34*598cee48SBryan O'Donoghue 35*598cee48SBryan O'Donoghue #define IMX_UART_CR2_OFFSET 0x84 36*598cee48SBryan O'Donoghue #define IMX_UART_CR2_ESCI BIT(15) 37*598cee48SBryan O'Donoghue #define IMX_UART_CR2_IRTS BIT(14) 38*598cee48SBryan O'Donoghue #define IMX_UART_CR2_CTSC BIT(13) 39*598cee48SBryan O'Donoghue #define IMX_UART_CR2_CTS BIT(12) 40*598cee48SBryan O'Donoghue #define IMX_UART_CR2_ESCEN BIT(11) 41*598cee48SBryan O'Donoghue #define IMX_UART_CR2_PREN BIT(8) 42*598cee48SBryan O'Donoghue #define IMX_UART_CR2_PROE BIT(7) 43*598cee48SBryan O'Donoghue #define IMX_UART_CR2_STPB BIT(6) 44*598cee48SBryan O'Donoghue #define IMX_UART_CR2_WS BIT(5) 45*598cee48SBryan O'Donoghue #define IMX_UART_CR2_RTSEN BIT(4) 46*598cee48SBryan O'Donoghue #define IMX_UART_CR2_ATEN BIT(3) 47*598cee48SBryan O'Donoghue #define IMX_UART_CR2_TXEN BIT(2) 48*598cee48SBryan O'Donoghue #define IMX_UART_CR2_RXEN BIT(1) 49*598cee48SBryan O'Donoghue #define IMX_UART_CR2_SRST BIT(0) 50*598cee48SBryan O'Donoghue 51*598cee48SBryan O'Donoghue #define IMX_UART_CR3_OFFSET 0x88 52*598cee48SBryan O'Donoghue #define IMX_UART_CR3_DTREN BIT(13) 53*598cee48SBryan O'Donoghue #define IMX_UART_CR3_PARERREN BIT(12) 54*598cee48SBryan O'Donoghue #define IMX_UART_CR3_FARERREN BIT(11) 55*598cee48SBryan O'Donoghue #define IMX_UART_CR3_DSD BIT(10) 56*598cee48SBryan O'Donoghue #define IMX_UART_CR3_DCD BIT(9) 57*598cee48SBryan O'Donoghue #define IMX_UART_CR3_RI BIT(8) 58*598cee48SBryan O'Donoghue #define IMX_UART_CR3_ADNIMP BIT(7) 59*598cee48SBryan O'Donoghue #define IMX_UART_CR3_RXDSEN BIT(6) 60*598cee48SBryan O'Donoghue #define IMX_UART_CR3_AIRINTEN BIT(5) 61*598cee48SBryan O'Donoghue #define IMX_UART_CR3_AWAKEN BIT(4) 62*598cee48SBryan O'Donoghue #define IMX_UART_CR3_DTRDEN BIT(3) 63*598cee48SBryan O'Donoghue #define IMX_UART_CR3_RXDMUXSEL BIT(2) 64*598cee48SBryan O'Donoghue #define IMX_UART_CR3_INVT BIT(1) 65*598cee48SBryan O'Donoghue #define IMX_UART_CR3_ACIEN BIT(0) 66*598cee48SBryan O'Donoghue 67*598cee48SBryan O'Donoghue #define IMX_UART_CR4_OFFSET 0x8c 68*598cee48SBryan O'Donoghue #define IMX_UART_CR4_INVR BIT(9) 69*598cee48SBryan O'Donoghue #define IMX_UART_CR4_ENIRI BIT(8) 70*598cee48SBryan O'Donoghue #define IMX_UART_CR4_WKEN BIT(7) 71*598cee48SBryan O'Donoghue #define IMX_UART_CR4_IDDMAEN BIT(6) 72*598cee48SBryan O'Donoghue #define IMX_UART_CR4_IRSC BIT(5) 73*598cee48SBryan O'Donoghue #define IMX_UART_CR4_LPBYP BIT(4) 74*598cee48SBryan O'Donoghue #define IMX_UART_CR4_TCEN BIT(3) 75*598cee48SBryan O'Donoghue #define IMX_UART_CR4_BKEN BIT(2) 76*598cee48SBryan O'Donoghue #define IMX_UART_CR4_OREN BIT(1) 77*598cee48SBryan O'Donoghue #define IMX_UART_CR4_DREN BIT(0) 78*598cee48SBryan O'Donoghue 79*598cee48SBryan O'Donoghue #define IMX_UART_FCR_OFFSET 0x90 80*598cee48SBryan O'Donoghue #define IMX_UART_FCR_TXTL_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12) |\ 81*598cee48SBryan O'Donoghue BIT(11) | BIT(10)) 82*598cee48SBryan O'Donoghue #define IMX_UART_FCR_TXTL(x) ((x) << 10) 83*598cee48SBryan O'Donoghue #define IMX_UART_FCR_RFDIV_MASK (BIT(9) | BIT(8) | BIT(7)) 84*598cee48SBryan O'Donoghue #define IMX_UART_FCR_RFDIV7 (BIT(9) | BIT(8)) 85*598cee48SBryan O'Donoghue #define IMX_UART_FCR_RFDIV1 (BIT(9) | BIT(7)) 86*598cee48SBryan O'Donoghue #define IMX_UART_FCR_RFDIV2 BIT(9) 87*598cee48SBryan O'Donoghue #define IMX_UART_FCR_RFDIV3 (BIT(8) | BIT(7)) 88*598cee48SBryan O'Donoghue #define IMX_UART_FCR_RFDIV4 BIT(8) 89*598cee48SBryan O'Donoghue #define IMX_UART_FCR_RFDIV5 BIT(7) 90*598cee48SBryan O'Donoghue #define IMX_UART_FCR_RFDIV6 0 91*598cee48SBryan O'Donoghue #define IMX_UART_FCR_DCEDTE BIT(6) 92*598cee48SBryan O'Donoghue #define IMX_UART_FCR_RXTL_MASK (BIT(5) | BIT(4) | BIT(3) | BIT(2) |\ 93*598cee48SBryan O'Donoghue BIT(1) | BIT(0)) 94*598cee48SBryan O'Donoghue #define IMX_UART_FCR_RXTL(x) x 95*598cee48SBryan O'Donoghue 96*598cee48SBryan O'Donoghue #define IMX_UART_STAT1_OFFSET 0x94 97*598cee48SBryan O'Donoghue #define IMX_UART_STAT1_PARITYERR BIT(15) 98*598cee48SBryan O'Donoghue #define IMX_UART_STAT1_RTSS BIT(14) 99*598cee48SBryan O'Donoghue #define IMX_UART_STAT1_TRDY BIT(13) 100*598cee48SBryan O'Donoghue #define IMX_UART_STAT1_RTSD BIT(12) 101*598cee48SBryan O'Donoghue #define IMX_UART_STAT1_ESCF BIT(11) 102*598cee48SBryan O'Donoghue #define IMX_UART_STAT1_FRAMEERR BIT(10) 103*598cee48SBryan O'Donoghue #define IMX_UART_STAT1_RRDY BIT(9) 104*598cee48SBryan O'Donoghue #define IMX_UART_STAT1_AGTIM BIT(8) 105*598cee48SBryan O'Donoghue #define IMX_UART_STAT1_DTRD BIT(7) 106*598cee48SBryan O'Donoghue #define IMX_UART_STAT1_RXDS BIT(6) 107*598cee48SBryan O'Donoghue #define IMX_UART_STAT1_AIRINT BIT(5) 108*598cee48SBryan O'Donoghue #define IMX_UART_STAT1_AWAKE BIT(4) 109*598cee48SBryan O'Donoghue #define IMX_UART_STAT1_SAD BIT(3) 110*598cee48SBryan O'Donoghue 111*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_OFFSET 0x98 112*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_ADET BIT(15) 113*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_TXFE BIT(14) 114*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_DTRF BIT(13) 115*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_IDLE BIT(12) 116*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_ACST BIT(11) 117*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_RIDELT BIT(10) 118*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_RIIN BIT(9) 119*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_IRINT BIT(8) 120*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_WAKE BIT(7) 121*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_DCDDELT BIT(6) 122*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_DCDIN BIT(5) 123*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_RTSF BIT(4) 124*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_TXDC BIT(3) 125*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_BRCD BIT(2) 126*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_ORE BIT(1) 127*598cee48SBryan O'Donoghue #define IMX_UART_STAT2_RCR BIT(0) 128*598cee48SBryan O'Donoghue 129*598cee48SBryan O'Donoghue #define IMX_UART_ESC_OFFSET 0x9c 130*598cee48SBryan O'Donoghue 131*598cee48SBryan O'Donoghue #define IMX_UART_TIM_OFFSET 0xa0 132*598cee48SBryan O'Donoghue 133*598cee48SBryan O'Donoghue #define IMX_UART_BIR_OFFSET 0xa4 134*598cee48SBryan O'Donoghue 135*598cee48SBryan O'Donoghue #define IMX_UART_BMR_OFFSET 0xa8 136*598cee48SBryan O'Donoghue 137*598cee48SBryan O'Donoghue #define IMX_UART_BRC_OFFSET 0xac 138*598cee48SBryan O'Donoghue 139*598cee48SBryan O'Donoghue #define IMX_UART_ONEMS_OFFSET 0xb0 140*598cee48SBryan O'Donoghue 141*598cee48SBryan O'Donoghue #define IMX_UART_TS_OFFSET 0xb4 142*598cee48SBryan O'Donoghue #define IMX_UART_TS_FRCPERR BIT(13) 143*598cee48SBryan O'Donoghue #define IMX_UART_TS_LOOP BIT(12) 144*598cee48SBryan O'Donoghue #define IMX_UART_TS_DBGEN BIT(11) 145*598cee48SBryan O'Donoghue #define IMX_UART_TS_LOOPIR BIT(10) 146*598cee48SBryan O'Donoghue #define IMX_UART_TS_RXDBG BIT(9) 147*598cee48SBryan O'Donoghue #define IMX_UART_TS_TXEMPTY BIT(6) 148*598cee48SBryan O'Donoghue #define IMX_UART_TS_RXEMPTY BIT(5) 149*598cee48SBryan O'Donoghue #define IMX_UART_TS_TXFULL BIT(4) 150*598cee48SBryan O'Donoghue #define IMX_UART_TS_RXFULL BIT(3) 151*598cee48SBryan O'Donoghue #define IMX_UART_TS_SOFTRST BIT(0) 152*598cee48SBryan O'Donoghue 153*598cee48SBryan O'Donoghue #endif /* __IMX_UART_H__ */ 154