1 /* 2 * Copyright (c) 2016 - 2020, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <lib/mmio.h> 11 12 #include <platform_def.h> 13 14 #include "bcm_emmc.h" 15 #include "emmc_chal_types.h" 16 #include "emmc_chal_sd.h" 17 #include "emmc_pboot_hal_memory_drv.h" 18 19 extern void emmc_soft_reset(void); 20 21 #define SD_VDD_WINDOW_1_6_TO_1_7 0x00000010 // 1.6 V to 1.7 Volts 22 #define SD_VDD_WINDOW_1_7_TO_1_8 0x00000020 // 1.7 V to 1.8 Volts 23 #define SD_VDD_WINDOW_1_8_TO_1_9 0x00000040 // 1.8 V to 1.9 Volts 24 #define SD_VDD_WINDOW_1_9_TO_2_0 0x00000080 // 1.9 V to 2.0 Volts 25 #define SD_VDD_WINDOW_2_0_TO_2_1 0x00000100 // 2.0 V to 2.1 Volts 26 #define SD_VDD_WINDOW_2_1_TO_2_2 0x00000200 // 2.1 V to 2.2 Volts 27 #define SD_VDD_WINDOW_2_2_TO_2_3 0x00000400 // 2.2 V to 2.3 Volts 28 #define SD_VDD_WINDOW_2_3_TO_2_4 0x00000800 // 2.3 V to 2.4 Volts 29 #define SD_VDD_WINDOW_2_4_TO_2_5 0x00001000 // 2.4 V to 2.5 Volts 30 #define SD_VDD_WINDOW_2_5_TO_2_6 0x00002000 // 2.5 V to 2.6 Volts 31 #define SD_VDD_WINDOW_2_6_TO_2_7 0x00004000 // 2.6 V to 2.7 Volts 32 #define SD_VDD_WINDOW_2_7_TO_2_8 0x00008000 // 2.7 V to 2.8 Volts 33 #define SD_VDD_WINDOW_2_8_TO_2_9 0x00010000 // 2.8 V to 2.9 Volts 34 #define SD_VDD_WINDOW_2_9_TO_3_0 0x00020000 // 2.9 V to 3.0 Volts 35 #define SD_VDD_WINDOW_3_0_TO_3_1 0x00040000 // 3.0 V to 3.1 Volts 36 #define SD_VDD_WINDOW_3_1_TO_3_2 0x00080000 // 3.1 V to 3.2 Volts 37 #define SD_VDD_WINDOW_3_2_TO_3_3 0x00100000 // 3.2 V to 3.3 Volts 38 #define SD_VDD_WINDOW_3_3_TO_3_4 0x00200000 // 3.3 V to 3.4 Volts 39 #define SD_VDD_WINDOW_3_4_TO_3_5 0x00400000 // 3.4 V to 3.5 Volts 40 #define SD_VDD_WINDOW_3_5_TO_3_6 0x00800000 // 3.5 V to 3.6 Volts 41 42 #define SD_VDD_WINDOW_1_6_TO_2_6 (SD_VDD_WINDOW_1_6_TO_1_7 | \ 43 SD_VDD_WINDOW_1_7_TO_1_8 | \ 44 SD_VDD_WINDOW_1_8_TO_1_9 | \ 45 SD_VDD_WINDOW_1_9_TO_2_0 | \ 46 SD_VDD_WINDOW_2_0_TO_2_1 | \ 47 SD_VDD_WINDOW_2_1_TO_2_2 | \ 48 SD_VDD_WINDOW_2_2_TO_2_3 | \ 49 SD_VDD_WINDOW_2_3_TO_2_4 | \ 50 SD_VDD_WINDOW_2_4_TO_2_5 | \ 51 SD_VDD_WINDOW_2_5_TO_2_6) 52 53 #define SD_VDD_WINDOW_2_6_TO_3_2 (SD_VDD_WINDOW_2_6_TO_2_7 | \ 54 SD_VDD_WINDOW_2_7_TO_2_8 | \ 55 SD_VDD_WINDOW_2_8_TO_2_9 | \ 56 SD_VDD_WINDOW_2_9_TO_3_0 | \ 57 SD_VDD_WINDOW_3_0_TO_3_1 | \ 58 SD_VDD_WINDOW_3_1_TO_3_2) 59 60 #define SD_VDD_WINDOW_3_2_TO_3_6 (SD_VDD_WINDOW_3_2_TO_3_3 | \ 61 SD_VDD_WINDOW_3_3_TO_3_4 | \ 62 SD_VDD_WINDOW_3_4_TO_3_5 | \ 63 SD_VDD_WINDOW_3_5_TO_3_6) 64 65 66 static int32_t chal_sd_set_power(struct sd_dev *handle, 67 uint32_t voltage, uint32_t state); 68 69 static void chal_sd_set_dma_boundary(struct sd_dev *handle, uint32_t boundary); 70 71 static int32_t chal_sd_setup_handler(struct sd_dev *handle, 72 uint32_t sdBbase, uint32_t hostBase); 73 74 /* 75 * Configure host controller pwr settings, 76 * to match voltage requirements by SD Card 77 */ 78 static int32_t chal_sd_set_power(struct sd_dev *handle, 79 uint32_t voltage, uint32_t state) 80 { 81 int32_t rc, rval = SD_FAIL; 82 uint32_t time = 0; 83 84 if (handle == NULL) 85 return SD_INVALID_HANDLE; 86 87 mmio_clrsetbits_32(handle->ctrl.sdRegBaseAddr + 88 SD4_EMMC_TOP_CTRL_OFFSET, 89 (SD4_EMMC_TOP_CTRL_SDVSELVDD1_MASK | 90 SD4_EMMC_TOP_CTRL_SDPWR_MASK), 91 (voltage << 9)); 92 93 /* 94 * Long delay is required here in emulation. Without this, the initial 95 * commands sent to the eMMC card timeout. We don't know if this 96 * delay is necessary with silicon, leaving in for safety. 97 * It is observed that 403ms on emulation system and as per the clock 98 * calculations it is expected to complete with in 1ms on chip 99 */ 100 do { 101 rc = mmio_read_32(handle->ctrl.sdRegBaseAddr + 102 SD4_EMMC_TOP_INTR_OFFSET); 103 104 if ((rc & SD4_EMMC_TOP_INTR_CRDINS_MASK) == 105 SD4_EMMC_TOP_INTR_CRDINS_MASK) 106 break; 107 108 mdelay(1); 109 } while (time++ < EMMC_CARD_DETECT_TIMEOUT_MS); 110 111 if (time >= EMMC_CARD_DETECT_TIMEOUT_MS) { 112 ERROR("EMMC: Card insert event detection timeout\n"); 113 return rval; 114 } 115 116 VERBOSE("EMMC: Card detection delay: %dms\n", time); 117 118 if (state) 119 mmio_setbits_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL_OFFSET, 120 SD4_EMMC_TOP_CTRL_SDPWR_MASK); 121 122 /* dummy write & ack to verify if the sdio is ready to send commands */ 123 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_ARG_OFFSET, 0); 124 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CMD_OFFSET, 0); 125 126 /* 127 * 63ms observed on emulation system, As per clock calculations 128 * it will complete < 1ms on chip. 129 */ 130 time = 0; 131 do { 132 rc = mmio_read_32(handle->ctrl.sdRegBaseAddr + 133 SD4_EMMC_TOP_INTR_OFFSET); 134 135 if (rc & SD4_EMMC_TOP_INTR_ERRIRQ_MASK) 136 break; 137 138 if ((rc & SD4_EMMC_TOP_INTR_CMDDONE_MASK) == 139 SD4_EMMC_TOP_INTR_CMDDONE_MASK) 140 break; 141 142 mdelay(1); 143 } while (time++ < EMMC_CMD_TIMEOUT_MS); 144 145 if (time >= EMMC_CMD_TIMEOUT_MS) { 146 WARN("%s %d Initial dummy command timeout is happened\n", 147 __func__, __LINE__); 148 return rval; 149 } 150 151 VERBOSE("EMMC: Dummy Command delay: %dms\n", time); 152 153 return SD_OK; 154 } 155 156 /* 157 * Configure DMA Boundaries 158 */ 159 static void chal_sd_set_dma_boundary(struct sd_dev *handle, uint32_t boundary) 160 { 161 if (handle == NULL) 162 return; 163 164 mmio_clrsetbits_32(handle->ctrl.sdRegBaseAddr + 165 SD4_EMMC_TOP_BLOCK_OFFSET, 166 SD4_EMMC_TOP_BLOCK_HSBS_MASK, boundary); 167 } 168 169 static int32_t chal_sd_setup_handler(struct sd_dev *handle, uint32_t sdBase, 170 uint32_t hostBase) 171 { 172 if (handle == NULL) 173 return SD_INVALID_HANDLE; 174 175 handle->ctrl.sdRegBaseAddr = sdBase; 176 handle->ctrl.hostRegBaseAddr = hostBase; 177 handle->ctrl.present = 0; 178 handle->ctrl.rca = 0; 179 handle->ctrl.blkGapEnable = 0; 180 handle->ctrl.cmdStatus = 0; 181 182 return SD_OK; 183 } 184 185 /* 186 * Initialize SD Host controller 187 */ 188 int32_t chal_sd_init(CHAL_HANDLE *sd_handle) 189 { 190 uint32_t cap_val_l = 0; 191 uint32_t ctl_val, voltage; 192 uint32_t timeout_val; 193 struct sd_dev *handle; 194 uint32_t reg_val; 195 int32_t rval = SD_FAIL; 196 197 if (sd_handle == NULL) 198 return SD_INVALID_HANDLE; 199 200 handle = (struct sd_dev *)sd_handle; 201 202 /* 203 * Set SDIO Host Controller capabilities register 204 */ 205 EMMC_TRACE("Set Host Controller Capabilities register\n"); 206 207 reg_val = 0; 208 reg_val |= (1 << ICFG_SDIO0_CAP0__SLOT_TYPE_R); 209 reg_val |= (0 << ICFG_SDIO0_CAP0__INT_MODE_R); 210 reg_val |= (0 << ICFG_SDIO0_CAP0__SYS_BUS_64BIT_R); 211 reg_val |= (1 << ICFG_SDIO0_CAP0__VOLTAGE_1P8V_R); 212 reg_val |= (1 << ICFG_SDIO0_CAP0__VOLTAGE_3P0V_R); 213 reg_val |= (1 << ICFG_SDIO0_CAP0__VOLTAGE_3P3V_R); 214 reg_val |= (1 << ICFG_SDIO0_CAP0__SUSPEND_RESUME_R); 215 reg_val |= (1 << ICFG_SDIO0_CAP0__SDMA_R); 216 reg_val |= (1 << ICFG_SDIO0_CAP0__HIGH_SPEED_R); 217 reg_val |= (1 << ICFG_SDIO0_CAP0__ADMA2_R); 218 reg_val |= (1 << ICFG_SDIO0_CAP0__EXTENDED_MEDIA_R); 219 reg_val |= (2 << ICFG_SDIO0_CAP0__MAX_BLOCK_LEN_R); 220 reg_val |= (0xd0 << ICFG_SDIO0_CAP0__BASE_CLK_FREQ_R); 221 reg_val |= (1 << ICFG_SDIO0_CAP0__TIMEOUT_UNIT_R); 222 reg_val |= (0x30 << ICFG_SDIO0_CAP0__TIMEOUT_CLK_FREQ_R); 223 224 mmio_write_32(ICFG_SDIO0_CAP0, reg_val); 225 226 reg_val = 0; 227 reg_val |= (1 << ICFG_SDIO0_CAP1__SPI_BLOCK_MODE_R); 228 reg_val |= (1 << ICFG_SDIO0_CAP1__SPI_MODE_R); 229 reg_val |= (0 << ICFG_SDIO0_CAP1__CLK_MULT_R); 230 reg_val |= (0 << ICFG_SDIO0_CAP1__RETUNING_MODE_R); 231 reg_val |= (1 << ICFG_SDIO0_CAP1__TUNE_SDR50_R); 232 reg_val |= (1 << ICFG_SDIO0_CAP1__TIME_RETUNE_R); 233 reg_val |= (1 << ICFG_SDIO0_CAP1__DRIVER_D_R); 234 reg_val |= (1 << ICFG_SDIO0_CAP1__DRIVER_C_R); 235 reg_val |= (1 << ICFG_SDIO0_CAP1__DRIVER_A_R); 236 reg_val |= (1 << ICFG_SDIO0_CAP1__DDR50_R); 237 reg_val |= (1 << ICFG_SDIO0_CAP1__SDR104_R); 238 reg_val |= (1 << ICFG_SDIO0_CAP1__SDR50_R); 239 240 mmio_write_32(ICFG_SDIO0_CAP1, reg_val); 241 242 /* Reset the SDIO controller */ 243 chal_sd_stop(); 244 245 /* Turn on SD clock */ 246 chal_sd_set_clock(sd_handle, 247 chal_sd_freq_2_div_ctrl_setting(INIT_CLK_FREQ), 1); 248 249 /* program data time out value to the max */ 250 timeout_val = SD_HOST_CORE_TIMEOUT; 251 252 ctl_val = mmio_read_32(handle->ctrl.sdRegBaseAddr + 253 SD4_EMMC_TOP_CTRL1_OFFSET); 254 ctl_val |= ((timeout_val & 0xf) << SD4_EMMC_TOP_CTRL1_DTCNT_SHIFT); 255 256 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET, 257 ctl_val); 258 259 /* enable all interrupt status */ 260 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN1_OFFSET, 261 0); 262 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN2_OFFSET, 263 0); 264 265 SD_US_DELAY(100); 266 267 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN1_OFFSET, 268 SD_NOR_INTERRUPTS | SD_ERR_INTERRUPTS); 269 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN2_OFFSET, 270 SD_NOR_INTERRUPTS | SD_ERR_INTERRUPTS); 271 272 /* Select SD bus voltage */ 273 cap_val_l = mmio_read_32(handle->ctrl.sdRegBaseAddr + 274 SD4_EMMC_TOP_CAPABILITIES1_OFFSET); 275 handle->cfg.voltage = 0; 276 voltage = 0x7; 277 278 if (cap_val_l & SD4_EMMC_TOP_CAPABILITIES1_V33_MASK) { 279 handle->cfg.voltage |= SD_VDD_WINDOW_3_3_TO_3_4; 280 voltage = 0x7; 281 } else if (cap_val_l & SD4_EMMC_TOP_CAPABILITIES1_V3_MASK) { 282 handle->cfg.voltage |= SD_VDD_WINDOW_3_0_TO_3_1; 283 voltage = 0x6; 284 } else if (cap_val_l & SD4_EMMC_TOP_CAPABILITIES1_V18_MASK) { 285 handle->cfg.voltage |= SD_VDD_WINDOW_1_8_TO_1_9; 286 voltage = 0x5; 287 } 288 289 rval = chal_sd_set_power(handle, voltage, SD4_EMMC_TOP_CTRL_SDPWR_MASK); 290 291 ctl_val = mmio_read_32(handle->ctrl.sdRegBaseAddr + 292 SD4_EMMC_TOP_HCVERSIRQ_OFFSET); 293 handle->ctrl.version = ((ctl_val >> 16) & 0xFF); 294 295 return rval; 296 } 297 298 void chal_sd_set_speed(CHAL_HANDLE *sd_handle, uint32_t speed) 299 { 300 struct sd_dev *handle; 301 302 if (sd_handle == NULL) 303 return; 304 305 handle = (struct sd_dev *) sd_handle; 306 307 if (speed) { 308 EMMC_TRACE("enable HighSpeed\n"); 309 mmio_setbits_32(handle->ctrl.sdRegBaseAddr + 310 SD4_EMMC_TOP_CTRL_OFFSET, 311 SD4_EMMC_TOP_CTRL_HSEN_MASK); 312 } else { 313 EMMC_TRACE("disable HighSpeed\n"); 314 mmio_clrbits_32(handle->ctrl.sdRegBaseAddr + 315 SD4_EMMC_TOP_CTRL_OFFSET, 316 SD4_EMMC_TOP_CTRL_HSEN_MASK); 317 } 318 } 319 320 int32_t chal_sd_stop(void) 321 { 322 uintptr_t idm_rst_ctrl_addr = EMMC_IDM_RESET_CTRL_ADDR; 323 324 /* Configure IO pins */ 325 emmc_soft_reset(); 326 327 /* Reset the SDIO controller */ 328 mmio_write_32(idm_rst_ctrl_addr, 1); 329 SD_US_DELAY(100); 330 mmio_write_32(idm_rst_ctrl_addr, 0); 331 SD_US_DELAY(100); 332 333 return SD_OK; 334 } 335 336 /* 337 * Check if host supports specified capability 338 * returns -ve val on error, 0 if capability not supported else 1. 339 */ 340 int32_t chal_sd_check_cap(CHAL_HANDLE *sd_handle, uint32_t caps) 341 { 342 struct sd_dev *handle; 343 344 if (sd_handle == NULL) 345 return SD_INVALID_HANDLE; 346 347 handle = (struct sd_dev *) sd_handle; 348 349 if (caps & mmio_read_32(handle->ctrl.sdRegBaseAddr + 350 SD4_EMMC_TOP_CAPABILITIES1_OFFSET)) 351 return 1; 352 else 353 return 0; 354 } 355 356 int32_t chal_sd_start(CHAL_HANDLE *sd_handle, 357 uint32_t mode, uint32_t sd_base, uint32_t host_base) 358 { 359 360 struct sd_dev *handle; 361 int32_t rval = SD_FAIL; 362 363 if (sd_handle == NULL) 364 return SD_INVALID_HANDLE; 365 366 handle = (struct sd_dev *) sd_handle; 367 368 handle->cfg.mode = SD_PIO_MODE; /* set to PIO mode first for init */ 369 handle->cfg.dma = SD_DMA_OFF; 370 371 chal_sd_setup_handler(handle, sd_base, host_base); 372 373 /* init and start hw */ 374 rval = chal_sd_init(sd_handle); 375 if (rval != SD_OK) 376 return rval; 377 378 chal_sd_clear_pending_irq(sd_handle); 379 380 handle->ctrl.eventList = 0; 381 handle->cfg.mode = mode; 382 383 return SD_OK; 384 } 385 386 /* 387 * Function to check 8bits of err generated from auto CMD12 388 */ 389 int32_t chal_sd_get_atuo12_error(CHAL_HANDLE *sd_handle) 390 { 391 struct sd_dev *handle; 392 393 if (sd_handle == NULL) 394 return SD_INVALID_HANDLE; 395 396 handle = (struct sd_dev *) sd_handle; 397 398 return (mmio_read_32(handle->ctrl.sdRegBaseAddr + 399 SD4_EMMC_TOP_ERRSTAT_OFFSET) & 0xFF); 400 } 401 402 /* 403 * Read present state register 404 */ 405 uint32_t chal_sd_get_present_status(CHAL_HANDLE *sd_handle) 406 { 407 struct sd_dev *handle; 408 409 if (sd_handle == NULL) 410 return SD_INVALID_HANDLE; 411 412 handle = (struct sd_dev *) sd_handle; 413 414 return mmio_read_32(handle->ctrl.sdRegBaseAddr + 415 SD4_EMMC_TOP_PSTATE_OFFSET); 416 } 417 418 /* 419 * Set SD bus width 420 */ 421 int32_t chal_sd_config_bus_width(CHAL_HANDLE *sd_handle, int32_t width) 422 { 423 uint32_t ctl_val; 424 struct sd_dev *handle; 425 426 if (sd_handle == NULL) 427 return SD_INVALID_HANDLE; 428 429 handle = (struct sd_dev *)sd_handle; 430 431 ctl_val = mmio_read_32(handle->ctrl.sdRegBaseAddr + 432 SD4_EMMC_TOP_CTRL_OFFSET); 433 434 switch (width) { 435 #ifdef DRIVER_EMMC_ENABLE_DATA_WIDTH_8BIT 436 case SD_BUS_DATA_WIDTH_8BIT: 437 ctl_val &= ~SD_BUS_DATA_WIDTH_4BIT; 438 ctl_val |= SD_BUS_DATA_WIDTH_8BIT; 439 break; 440 #endif 441 case SD_BUS_DATA_WIDTH_4BIT: 442 ctl_val &= ~SD_BUS_DATA_WIDTH_8BIT; 443 ctl_val |= SD_BUS_DATA_WIDTH_4BIT; 444 break; 445 case SD_BUS_DATA_WIDTH_1BIT: 446 ctl_val &= ~(SD_BUS_DATA_WIDTH_4BIT | SD_BUS_DATA_WIDTH_8BIT); 447 break; 448 default: 449 return SD_INV_DATA_WIDTH; 450 }; 451 452 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL_OFFSET, 453 ctl_val); 454 455 return SD_OK; 456 } 457 458 /* 459 * Function to enable or disable DMA control. 460 */ 461 int32_t chal_sd_set_dma(CHAL_HANDLE *sd_handle, uint32_t mode) 462 { 463 uint32_t val; 464 struct sd_dev *handle; 465 int32_t rc; 466 467 if (sd_handle == NULL) 468 return SD_INVALID_HANDLE; 469 470 handle = (struct sd_dev *)sd_handle; 471 472 if (mode) { 473 rc = chal_sd_check_cap(sd_handle, 474 SD4_EMMC_TOP_CAPABILITIES1_SDMA_MASK | 475 SD4_EMMC_TOP_CAPABILITIES1_ADMA2_MASK); 476 if (rc < 0) 477 return rc; 478 479 if (rc) { 480 481 handle->cfg.dma = mode; 482 val = mmio_read_32(handle->ctrl.sdRegBaseAddr + 483 SD4_EMMC_TOP_CTRL_OFFSET); 484 val &= ~(SD4_EMMC_TOP_CTRL_DMASEL_MASK); 485 val |= handle->cfg.dma - 1; 486 mmio_write_32(handle->ctrl.sdRegBaseAddr + 487 SD4_EMMC_TOP_CTRL_OFFSET, val); 488 return SD_OK; 489 } 490 } 491 handle->cfg.dma = 0; 492 493 return SD_FAIL; 494 } 495 496 /* 497 * Get current DMA address. 498 * Called only when there is no data transaction activity. 499 */ 500 uintptr_t chal_sd_get_dma_addr(CHAL_HANDLE *sd_handle) 501 { 502 struct sd_dev *handle; 503 504 if (sd_handle == NULL) 505 return SD_INVALID_HANDLE; 506 507 handle = (struct sd_dev *) sd_handle; 508 509 if (handle->cfg.dma == SD_DMA_OFF) 510 return 0; 511 512 return (uintptr_t)mmio_read_32(handle->ctrl.sdRegBaseAddr + 513 SD4_EMMC_TOP_SYSADDR_OFFSET); 514 } 515 516 int32_t chal_sd_send_cmd(CHAL_HANDLE *sd_handle, uint32_t cmd_idx, 517 uint32_t argument, uint32_t options) 518 { 519 uint32_t cmd_mode_reg = 0; 520 struct sd_dev *handle; 521 522 if (sd_handle == NULL) 523 return SD_INVALID_HANDLE; 524 525 handle = (struct sd_dev *) sd_handle; 526 527 EMMC_TRACE("%s %d cmd:%d argReg:%x options:%x\n", 528 __func__, __LINE__, cmd_idx, argument, options); 529 530 /* Configure the value for command and mode registers */ 531 cmd_mode_reg = (cmd_idx << 24) | options; 532 533 /* 534 * 1. Write block size reg & block count reg, 535 * this is done in the tx or rx setup 536 */ 537 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_BLOCK_OFFSET, 538 handle->ctrl.blkReg); 539 540 /* 2. Write argument reg */ 541 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_ARG_OFFSET, 542 argument); 543 handle->ctrl.argReg = argument; 544 545 /* 546 * 3. Write transfer mode reg & command reg, check the DMA bit which is 547 * set before this function call if it is selected. 548 */ 549 if (cmd_idx == 24 || cmd_idx == 25 || cmd_idx == 18 || cmd_idx == 17 || 550 cmd_idx == 42 || cmd_idx == 51 || cmd_idx == 53) 551 cmd_mode_reg |= ((handle->cfg.dma) ? 1 : 0); 552 553 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CMD_OFFSET, 554 cmd_mode_reg); 555 556 handle->ctrl.cmdIndex = cmd_idx; 557 558 return SD_OK; 559 } 560 561 int32_t chal_sd_set_dma_addr(CHAL_HANDLE *sd_handle, uintptr_t address) 562 { 563 struct sd_dev *handle; 564 565 if (sd_handle == NULL) 566 return SD_INVALID_HANDLE; 567 568 handle = (struct sd_dev *) sd_handle; 569 570 if (handle->cfg.dma == SD_DMA_OFF) 571 return SD_FAIL; 572 573 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_SYSADDR_OFFSET, 574 address); 575 return SD_OK; 576 } 577 578 uint32_t chal_sd_freq_2_div_ctrl_setting(uint32_t desired_freq) 579 { 580 /* 581 * Divider control setting represents 1/2 of the actual divider value. 582 * 583 * DesiredFreq = BaseClockFreq / (2 * div_ctrl_setting) 584 * 585 * ==> div_ctrl_setting = BaseClockFreq / (2 * DesiredFreq) 586 */ 587 uint32_t div_ctrl_setting; 588 uint32_t actual_freq; 589 590 assert(desired_freq != 0); 591 592 /* Special case, 0 = divider of 1. */ 593 if (desired_freq >= BASE_CLK_FREQ) 594 return 0; 595 596 /* Normal case, desired_freq < BASE_CLK_FREQ */ 597 div_ctrl_setting = BASE_CLK_FREQ / (2 * desired_freq); 598 599 actual_freq = BASE_CLK_FREQ / (2 * div_ctrl_setting); 600 601 if (actual_freq > desired_freq) { 602 /* 603 * Division does not result in exact frequency match. 604 * Make sure resulting frequency does not exceed requested freq. 605 */ 606 div_ctrl_setting++; 607 } 608 609 return div_ctrl_setting; 610 } 611 612 int32_t chal_sd_set_clock(CHAL_HANDLE *sd_handle, uint32_t div_ctrl_setting, 613 uint32_t on) 614 { 615 uint32_t value; 616 struct sd_dev *handle; 617 uint32_t time; 618 uint32_t clk_sel_high_byte = 0xFF & (div_ctrl_setting >> 8); 619 uint32_t clk_sel_low_byte = 0xFF & div_ctrl_setting; 620 621 if (sd_handle == NULL) 622 return SD_INVALID_HANDLE; 623 624 EMMC_TRACE("set_clock(div_ctrl_setting=%d,on=%d)\n", 625 div_ctrl_setting, on); 626 627 handle = (struct sd_dev *) sd_handle; 628 629 /* Read control register content. */ 630 value = mmio_read_32(handle->ctrl.sdRegBaseAddr + 631 SD4_EMMC_TOP_CTRL1_OFFSET); 632 633 /* Disable Clock */ 634 value &= ~(SD4_EMMC_TOP_CTRL1_SDCLKEN_MASK); 635 636 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET, 637 value); 638 639 /* Clear bits of interest. */ 640 value &= ~(SD4_EMMC_TOP_CTRL1_SDCLKSEL_MASK | 641 SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_MASK); 642 643 /* Set bits of interest to new value. */ 644 value |= (SD4_EMMC_TOP_CTRL1_SDCLKSEL_MASK & 645 (clk_sel_low_byte << SD4_EMMC_TOP_CTRL1_SDCLKSEL_SHIFT)); 646 value |= (SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_MASK & 647 (clk_sel_high_byte << SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_SHIFT)); 648 value |= SD4_EMMC_TOP_CTRL1_ICLKEN_MASK; 649 650 /* Write updated value back to control register. */ 651 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET, 652 value); 653 654 time = 0; 655 do { 656 value = mmio_read_32(handle->ctrl.sdRegBaseAddr + 657 SD4_EMMC_TOP_CTRL1_OFFSET); 658 659 if ((value & SD4_EMMC_TOP_CTRL1_ICLKSTB_MASK) == 660 SD4_EMMC_TOP_CTRL1_ICLKSTB_MASK) 661 break; 662 663 mdelay(1); 664 } while (time++ < EMMC_CLOCK_SETTING_TIMEOUT_MS); 665 666 if (time >= EMMC_CLOCK_SETTING_TIMEOUT_MS) 667 WARN("%s %d clock settings timeout happenedi (%dms)\n", 668 __func__, __LINE__, time); 669 670 VERBOSE("EMMC: clock settings delay: %dms\n", time); 671 672 value = mmio_read_32(handle->ctrl.sdRegBaseAddr + 673 SD4_EMMC_TOP_CTRL1_OFFSET); 674 675 if (on) 676 value |= SD4_EMMC_TOP_CTRL1_SDCLKEN_MASK; 677 678 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET, 679 value); 680 681 return SD_OK; 682 } 683 684 /* 685 * function to setup DMA buffer and data length, calculates block 686 * size and the number of blocks to be transferred and return 687 * the DMA buffer address. 688 */ 689 int32_t chal_sd_setup_xfer(CHAL_HANDLE *sd_handle, 690 uint8_t *data, uint32_t length, int32_t dir) 691 { 692 uint32_t blocks = 0; 693 struct sd_dev *handle; 694 695 if (sd_handle == NULL) 696 return SD_INVALID_HANDLE; 697 698 handle = (struct sd_dev *) sd_handle; 699 700 if (length <= handle->cfg.blockSize) { 701 handle->ctrl.blkReg = length | handle->cfg.dmaBoundary; 702 } else { 703 blocks = length / handle->cfg.blockSize; 704 handle->ctrl.blkReg = (blocks << 16) | handle->cfg.blockSize | 705 handle->cfg.dmaBoundary; 706 } 707 708 if (handle->cfg.dma != SD_DMA_OFF) { 709 /* For DMA target address setting, physical address should be used */ 710 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_SYSADDR_OFFSET, 711 (uintptr_t)data); 712 } 713 714 return SD_OK; 715 } 716 717 #ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE 718 /* 719 * function to write one block data directly to the 720 * host controller's FIFO which is 1K uint8_t or 721 * 2K uint8_t in size. 722 * It is used in Non-DMA mode for data transmission. 723 */ 724 int32_t chal_sd_write_buffer(CHAL_HANDLE *sd_handle, uint32_t length, 725 uint8_t *data) 726 { 727 uint32_t i, leftOver = 0, blockSize, size, value = 0; 728 struct sd_dev *handle; 729 730 if (sd_handle == NULL) 731 return SD_INVALID_HANDLE; 732 733 handle = (struct sd_dev *) sd_handle; 734 735 blockSize = handle->cfg.blockSize; 736 737 if (length == 0) 738 return SD_OK; 739 740 /* PIO mode, push into fifo word by word */ 741 if (length >= blockSize) { 742 size = blockSize; 743 } else { 744 size = ((length >> 2) << 2); 745 leftOver = length % 4; 746 } 747 748 for (i = 0; i < size; i += 4) { 749 value = *(uint32_t *)(data + i); 750 mmio_write_32(handle->ctrl.sdRegBaseAddr + 751 SD4_EMMC_TOP_BUFDAT_OFFSET, value); 752 } 753 /* 754 * BUG ALERT: 755 * This implementation has TWO issues that must be addressed before you 756 * can safely INCLUDE_EMMC_DRIVER_WRITE_CODE. 757 * 758 * (1) For the last leftOver bytes, driver writes full word, which means 759 * some of the eMMC content (i.e. "4 - leftOver" will be erroneously 760 * overwritten). 761 * (2) eMMC is a block device. What happens when less than a full block of 762 * data is submitted??? 763 */ 764 if (leftOver > 0) { 765 value = ((*(uint32_t *)(data + i)) << (4 - leftOver)); 766 mmio_write_32(handle->ctrl.sdRegBaseAddr + 767 SD4_EMMC_TOP_BUFDAT_OFFSET, value); 768 } 769 770 return SD_OK; 771 } 772 #endif /* INCLUDE_EMMC_DRIVER_WRITE_CODE */ 773 774 /* 775 * Function to read maximal one block data directly 776 * from the data port of the host controller (FIFO). It is used 777 * in Non-DMA mode for data transmission. 778 */ 779 int32_t chal_sd_read_buffer(CHAL_HANDLE *sd_handle, uint32_t length, 780 uint8_t *data) 781 { 782 uint32_t i, size, leftOver, blockSize, value; 783 struct sd_dev *handle; 784 785 if (sd_handle == NULL) 786 return SD_INVALID_HANDLE; 787 788 handle = (struct sd_dev *)sd_handle; 789 790 value = 0; 791 792 blockSize = handle->cfg.blockSize; 793 794 /* PIO mode, extract fifo word by word */ 795 if (length >= blockSize) { 796 size = blockSize; 797 leftOver = 0; 798 } else { 799 leftOver = length % 4; 800 size = ((length >> 2) << 2); 801 } 802 803 for (i = 0; i < size; i += 4) { 804 value = 805 mmio_read_32(handle->ctrl.sdRegBaseAddr + 806 SD4_EMMC_TOP_BUFDAT_OFFSET); 807 memcpy((void *)(data + i), &value, sizeof(uint32_t)); 808 } 809 810 if (leftOver > 0) { 811 value = mmio_read_32(handle->ctrl.sdRegBaseAddr + 812 SD4_EMMC_TOP_BUFDAT_OFFSET); 813 814 /* 815 * Copy remaining non-full word bytes. 816 * (We run ARM as Little Endian) 817 */ 818 uint8_t j = 0; 819 820 for (j = 0; j < leftOver; j++) { 821 data[i + j] = (value >> (j * 8)) & 0xFF; 822 } 823 } 824 825 return SD_OK; 826 } 827 828 /* 829 * Resets both DAT or CMD line. 830 */ 831 int32_t chal_sd_reset_line(CHAL_HANDLE *sd_handle, uint32_t line) 832 { 833 uint32_t control, flag; 834 struct sd_dev *handle; 835 836 if (sd_handle == NULL) 837 return SD_INVALID_HANDLE; 838 839 handle = (struct sd_dev *) sd_handle; 840 841 flag = SD4_EMMC_TOP_CTRL1_CMDRST_MASK | SD4_EMMC_TOP_CTRL1_DATRST_MASK; 842 843 if (flag != (line | flag)) 844 return SD_FAIL; 845 846 control = mmio_read_32(handle->ctrl.sdRegBaseAddr + 847 SD4_EMMC_TOP_CTRL1_OFFSET); 848 control |= line; 849 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET, 850 control); 851 852 /* reset CMD and DATA line should always work, no need to timed out */ 853 do { 854 control = mmio_read_32(handle->ctrl.sdRegBaseAddr + 855 SD4_EMMC_TOP_CTRL1_OFFSET); 856 } while (control & line); 857 858 return SD_OK; 859 } 860 861 /* 862 * Function to be called once a SD command is done to read 863 * back it's response data. 864 */ 865 int32_t chal_sd_get_response(CHAL_HANDLE *sd_handle, uint32_t *resp) 866 { 867 struct sd_dev *handle; 868 869 if (sd_handle == NULL) 870 return SD_INVALID_HANDLE; 871 872 handle = (struct sd_dev *) sd_handle; 873 resp[0] = mmio_read_32(handle->ctrl.sdRegBaseAddr + 874 SD4_EMMC_TOP_RESP0_OFFSET); 875 resp[1] = mmio_read_32(handle->ctrl.sdRegBaseAddr + 876 SD4_EMMC_TOP_RESP2_OFFSET); 877 resp[2] = mmio_read_32(handle->ctrl.sdRegBaseAddr + 878 SD4_EMMC_TOP_RESP4_OFFSET); 879 resp[3] = mmio_read_32(handle->ctrl.sdRegBaseAddr + 880 SD4_EMMC_TOP_RESP6_OFFSET); 881 882 return SD_OK; 883 } 884 885 /* 886 * The function is called to clean all the pending interrupts. 887 */ 888 int32_t chal_sd_clear_pending_irq(CHAL_HANDLE *sd_handle) 889 { 890 uint32_t status = SD_OK; 891 struct sd_dev *handle; 892 893 if (sd_handle == NULL) 894 return SD_INVALID_HANDLE; 895 896 handle = (struct sd_dev *)sd_handle; 897 898 /* Make sure clean all interrupts */ 899 do { 900 mmio_write_32(handle->ctrl.sdRegBaseAddr + 901 SD4_EMMC_TOP_INTR_OFFSET, 0xFFFFFFFF); 902 SD_US_DELAY(10); 903 } while (mmio_read_32(handle->ctrl.sdRegBaseAddr + 904 SD4_EMMC_TOP_INTR_OFFSET)); 905 906 return status; 907 } 908 909 /* 910 * The function returns interrupt status register value. 911 */ 912 int32_t chal_sd_get_irq_status(CHAL_HANDLE *sd_handle) 913 { 914 struct sd_dev *handle; 915 916 if (sd_handle == NULL) 917 return SD_INVALID_HANDLE; 918 919 handle = (struct sd_dev *) sd_handle; 920 921 return (mmio_read_32(handle->ctrl.sdRegBaseAddr + 922 SD4_EMMC_TOP_INTR_OFFSET)); 923 } 924 925 /* 926 * The function clears interrupt(s) specified in the mask. 927 */ 928 int32_t chal_sd_clear_irq(CHAL_HANDLE *sd_handle, uint32_t mask) 929 { 930 struct sd_dev *handle; 931 932 if (sd_handle == NULL) 933 return SD_INVALID_HANDLE; 934 935 handle = (struct sd_dev *) sd_handle; 936 937 /* Make sure clean masked interrupts */ 938 do { 939 mmio_write_32(handle->ctrl.sdRegBaseAddr + 940 SD4_EMMC_TOP_INTR_OFFSET, mask); 941 SD_US_DELAY(10); 942 } while (mask & 943 mmio_read_32(handle->ctrl.sdRegBaseAddr + 944 SD4_EMMC_TOP_INTR_OFFSET)); 945 946 return SD_OK; 947 } 948 949 /* 950 * Description: The function configures the SD host controller. 951 */ 952 int32_t chal_sd_config(CHAL_HANDLE *sd_handle, uint32_t speed, uint32_t retry, 953 uint32_t boundary, uint32_t blkSize, uint32_t dma) 954 { 955 struct sd_dev *handle; 956 957 if (sd_handle == NULL) 958 return SD_INVALID_HANDLE; 959 960 handle = (struct sd_dev *) sd_handle; 961 962 handle->cfg.speedMode = speed; 963 handle->cfg.retryLimit = retry; 964 handle->cfg.dmaBoundary = boundary; 965 handle->cfg.blockSize = blkSize; 966 967 chal_sd_set_dma(sd_handle, dma); 968 SD_US_DELAY(100); 969 chal_sd_set_dma_boundary(handle, boundary); 970 SD_US_DELAY(100); 971 972 chal_sd_set_speed(sd_handle, speed); 973 974 SD_US_DELAY(100); 975 return SD_OK; 976 } 977 978 /* 979 * Cleans up HC FIFO. 980 */ 981 void chal_sd_dump_fifo(CHAL_HANDLE *sd_handle) 982 { 983 struct sd_dev *handle; 984 985 if (sd_handle == NULL) 986 return; 987 988 handle = (struct sd_dev *)sd_handle; 989 990 /* in case there still data in the host buffer */ 991 while (mmio_read_32(handle->ctrl.sdRegBaseAddr + 992 SD4_EMMC_TOP_PSTATE_OFFSET) & 0x800) { 993 mmio_read_32(handle->ctrl.sdRegBaseAddr + 994 SD4_EMMC_TOP_BUFDAT_OFFSET); 995 }; 996 } 997 998 /* 999 * Enable or disable a SD interrupt signal. 1000 */ 1001 void chal_sd_set_irq_signal(CHAL_HANDLE *sd_handle, uint32_t mask, 1002 uint32_t state) 1003 { 1004 struct sd_dev *handle; 1005 1006 if (sd_handle == NULL) 1007 return; 1008 1009 handle = (struct sd_dev *)sd_handle; 1010 1011 if (state) 1012 mmio_setbits_32(handle->ctrl.sdRegBaseAddr + 1013 SD4_EMMC_TOP_INTREN2_OFFSET, mask); 1014 else 1015 mmio_clrbits_32(handle->ctrl.sdRegBaseAddr + 1016 SD4_EMMC_TOP_INTREN2_OFFSET, mask); 1017 } 1018