xref: /rk3399_ARM-atf/drivers/arm/sp804/sp804_delay_timer.c (revision 51faada71a219a8b94cd8d8e423f0f22e9da4d8f)
1 /*
2  * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * Redistributions of source code must retain the above copyright notice, this
8  * list of conditions and the following disclaimer.
9  *
10  * Redistributions in binary form must reproduce the above copyright notice,
11  * this list of conditions and the following disclaimer in the documentation
12  * and/or other materials provided with the distribution.
13  *
14  * Neither the name of ARM nor the names of its contributors may be used
15  * to endorse or promote products derived from this software without specific
16  * prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28  * POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 #include <assert.h>
32 #include <delay_timer.h>
33 #include <mmio.h>
34 
35 uintptr_t sp804_base_addr;
36 
37 #define SP804_TIMER1_LOAD	(sp804_base_addr + 0x000)
38 #define SP804_TIMER1_VALUE	(sp804_base_addr + 0x004)
39 #define SP804_TIMER1_CONTROL	(sp804_base_addr + 0x008)
40 #define SP804_TIMER1_BGLOAD	(sp804_base_addr + 0x018)
41 
42 #define TIMER_CTRL_ONESHOT	(1 << 0)
43 #define TIMER_CTRL_32BIT	(1 << 1)
44 #define TIMER_CTRL_DIV1		(0 << 2)
45 #define TIMER_CTRL_DIV16	(1 << 2)
46 #define TIMER_CTRL_DIV256	(2 << 2)
47 #define TIMER_CTRL_IE		(1 << 5)
48 #define TIMER_CTRL_PERIODIC	(1 << 6)
49 #define TIMER_CTRL_ENABLE	(1 << 7)
50 
51 /********************************************************************
52  * The SP804 timer delay function
53  ********************************************************************/
54 uint32_t sp804_get_timer_value(void)
55 {
56 	return mmio_read_32(SP804_TIMER1_VALUE);
57 }
58 
59 /********************************************************************
60  * Initialize the 1st timer in the SP804 dual timer with a base
61  * address and a timer ops
62  ********************************************************************/
63 void sp804_timer_ops_init(uintptr_t base_addr, const timer_ops_t *ops)
64 {
65 	assert(base_addr != 0);
66 	assert(ops != 0 && ops->get_timer_value == sp804_get_timer_value);
67 
68 	sp804_base_addr = base_addr;
69 	timer_init(ops);
70 
71 	/* disable timer1 */
72 	mmio_write_32(SP804_TIMER1_CONTROL, 0);
73 	mmio_write_32(SP804_TIMER1_LOAD, UINT32_MAX);
74 	mmio_write_32(SP804_TIMER1_VALUE, UINT32_MAX);
75 
76 	/* enable as a free running 32-bit counter */
77 	mmio_write_32(SP804_TIMER1_CONTROL,
78 			TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE);
79 }
80