1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <cdefs.h> 9 #include <drivers/arm/smmu_v3.h> 10 #include <lib/mmio.h> 11 12 /* SMMU poll number of retries */ 13 #define SMMU_POLL_RETRY 1000000 14 15 static int __init smmuv3_poll(uintptr_t smmu_reg, uint32_t mask, 16 uint32_t value) 17 { 18 uint32_t reg_val, retries = SMMU_POLL_RETRY; 19 20 do { 21 reg_val = mmio_read_32(smmu_reg); 22 if ((reg_val & mask) == value) 23 return 0; 24 } while (--retries != 0U); 25 26 ERROR("Failed to poll SMMUv3 register @%p\n", (void *)smmu_reg); 27 ERROR("Read value 0x%x, expected 0x%x\n", reg_val, 28 value == 0U ? reg_val & ~mask : reg_val | mask); 29 return -1; 30 } 31 32 /* 33 * Abort all incoming transactions in order to implement a default 34 * deny policy on reset. 35 */ 36 int __init smmuv3_security_init(uintptr_t smmu_base) 37 { 38 /* Attribute update has completed when SMMU_(S)_GBPA.Update bit is 0 */ 39 if (smmuv3_poll(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE, 0U) != 0U) 40 return -1; 41 42 /* 43 * SMMU_(S)_CR0 resets to zero with all streams bypassing the SMMU, 44 * so just abort all incoming transactions. 45 */ 46 mmio_setbits_32(smmu_base + SMMU_GBPA, 47 SMMU_GBPA_UPDATE | SMMU_GBPA_ABORT); 48 49 if (smmuv3_poll(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE, 0U) != 0U) 50 return -1; 51 52 /* Check if the SMMU supports secure state */ 53 if ((mmio_read_32(smmu_base + SMMU_S_IDR1) & 54 SMMU_S_IDR1_SECURE_IMPL) == 0U) 55 return 0; 56 57 /* Abort all incoming secure transactions */ 58 if (smmuv3_poll(smmu_base + SMMU_S_GBPA, SMMU_S_GBPA_UPDATE, 0U) != 0U) 59 return -1; 60 61 mmio_setbits_32(smmu_base + SMMU_S_GBPA, 62 SMMU_S_GBPA_UPDATE | SMMU_S_GBPA_ABORT); 63 64 return smmuv3_poll(smmu_base + SMMU_S_GBPA, SMMU_S_GBPA_UPDATE, 0U); 65 } 66 67 /* 68 * Initialize the SMMU by invalidating all secure caches and TLBs. 69 * Abort all incoming transactions in order to implement a default 70 * deny policy on reset 71 */ 72 int __init smmuv3_init(uintptr_t smmu_base) 73 { 74 /* Abort all incoming transactions */ 75 if (smmuv3_security_init(smmu_base) != 0) 76 return -1; 77 78 /* Check if the SMMU supports secure state */ 79 if ((mmio_read_32(smmu_base + SMMU_S_IDR1) & 80 SMMU_S_IDR1_SECURE_IMPL) == 0U) 81 return 0; 82 /* 83 * Initiate invalidation of secure caches and TLBs if the SMMU 84 * supports secure state. If not, it's implementation defined 85 * as to how SMMU_S_INIT register is accessed. 86 */ 87 mmio_write_32(smmu_base + SMMU_S_INIT, SMMU_S_INIT_INV_ALL); 88 89 /* Wait for global invalidation operation to finish */ 90 return smmuv3_poll(smmu_base + SMMU_S_INIT, 91 SMMU_S_INIT_INV_ALL, 0U); 92 } 93