1*1154586bSJeenu Viswambharan /* 2*1154586bSJeenu Viswambharan * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*1154586bSJeenu Viswambharan * 4*1154586bSJeenu Viswambharan * SPDX-License-Identifier: BSD-3-Clause 5*1154586bSJeenu Viswambharan */ 6*1154586bSJeenu Viswambharan 7*1154586bSJeenu Viswambharan #include <mmio.h> 8*1154586bSJeenu Viswambharan #include <smmu_v3.h> 9*1154586bSJeenu Viswambharan 10*1154586bSJeenu Viswambharan /* Test for pending invalidate */ 11*1154586bSJeenu Viswambharan #define INVAL_PENDING(base) \ 12*1154586bSJeenu Viswambharan smmuv3_read_s_init(base) & SMMU_S_INIT_INV_ALL_MASK 13*1154586bSJeenu Viswambharan 14*1154586bSJeenu Viswambharan static inline uint32_t smmuv3_read_s_idr1(uintptr_t base) 15*1154586bSJeenu Viswambharan { 16*1154586bSJeenu Viswambharan return mmio_read_32(base + SMMU_S_IDR1); 17*1154586bSJeenu Viswambharan } 18*1154586bSJeenu Viswambharan 19*1154586bSJeenu Viswambharan static inline uint32_t smmuv3_read_s_init(uintptr_t base) 20*1154586bSJeenu Viswambharan { 21*1154586bSJeenu Viswambharan return mmio_read_32(base + SMMU_S_INIT); 22*1154586bSJeenu Viswambharan } 23*1154586bSJeenu Viswambharan 24*1154586bSJeenu Viswambharan static inline void smmuv3_write_s_init(uintptr_t base, uint32_t value) 25*1154586bSJeenu Viswambharan { 26*1154586bSJeenu Viswambharan mmio_write_32(base + SMMU_S_INIT, value); 27*1154586bSJeenu Viswambharan } 28*1154586bSJeenu Viswambharan 29*1154586bSJeenu Viswambharan /* 30*1154586bSJeenu Viswambharan * Initialize the SMMU by invalidating all secure caches and TLBs. 31*1154586bSJeenu Viswambharan * 32*1154586bSJeenu Viswambharan * Returns 0 on success, and -1 on failure. 33*1154586bSJeenu Viswambharan */ 34*1154586bSJeenu Viswambharan int smmuv3_init(uintptr_t smmu_base) 35*1154586bSJeenu Viswambharan { 36*1154586bSJeenu Viswambharan uint32_t idr1_reg; 37*1154586bSJeenu Viswambharan 38*1154586bSJeenu Viswambharan /* 39*1154586bSJeenu Viswambharan * Invalidation of secure caches and TLBs is required only if the SMMU 40*1154586bSJeenu Viswambharan * supports secure state. If not, it's implementation defined as to how 41*1154586bSJeenu Viswambharan * SMMU_S_INIT register is accessed. 42*1154586bSJeenu Viswambharan */ 43*1154586bSJeenu Viswambharan idr1_reg = smmuv3_read_s_idr1(smmu_base); 44*1154586bSJeenu Viswambharan if (!((idr1_reg >> SMMU_S_IDR1_SECURE_IMPL_SHIFT) & 45*1154586bSJeenu Viswambharan SMMU_S_IDR1_SECURE_IMPL_MASK)) { 46*1154586bSJeenu Viswambharan return -1; 47*1154586bSJeenu Viswambharan } 48*1154586bSJeenu Viswambharan 49*1154586bSJeenu Viswambharan /* Initiate invalidation, and wait for it to finish */ 50*1154586bSJeenu Viswambharan smmuv3_write_s_init(smmu_base, SMMU_S_INIT_INV_ALL_MASK); 51*1154586bSJeenu Viswambharan while (INVAL_PENDING(smmu_base)) 52*1154586bSJeenu Viswambharan ; 53*1154586bSJeenu Viswambharan 54*1154586bSJeenu Viswambharan return 0; 55*1154586bSJeenu Viswambharan } 56