1*c20c0525SVishnu Banavath /* 2*c20c0525SVishnu Banavath * Copyright (c) 2019, Arm Limited. All rights reserved. 3*c20c0525SVishnu Banavath * 4*c20c0525SVishnu Banavath * SPDX-License-Identifier: BSD-3-Clause 5*c20c0525SVishnu Banavath */ 6*c20c0525SVishnu Banavath 7*c20c0525SVishnu Banavath #include <assert.h> 8*c20c0525SVishnu Banavath #include <drivers/arm/scu.h> 9*c20c0525SVishnu Banavath #include <lib/mmio.h> 10*c20c0525SVishnu Banavath #include <plat/common/platform.h> 11*c20c0525SVishnu Banavath #include <stdint.h> 12*c20c0525SVishnu Banavath 13*c20c0525SVishnu Banavath /******************************************************************************* 14*c20c0525SVishnu Banavath * Turn ON snoop control unit. This is needed to synchronize the data between 15*c20c0525SVishnu Banavath * CPU's. 16*c20c0525SVishnu Banavath ******************************************************************************/ enable_snoop_ctrl_unit(uintptr_t base)17*c20c0525SVishnu Banavathvoid enable_snoop_ctrl_unit(uintptr_t base) 18*c20c0525SVishnu Banavath { 19*c20c0525SVishnu Banavath uint32_t scu_ctrl; 20*c20c0525SVishnu Banavath 21*c20c0525SVishnu Banavath INFO("[SCU]: enabling snoop control unit ... \n"); 22*c20c0525SVishnu Banavath 23*c20c0525SVishnu Banavath assert(base != 0U); 24*c20c0525SVishnu Banavath scu_ctrl = mmio_read_32(base + SCU_CTRL_REG); 25*c20c0525SVishnu Banavath 26*c20c0525SVishnu Banavath /* already enabled? */ 27*c20c0525SVishnu Banavath if ((scu_ctrl & SCU_ENABLE_BIT) != 0) { 28*c20c0525SVishnu Banavath return; 29*c20c0525SVishnu Banavath } 30*c20c0525SVishnu Banavath 31*c20c0525SVishnu Banavath scu_ctrl |= SCU_ENABLE_BIT; 32*c20c0525SVishnu Banavath mmio_write_32(base + SCU_CTRL_REG, scu_ctrl); 33*c20c0525SVishnu Banavath } 34*c20c0525SVishnu Banavath 35*c20c0525SVishnu Banavath /******************************************************************************* 36*c20c0525SVishnu Banavath * Snoop Control Unit configuration register. This is read-only register and 37*c20c0525SVishnu Banavath * contains information such as 38*c20c0525SVishnu Banavath * - number of CPUs present 39*c20c0525SVishnu Banavath * - is a particular CPU operating in SMP mode or AMP mode 40*c20c0525SVishnu Banavath * - data cache size of a particular CPU 41*c20c0525SVishnu Banavath * - does SCU has ACP port 42*c20c0525SVishnu Banavath * - is L2CPRESENT 43*c20c0525SVishnu Banavath * NOTE: user of this API should interpert the bits in this register according 44*c20c0525SVishnu Banavath * to the TRM 45*c20c0525SVishnu Banavath ******************************************************************************/ read_snoop_ctrl_unit_cfg(uintptr_t base)46*c20c0525SVishnu Banavathuint32_t read_snoop_ctrl_unit_cfg(uintptr_t base) 47*c20c0525SVishnu Banavath { 48*c20c0525SVishnu Banavath assert(base != 0U); 49*c20c0525SVishnu Banavath 50*c20c0525SVishnu Banavath return mmio_read_32(base + SCU_CFG_REG); 51*c20c0525SVishnu Banavath } 52