1*f79abf5eSAditya Angadi /* 2*f79abf5eSAditya Angadi * Copyright (c) 2019, ARM Limited. All rights reserved. 3*f79abf5eSAditya Angadi * 4*f79abf5eSAditya Angadi * SPDX-License-Identifier: BSD-3-Clause 5*f79abf5eSAditya Angadi */ 6*f79abf5eSAditya Angadi 7*f79abf5eSAditya Angadi #include <plat/common/platform.h> 8*f79abf5eSAditya Angadi #include <drivers/arm/sbsa.h> 9*f79abf5eSAditya Angadi #include <lib/mmio.h> 10*f79abf5eSAditya Angadi #include <stdint_.h> 11*f79abf5eSAditya Angadi #include <assert.h> 12*f79abf5eSAditya Angadi 13*f79abf5eSAditya Angadi void sbsa_watchdog_offset_reg_write(uintptr_t base, uint64_t value) 14*f79abf5eSAditya Angadi { 15*f79abf5eSAditya Angadi assert((value >> SBSA_WDOG_WOR_WIDTH) == 0); 16*f79abf5eSAditya Angadi mmio_write_32(base + SBSA_WDOG_WOR_LOW_OFFSET, 17*f79abf5eSAditya Angadi ((uint32_t)value & UINT32_MAX)); 18*f79abf5eSAditya Angadi mmio_write_32(base + SBSA_WDOG_WOR_HIGH_OFFSET, (uint32_t)(value >> 32)); 19*f79abf5eSAditya Angadi } 20*f79abf5eSAditya Angadi 21*f79abf5eSAditya Angadi /* 22*f79abf5eSAditya Angadi * Start the watchdog timer at base address "base" for a 23*f79abf5eSAditya Angadi * period of "ms" milliseconds.The watchdog has to be 24*f79abf5eSAditya Angadi * refreshed within this time period. 25*f79abf5eSAditya Angadi */ 26*f79abf5eSAditya Angadi void sbsa_wdog_start(uintptr_t base, uint64_t ms) 27*f79abf5eSAditya Angadi { 28*f79abf5eSAditya Angadi uint64_t counter_freq; 29*f79abf5eSAditya Angadi uint64_t offset_reg_value; 30*f79abf5eSAditya Angadi 31*f79abf5eSAditya Angadi counter_freq = (uint64_t)plat_get_syscnt_freq2(); 32*f79abf5eSAditya Angadi offset_reg_value = ms * counter_freq / 1000; 33*f79abf5eSAditya Angadi 34*f79abf5eSAditya Angadi sbsa_watchdog_offset_reg_write(base, offset_reg_value); 35*f79abf5eSAditya Angadi mmio_write_32(base + SBSA_WDOG_WCS_OFFSET, SBSA_WDOG_WCS_EN); 36*f79abf5eSAditya Angadi } 37*f79abf5eSAditya Angadi 38*f79abf5eSAditya Angadi /* Stop the watchdog */ 39*f79abf5eSAditya Angadi void sbsa_wdog_stop(uintptr_t base) 40*f79abf5eSAditya Angadi { 41*f79abf5eSAditya Angadi mmio_write_32(base + SBSA_WDOG_WCS_OFFSET, (0x0)); 42*f79abf5eSAditya Angadi } 43