18cef63d6SBoyan Karatotev /* 28cef63d6SBoyan Karatotev * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. 38cef63d6SBoyan Karatotev * 48cef63d6SBoyan Karatotev * SPDX-License-Identifier: BSD-3-Clause 58cef63d6SBoyan Karatotev */ 613b62814SBoyan Karatotev 713b62814SBoyan Karatotev #include <cdefs.h> 813b62814SBoyan Karatotev 9*82b228baSBoyan Karatotev #include <arch.h> 1013b62814SBoyan Karatotev #include <arch_features.h> 11*82b228baSBoyan Karatotev #include <arch_helpers.h> 12*82b228baSBoyan Karatotev 1313b62814SBoyan Karatotev #include <bl31/interrupt_mgmt.h> 1413b62814SBoyan Karatotev #include <common/debug.h> 1513b62814SBoyan Karatotev #include <drivers/arm/gicv5.h> 1613b62814SBoyan Karatotev 1713b62814SBoyan Karatotev void __init gicv5_driver_init(void) 1813b62814SBoyan Karatotev { 1913b62814SBoyan Karatotev } 2013b62814SBoyan Karatotev 2113b62814SBoyan Karatotev /* 2213b62814SBoyan Karatotev * There exists a theoretical configuration where FEAT_RME is enabled 2313b62814SBoyan Karatotev * without using TrustZone (i.e., no Secure world present). Currently, 2413b62814SBoyan Karatotev * there is no reliable mechanism to detect this scenario at runtime. 2513b62814SBoyan Karatotev * 2613b62814SBoyan Karatotev * TODO: Add support for this configuration in the future if required. 2713b62814SBoyan Karatotev */ 2813b62814SBoyan Karatotev bool gicv5_has_interrupt_type(unsigned int type) 2913b62814SBoyan Karatotev { 3013b62814SBoyan Karatotev switch (type) { 3113b62814SBoyan Karatotev case INTR_TYPE_EL3: 3213b62814SBoyan Karatotev case INTR_TYPE_S_EL1: 3313b62814SBoyan Karatotev case INTR_TYPE_NS: 3413b62814SBoyan Karatotev return true; 3513b62814SBoyan Karatotev case INTR_TYPE_RL: 3613b62814SBoyan Karatotev return is_feat_rme_supported(); 3713b62814SBoyan Karatotev default: 3813b62814SBoyan Karatotev return false; 3913b62814SBoyan Karatotev } 4013b62814SBoyan Karatotev } 4113b62814SBoyan Karatotev 4213b62814SBoyan Karatotev uint8_t gicv5_get_pending_interrupt_type(void) 4313b62814SBoyan Karatotev { 4413b62814SBoyan Karatotev /* there is no pending interrupt expected */ 4513b62814SBoyan Karatotev return INTR_TYPE_INVAL; 4613b62814SBoyan Karatotev } 47*82b228baSBoyan Karatotev 48*82b228baSBoyan Karatotev /* TODO: these will probably end up contexted. Make Linux work for now */ 49*82b228baSBoyan Karatotev void gicv5_enable_ppis(void) 50*82b228baSBoyan Karatotev { 51*82b228baSBoyan Karatotev uint64_t domainr = 0U; 52*82b228baSBoyan Karatotev 53*82b228baSBoyan Karatotev /* the only ones described in the device tree at the moment */ 54*82b228baSBoyan Karatotev write_icc_ppi_domainr(domainr, PPI_PMUIRQ, INTDMN_NS); 55*82b228baSBoyan Karatotev write_icc_ppi_domainr(domainr, PPI_GICMNT, INTDMN_NS); 56*82b228baSBoyan Karatotev write_icc_ppi_domainr(domainr, PPI_CNTHP, INTDMN_NS); 57*82b228baSBoyan Karatotev write_icc_ppi_domainr(domainr, PPI_CNTV, INTDMN_NS); 58*82b228baSBoyan Karatotev write_icc_ppi_domainr(domainr, PPI_CNTPS, INTDMN_NS); 59*82b228baSBoyan Karatotev write_icc_ppi_domainr(domainr, PPI_CNTP, INTDMN_NS); 60*82b228baSBoyan Karatotev 61*82b228baSBoyan Karatotev write_icc_ppi_domainr0_el3(domainr); 62*82b228baSBoyan Karatotev } 63