1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GICV3_PRIVATE_H__ 8 #define __GICV3_PRIVATE_H__ 9 10 #include <assert.h> 11 #include <gic_common.h> 12 #include <gicv3.h> 13 #include <mmio.h> 14 #include <stdint.h> 15 #include "../common/gic_common_private.h" 16 17 /******************************************************************************* 18 * GICv3 private macro definitions 19 ******************************************************************************/ 20 21 /* Constants to indicate the status of the RWP bit */ 22 #define RWP_TRUE U(1) 23 #define RWP_FALSE U(0) 24 25 /* 26 * Macro to convert an mpidr to a value suitable for programming into a 27 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant 28 * to GICv3. 29 */ 30 static inline u_register_t gicd_irouter_val_from_mpidr(u_register_t mpidr, 31 unsigned int irm) 32 { 33 return (mpidr & ~(U(0xff) << 24)) | 34 ((irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT); 35 } 36 37 /* 38 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] 39 * are zeroes. 40 */ 41 #ifdef AARCH32 42 static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) 43 { 44 return (((typer_val) >> 32) & U(0xffffff)); 45 } 46 #else 47 static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) 48 { 49 return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | 50 ((typer_val >> 32) & U(0xffffff)); 51 } 52 #endif 53 54 /******************************************************************************* 55 * GICv3 private global variables declarations 56 ******************************************************************************/ 57 extern const gicv3_driver_data_t *gicv3_driver_data; 58 59 /******************************************************************************* 60 * Private GICv3 function prototypes for accessing entire registers. 61 * Note: The raw register values correspond to multiple interrupt IDs and 62 * the number of interrupt IDs involved depends on the register accessed. 63 ******************************************************************************/ 64 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id); 65 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id); 66 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); 67 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); 68 69 /******************************************************************************* 70 * Private GICv3 function prototypes for accessing the GIC registers 71 * corresponding to a single interrupt ID. These functions use bitwise 72 * operations or appropriate register accesses to modify or return 73 * the bit-field corresponding the single interrupt ID. 74 ******************************************************************************/ 75 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id); 76 unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id); 77 unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id); 78 unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id); 79 void gicd_set_igrpmodr(uintptr_t base, unsigned int id); 80 void gicr_set_igrpmodr0(uintptr_t base, unsigned int id); 81 void gicr_set_isenabler0(uintptr_t base, unsigned int id); 82 void gicr_set_icenabler0(uintptr_t base, unsigned int id); 83 void gicr_set_ispendr0(uintptr_t base, unsigned int id); 84 void gicr_set_icpendr0(uintptr_t base, unsigned int id); 85 void gicr_set_igroupr0(uintptr_t base, unsigned int id); 86 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id); 87 void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id); 88 void gicr_clr_igroupr0(uintptr_t base, unsigned int id); 89 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); 90 void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg); 91 void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg); 92 93 /******************************************************************************* 94 * Private GICv3 helper function prototypes 95 ******************************************************************************/ 96 void gicv3_spis_config_defaults(uintptr_t gicd_base); 97 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base); 98 #if !ERROR_DEPRECATED 99 void gicv3_secure_spis_config(uintptr_t gicd_base, 100 unsigned int num_ints, 101 const unsigned int *sec_intr_list, 102 unsigned int int_grp); 103 void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base, 104 unsigned int num_ints, 105 const unsigned int *sec_intr_list, 106 unsigned int int_grp); 107 #endif 108 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, 109 const interrupt_prop_t *interrupt_props, 110 unsigned int interrupt_props_num); 111 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, 112 const interrupt_prop_t *interrupt_props, 113 unsigned int interrupt_props_num); 114 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 115 unsigned int rdistif_num, 116 uintptr_t gicr_base, 117 mpidr_hash_fn mpidr_to_core_pos); 118 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base); 119 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base); 120 121 /******************************************************************************* 122 * GIC Distributor interface accessors 123 ******************************************************************************/ 124 /* 125 * Wait for updates to : 126 * GICD_CTLR[2:0] - the Group Enables 127 * GICD_CTLR[5:4] - the ARE bits 128 * GICD_ICENABLERn - the clearing of enable state for SPIs 129 */ 130 static inline void gicd_wait_for_pending_write(uintptr_t gicd_base) 131 { 132 while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U) 133 ; 134 } 135 136 static inline unsigned int gicd_read_pidr2(uintptr_t base) 137 { 138 return mmio_read_32(base + GICD_PIDR2_GICV3); 139 } 140 141 static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id) 142 { 143 assert(id >= MIN_SPI_ID); 144 return mmio_read_64(base + GICD_IROUTER + (id << 3)); 145 } 146 147 static inline void gicd_write_irouter(uintptr_t base, 148 unsigned int id, 149 unsigned long long affinity) 150 { 151 assert(id >= MIN_SPI_ID); 152 mmio_write_64(base + GICD_IROUTER + (id << 3), affinity); 153 } 154 155 static inline void gicd_clr_ctlr(uintptr_t base, 156 unsigned int bitmap, 157 unsigned int rwp) 158 { 159 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap); 160 if (rwp != 0U) 161 gicd_wait_for_pending_write(base); 162 } 163 164 static inline void gicd_set_ctlr(uintptr_t base, 165 unsigned int bitmap, 166 unsigned int rwp) 167 { 168 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap); 169 if (rwp != 0U) 170 gicd_wait_for_pending_write(base); 171 } 172 173 /******************************************************************************* 174 * GIC Redistributor interface accessors 175 ******************************************************************************/ 176 static inline uint32_t gicr_read_ctlr(uintptr_t base) 177 { 178 return mmio_read_32(base + GICR_CTLR); 179 } 180 181 static inline void gicr_write_ctlr(uintptr_t base, uint32_t val) 182 { 183 mmio_write_32(base + GICR_CTLR, val); 184 } 185 186 static inline unsigned long long gicr_read_typer(uintptr_t base) 187 { 188 return mmio_read_64(base + GICR_TYPER); 189 } 190 191 static inline unsigned int gicr_read_waker(uintptr_t base) 192 { 193 return mmio_read_32(base + GICR_WAKER); 194 } 195 196 static inline void gicr_write_waker(uintptr_t base, unsigned int val) 197 { 198 mmio_write_32(base + GICR_WAKER, val); 199 } 200 201 /* 202 * Wait for updates to : 203 * GICR_ICENABLER0 204 * GICR_CTLR.DPG1S 205 * GICR_CTLR.DPG1NS 206 * GICR_CTLR.DPG0 207 */ 208 static inline void gicr_wait_for_pending_write(uintptr_t gicr_base) 209 { 210 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) 211 ; 212 } 213 214 static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base) 215 { 216 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U) 217 ; 218 } 219 220 /* Private implementation of Distributor power control hooks */ 221 void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num); 222 void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num); 223 224 /******************************************************************************* 225 * GIC Re-distributor functions for accessing entire registers. 226 * Note: The raw register values correspond to multiple interrupt IDs and 227 * the number of interrupt IDs involved depends on the register accessed. 228 ******************************************************************************/ 229 static inline unsigned int gicr_read_icenabler0(uintptr_t base) 230 { 231 return mmio_read_32(base + GICR_ICENABLER0); 232 } 233 234 static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val) 235 { 236 mmio_write_32(base + GICR_ICENABLER0, val); 237 } 238 239 static inline unsigned int gicr_read_isenabler0(uintptr_t base) 240 { 241 return mmio_read_32(base + GICR_ISENABLER0); 242 } 243 244 static inline void gicr_write_icpendr0(uintptr_t base, unsigned int val) 245 { 246 mmio_write_32(base + GICR_ICPENDR0, val); 247 } 248 249 static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val) 250 { 251 mmio_write_32(base + GICR_ISENABLER0, val); 252 } 253 254 static inline unsigned int gicr_read_igroupr0(uintptr_t base) 255 { 256 return mmio_read_32(base + GICR_IGROUPR0); 257 } 258 259 static inline unsigned int gicr_read_ispendr0(uintptr_t base) 260 { 261 return mmio_read_32(base + GICR_ISPENDR0); 262 } 263 264 static inline void gicr_write_ispendr0(uintptr_t base, unsigned int val) 265 { 266 mmio_write_32(base + GICR_ISPENDR0, val); 267 } 268 269 static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val) 270 { 271 mmio_write_32(base + GICR_IGROUPR0, val); 272 } 273 274 static inline unsigned int gicr_read_igrpmodr0(uintptr_t base) 275 { 276 return mmio_read_32(base + GICR_IGRPMODR0); 277 } 278 279 static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val) 280 { 281 mmio_write_32(base + GICR_IGRPMODR0, val); 282 } 283 284 static inline unsigned int gicr_read_nsacr(uintptr_t base) 285 { 286 return mmio_read_32(base + GICR_NSACR); 287 } 288 289 static inline void gicr_write_nsacr(uintptr_t base, unsigned int val) 290 { 291 mmio_write_32(base + GICR_NSACR, val); 292 } 293 294 static inline unsigned int gicr_read_isactiver0(uintptr_t base) 295 { 296 return mmio_read_32(base + GICR_ISACTIVER0); 297 } 298 299 static inline void gicr_write_isactiver0(uintptr_t base, unsigned int val) 300 { 301 mmio_write_32(base + GICR_ISACTIVER0, val); 302 } 303 304 static inline unsigned int gicr_read_icfgr0(uintptr_t base) 305 { 306 return mmio_read_32(base + GICR_ICFGR0); 307 } 308 309 static inline unsigned int gicr_read_icfgr1(uintptr_t base) 310 { 311 return mmio_read_32(base + GICR_ICFGR1); 312 } 313 314 static inline void gicr_write_icfgr0(uintptr_t base, unsigned int val) 315 { 316 mmio_write_32(base + GICR_ICFGR0, val); 317 } 318 319 static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val) 320 { 321 mmio_write_32(base + GICR_ICFGR1, val); 322 } 323 324 static inline uint64_t gicr_read_propbaser(uintptr_t base) 325 { 326 return mmio_read_64(base + GICR_PROPBASER); 327 } 328 329 static inline void gicr_write_propbaser(uintptr_t base, uint64_t val) 330 { 331 mmio_write_64(base + GICR_PROPBASER, val); 332 } 333 334 static inline uint64_t gicr_read_pendbaser(uintptr_t base) 335 { 336 return mmio_read_64(base + GICR_PENDBASER); 337 } 338 339 static inline void gicr_write_pendbaser(uintptr_t base, uint64_t val) 340 { 341 mmio_write_64(base + GICR_PENDBASER, val); 342 } 343 344 /******************************************************************************* 345 * GIC ITS functions to read and write entire ITS registers. 346 ******************************************************************************/ 347 static inline uint32_t gits_read_ctlr(uintptr_t base) 348 { 349 return mmio_read_32(base + GITS_CTLR); 350 } 351 352 static inline void gits_write_ctlr(uintptr_t base, unsigned int val) 353 { 354 mmio_write_32(base + GITS_CTLR, val); 355 } 356 357 static inline uint64_t gits_read_cbaser(uintptr_t base) 358 { 359 return mmio_read_64(base + GITS_CBASER); 360 } 361 362 static inline void gits_write_cbaser(uintptr_t base, uint64_t val) 363 { 364 mmio_write_64(base + GITS_CBASER, val); 365 } 366 367 static inline uint64_t gits_read_cwriter(uintptr_t base) 368 { 369 return mmio_read_64(base + GITS_CWRITER); 370 } 371 372 static inline void gits_write_cwriter(uintptr_t base, uint64_t val) 373 { 374 mmio_write_64(base + GITS_CWRITER, val); 375 } 376 377 static inline uint64_t gits_read_baser(uintptr_t base, unsigned int its_table_id) 378 { 379 assert(its_table_id < 8U); 380 return mmio_read_64(base + GITS_BASER + (8U * its_table_id)); 381 } 382 383 static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id, uint64_t val) 384 { 385 assert(its_table_id < 8U); 386 mmio_write_64(base + GITS_BASER + (8U * its_table_id), val); 387 } 388 389 /* 390 * Wait for Quiescent bit when GIC ITS is disabled 391 */ 392 static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base) 393 { 394 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 395 while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0U) 396 ; 397 } 398 399 400 #endif /* __GICV3_PRIVATE_H__ */ 401