1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GICV3_PRIVATE_H 8 #define GICV3_PRIVATE_H 9 10 #include <assert.h> 11 #include <stdint.h> 12 13 #include <drivers/arm/gic_common.h> 14 #include <drivers/arm/gicv3.h> 15 #include <lib/mmio.h> 16 17 #include "../common/gic_common_private.h" 18 19 /******************************************************************************* 20 * GICv3 private macro definitions 21 ******************************************************************************/ 22 23 /* Constants to indicate the status of the RWP bit */ 24 #define RWP_TRUE U(1) 25 #define RWP_FALSE U(0) 26 27 /* Calculate GIC register bit number corresponding to its interrupt ID */ 28 #define BIT_NUM(REG, id) \ 29 ((id) & ((1U << REG##R_SHIFT) - 1U)) 30 31 /* 32 * Calculate 8, 32 and 64-bit GICD register offset 33 * corresponding to its interrupt ID 34 */ 35 #if GIC_EXT_INTID 36 /* GICv3.1 */ 37 #define GICD_OFFSET_8(REG, id) \ 38 (((id) <= MAX_SPI_ID) ? \ 39 GICD_##REG##R + (uintptr_t)(id) : \ 40 GICD_##REG##RE + (uintptr_t)(id) - MIN_ESPI_ID) 41 42 #define GICD_OFFSET(REG, id) \ 43 (((id) <= MAX_SPI_ID) ? \ 44 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \ 45 GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \ 46 REG##R_SHIFT) << 2)) 47 48 #define GICD_OFFSET_64(REG, id) \ 49 (((id) <= MAX_SPI_ID) ? \ 50 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) : \ 51 GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \ 52 REG##R_SHIFT) << 3)) 53 54 #else /* GICv3 */ 55 #define GICD_OFFSET_8(REG, id) \ 56 (GICD_##REG##R + (uintptr_t)(id)) 57 58 #define GICD_OFFSET(REG, id) \ 59 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2)) 60 61 #define GICD_OFFSET_64(REG, id) \ 62 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3)) 63 #endif /* GIC_EXT_INTID */ 64 65 /* 66 * Read/Write 8, 32 and 64-bit GIC Distributor register 67 * corresponding to its interrupt ID 68 */ 69 #define GICD_READ(REG, base, id) \ 70 mmio_read_32((base) + GICD_OFFSET(REG, (id))) 71 72 #define GICD_READ_64(REG, base, id) \ 73 mmio_read_64((base) + GICD_OFFSET_64(REG, (id))) 74 75 #define GICD_WRITE_8(REG, base, id, val) \ 76 mmio_write_8((base) + GICD_OFFSET_8(REG, (id)), (val)) 77 78 #define GICD_WRITE(REG, base, id, val) \ 79 mmio_write_32((base) + GICD_OFFSET(REG, (id)), (val)) 80 81 #define GICD_WRITE_64(REG, base, id, val) \ 82 mmio_write_64((base) + GICD_OFFSET_64(REG, (id)), (val)) 83 84 /* 85 * Bit operations on GIC Distributor register corresponding 86 * to its interrupt ID 87 */ 88 /* Get bit in GIC Distributor register */ 89 #define GICD_GET_BIT(REG, base, id) \ 90 ((mmio_read_32((base) + GICD_OFFSET(REG, (id))) >> \ 91 BIT_NUM(REG, (id))) & 1U) 92 93 /* Set bit in GIC Distributor register */ 94 #define GICD_SET_BIT(REG, base, id) \ 95 mmio_setbits_32((base) + GICD_OFFSET(REG, (id)), \ 96 ((uint32_t)1 << BIT_NUM(REG, (id)))) 97 98 /* Clear bit in GIC Distributor register */ 99 #define GICD_CLR_BIT(REG, base, id) \ 100 mmio_clrbits_32((base) + GICD_OFFSET(REG, (id)), \ 101 ((uint32_t)1 << BIT_NUM(REG, (id)))) 102 103 /* Write bit in GIC Distributor register */ 104 #define GICD_WRITE_BIT(REG, base, id) \ 105 mmio_write_32((base) + GICD_OFFSET(REG, (id)), \ 106 ((uint32_t)1 << BIT_NUM(REG, (id)))) 107 108 /* 109 * Calculate 8 and 32-bit GICR register offset 110 * corresponding to its interrupt ID 111 */ 112 #if GIC_EXT_INTID 113 /* GICv3.1 */ 114 #define GICR_OFFSET_8(REG, id) \ 115 (((id) <= MAX_PPI_ID) ? \ 116 GICR_##REG##R + (uintptr_t)(id) : \ 117 GICR_##REG##R + (uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID)) 118 119 #define GICR_OFFSET(REG, id) \ 120 (((id) <= MAX_PPI_ID) ? \ 121 GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \ 122 GICR_##REG##R + ((((uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID))\ 123 >> REG##R_SHIFT) << 2)) 124 #else /* GICv3 */ 125 #define GICR_OFFSET_8(REG, id) \ 126 (GICR_##REG##R + (uintptr_t)(id)) 127 128 #define GICR_OFFSET(REG, id) \ 129 (GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2)) 130 #endif /* GIC_EXT_INTID */ 131 132 /* Read/Write GIC Redistributor register corresponding to its interrupt ID */ 133 #define GICR_READ(REG, base, id) \ 134 mmio_read_32((base) + GICR_OFFSET(REG, (id))) 135 136 #define GICR_WRITE_8(REG, base, id, val) \ 137 mmio_write_8((base) + GICR_OFFSET_8(REG, (id)), (val)) 138 139 #define GICR_WRITE(REG, base, id, val) \ 140 mmio_write_32((base) + GICR_OFFSET(REG, (id)), (val)) 141 142 /* 143 * Bit operations on GIC Redistributor register 144 * corresponding to its interrupt ID 145 */ 146 /* Get bit in GIC Redistributor register */ 147 #define GICR_GET_BIT(REG, base, id) \ 148 ((mmio_read_32((base) + GICR_OFFSET(REG, (id))) >> \ 149 BIT_NUM(REG, (id))) & 1U) 150 151 /* Write bit in GIC Redistributor register */ 152 #define GICR_WRITE_BIT(REG, base, id) \ 153 mmio_write_32((base) + GICR_OFFSET(REG, (id)), \ 154 ((uint32_t)1 << BIT_NUM(REG, (id)))) 155 156 /* Set bit in GIC Redistributor register */ 157 #define GICR_SET_BIT(REG, base, id) \ 158 mmio_setbits_32((base) + GICR_OFFSET(REG, (id)), \ 159 ((uint32_t)1 << BIT_NUM(REG, (id)))) 160 161 /* Clear bit in GIC Redistributor register */ 162 #define GICR_CLR_BIT(REG, base, id) \ 163 mmio_clrbits_32((base) + GICR_OFFSET(REG, (id)), \ 164 ((uint32_t)1 << BIT_NUM(REG, (id)))) 165 166 /* 167 * Macro to convert an mpidr to a value suitable for programming into a 168 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant 169 * to GICv3. 170 */ 171 static inline u_register_t gicd_irouter_val_from_mpidr(u_register_t mpidr, 172 unsigned int irm) 173 { 174 return (mpidr & MPIDR_AFFINITY_MASK) | 175 ((irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT); 176 } 177 178 /* 179 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] 180 * are zeroes. 181 */ 182 #ifdef __aarch64__ 183 static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) 184 { 185 return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | 186 ((typer_val >> 32) & U(0xffffff)); 187 } 188 #else 189 static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) 190 { 191 return (((typer_val) >> 32) & U(0xffffff)); 192 } 193 #endif 194 195 /******************************************************************************* 196 * GICv3 private global variables declarations 197 ******************************************************************************/ 198 extern const gicv3_driver_data_t *gicv3_driver_data; 199 200 /******************************************************************************* 201 * Private GICv3 function prototypes for accessing entire registers. 202 * Note: The raw register values correspond to multiple interrupt IDs and 203 * the number of interrupt IDs involved depends on the register accessed. 204 ******************************************************************************/ 205 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id); 206 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id); 207 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); 208 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); 209 210 /******************************************************************************* 211 * Private GICv3 function prototypes for accessing the GIC registers 212 * corresponding to a single interrupt ID. These functions use bitwise 213 * operations or appropriate register accesses to modify or return 214 * the bit-field corresponding the single interrupt ID. 215 ******************************************************************************/ 216 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id); 217 unsigned int gicr_get_igrpmodr(uintptr_t base, unsigned int id); 218 unsigned int gicr_get_igroupr(uintptr_t base, unsigned int id); 219 unsigned int gicr_get_isactiver(uintptr_t base, unsigned int id); 220 void gicd_set_igrpmodr(uintptr_t base, unsigned int id); 221 void gicr_set_igrpmodr(uintptr_t base, unsigned int id); 222 void gicr_set_isenabler(uintptr_t base, unsigned int id); 223 void gicr_set_icenabler(uintptr_t base, unsigned int id); 224 void gicr_set_ispendr(uintptr_t base, unsigned int id); 225 void gicr_set_icpendr(uintptr_t base, unsigned int id); 226 void gicr_set_igroupr(uintptr_t base, unsigned int id); 227 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id); 228 void gicr_clr_igrpmodr(uintptr_t base, unsigned int id); 229 void gicr_clr_igroupr(uintptr_t base, unsigned int id); 230 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); 231 void gicr_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg); 232 233 /******************************************************************************* 234 * Private GICv3 helper function prototypes 235 ******************************************************************************/ 236 unsigned int gicv3_get_spi_limit(uintptr_t gicd_base); 237 unsigned int gicv3_get_espi_limit(uintptr_t gicd_base); 238 void gicv3_spis_config_defaults(uintptr_t gicd_base); 239 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base); 240 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, 241 const interrupt_prop_t *interrupt_props, 242 unsigned int interrupt_props_num); 243 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, 244 const interrupt_prop_t *interrupt_props, 245 unsigned int interrupt_props_num); 246 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 247 unsigned int rdistif_num, 248 uintptr_t gicr_base, 249 mpidr_hash_fn mpidr_to_core_pos); 250 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base); 251 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base); 252 253 /******************************************************************************* 254 * GIC Distributor interface accessors 255 ******************************************************************************/ 256 /* 257 * Wait for updates to: 258 * GICD_CTLR[2:0] - the Group Enables 259 * GICD_CTLR[7:4] - the ARE bits, E1NWF bit and DS bit 260 * GICD_ICENABLER<n> - the clearing of enable state for SPIs 261 */ 262 static inline void gicd_wait_for_pending_write(uintptr_t gicd_base) 263 { 264 while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U) { 265 } 266 } 267 268 static inline uint32_t gicd_read_pidr2(uintptr_t base) 269 { 270 return mmio_read_32(base + GICD_PIDR2_GICV3); 271 } 272 273 static inline uint64_t gicd_read_irouter(uintptr_t base, unsigned int id) 274 { 275 assert(id >= MIN_SPI_ID); 276 return GICD_READ_64(IROUTE, base, id); 277 } 278 279 static inline void gicd_write_irouter(uintptr_t base, 280 unsigned int id, 281 uint64_t affinity) 282 { 283 assert(id >= MIN_SPI_ID); 284 GICD_WRITE_64(IROUTE, base, id, affinity); 285 } 286 287 static inline void gicd_clr_ctlr(uintptr_t base, 288 unsigned int bitmap, 289 unsigned int rwp) 290 { 291 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap); 292 if (rwp != 0U) { 293 gicd_wait_for_pending_write(base); 294 } 295 } 296 297 static inline void gicd_set_ctlr(uintptr_t base, 298 unsigned int bitmap, 299 unsigned int rwp) 300 { 301 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap); 302 if (rwp != 0U) { 303 gicd_wait_for_pending_write(base); 304 } 305 } 306 307 /******************************************************************************* 308 * GIC Redistributor interface accessors 309 ******************************************************************************/ 310 static inline uint32_t gicr_read_ctlr(uintptr_t base) 311 { 312 return mmio_read_32(base + GICR_CTLR); 313 } 314 315 static inline void gicr_write_ctlr(uintptr_t base, uint32_t val) 316 { 317 mmio_write_32(base + GICR_CTLR, val); 318 } 319 320 static inline uint64_t gicr_read_typer(uintptr_t base) 321 { 322 return mmio_read_64(base + GICR_TYPER); 323 } 324 325 static inline uint32_t gicr_read_waker(uintptr_t base) 326 { 327 return mmio_read_32(base + GICR_WAKER); 328 } 329 330 static inline void gicr_write_waker(uintptr_t base, uint32_t val) 331 { 332 mmio_write_32(base + GICR_WAKER, val); 333 } 334 335 /* 336 * Wait for updates to: 337 * GICR_ICENABLER0 338 * GICR_CTLR.DPG1S 339 * GICR_CTLR.DPG1NS 340 * GICR_CTLR.DPG0 341 * GICR_CTLR, which clears EnableLPIs from 1 to 0 342 */ 343 static inline void gicr_wait_for_pending_write(uintptr_t gicr_base) 344 { 345 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) { 346 } 347 } 348 349 static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base) 350 { 351 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U) { 352 } 353 } 354 355 /* Private implementation of Distributor power control hooks */ 356 void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num); 357 void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num); 358 359 /******************************************************************************* 360 * GIC Redistributor functions for accessing entire registers. 361 * Note: The raw register values correspond to multiple interrupt IDs and 362 * the number of interrupt IDs involved depends on the register accessed. 363 ******************************************************************************/ 364 365 /* 366 * Accessors to read/write GIC Redistributor ICENABLER0 register 367 */ 368 static inline unsigned int gicr_read_icenabler0(uintptr_t base) 369 { 370 return mmio_read_32(base + GICR_ICENABLER0); 371 } 372 373 static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val) 374 { 375 mmio_write_32(base + GICR_ICENABLER0, val); 376 } 377 378 /* 379 * Accessors to read/write GIC Redistributor ICENABLER0 and ICENABLERE 380 * register corresponding to its number 381 */ 382 static inline unsigned int gicr_read_icenabler(uintptr_t base, 383 unsigned int reg_num) 384 { 385 return mmio_read_32(base + GICR_ICENABLER + (reg_num << 2)); 386 } 387 388 static inline void gicr_write_icenabler(uintptr_t base, unsigned int reg_num, 389 unsigned int val) 390 { 391 mmio_write_32(base + GICR_ICENABLER + (reg_num << 2), val); 392 } 393 394 /* 395 * Accessors to read/write GIC Redistributor ICFGR0, ICFGR1 registers 396 */ 397 static inline unsigned int gicr_read_icfgr0(uintptr_t base) 398 { 399 return mmio_read_32(base + GICR_ICFGR0); 400 } 401 402 static inline unsigned int gicr_read_icfgr1(uintptr_t base) 403 { 404 return mmio_read_32(base + GICR_ICFGR1); 405 } 406 407 static inline void gicr_write_icfgr0(uintptr_t base, unsigned int val) 408 { 409 mmio_write_32(base + GICR_ICFGR0, val); 410 } 411 412 static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val) 413 { 414 mmio_write_32(base + GICR_ICFGR1, val); 415 } 416 417 /* 418 * Accessors to read/write GIC Redistributor ICFGR0, ICFGR1 and ICFGRE 419 * register corresponding to its number 420 */ 421 static inline unsigned int gicr_read_icfgr(uintptr_t base, unsigned int reg_num) 422 { 423 return mmio_read_32(base + GICR_ICFGR + (reg_num << 2)); 424 } 425 426 static inline void gicr_write_icfgr(uintptr_t base, unsigned int reg_num, 427 unsigned int val) 428 { 429 mmio_write_32(base + GICR_ICFGR + (reg_num << 2), val); 430 } 431 432 /* 433 * Accessor to write GIC Redistributor ICPENDR0 register 434 */ 435 static inline void gicr_write_icpendr0(uintptr_t base, unsigned int val) 436 { 437 mmio_write_32(base + GICR_ICPENDR0, val); 438 } 439 440 /* 441 * Accessor to write GIC Redistributor ICPENDR0 and ICPENDRE 442 * register corresponding to its number 443 */ 444 static inline void gicr_write_icpendr(uintptr_t base, unsigned int reg_num, 445 unsigned int val) 446 { 447 mmio_write_32(base + GICR_ICPENDR + (reg_num << 2), val); 448 } 449 450 /* 451 * Accessors to read/write GIC Redistributor IGROUPR0 register 452 */ 453 static inline unsigned int gicr_read_igroupr0(uintptr_t base) 454 { 455 return mmio_read_32(base + GICR_IGROUPR0); 456 } 457 458 static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val) 459 { 460 mmio_write_32(base + GICR_IGROUPR0, val); 461 } 462 463 /* 464 * Accessors to read/write GIC Redistributor IGROUPR0 and IGROUPRE 465 * register corresponding to its number 466 */ 467 static inline unsigned int gicr_read_igroupr(uintptr_t base, 468 unsigned int reg_num) 469 { 470 return mmio_read_32(base + GICR_IGROUPR + (reg_num << 2)); 471 } 472 473 static inline void gicr_write_igroupr(uintptr_t base, unsigned int reg_num, 474 unsigned int val) 475 { 476 mmio_write_32(base + GICR_IGROUPR + (reg_num << 2), val); 477 } 478 479 /* 480 * Accessors to read/write GIC Redistributor IGRPMODR0 register 481 */ 482 static inline unsigned int gicr_read_igrpmodr0(uintptr_t base) 483 { 484 return mmio_read_32(base + GICR_IGRPMODR0); 485 } 486 487 static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val) 488 { 489 mmio_write_32(base + GICR_IGRPMODR0, val); 490 } 491 492 /* 493 * Accessors to read/write GIC Redistributor IGRPMODR0 and IGRPMODRE 494 * register corresponding to its number 495 */ 496 static inline unsigned int gicr_read_igrpmodr(uintptr_t base, 497 unsigned int reg_num) 498 { 499 return mmio_read_32(base + GICR_IGRPMODR + (reg_num << 2)); 500 } 501 502 static inline void gicr_write_igrpmodr(uintptr_t base, unsigned int reg_num, 503 unsigned int val) 504 { 505 mmio_write_32(base + GICR_IGRPMODR + (reg_num << 2), val); 506 } 507 508 /* 509 * Accessors to read/write the GIC Redistributor IPRIORITYR(E) register 510 * corresponding to its number, 4 interrupts IDs at a time. 511 */ 512 static inline unsigned int gicr_ipriorityr_read(uintptr_t base, 513 unsigned int reg_num) 514 { 515 return mmio_read_32(base + GICR_IPRIORITYR + (reg_num << 2)); 516 } 517 518 static inline void gicr_ipriorityr_write(uintptr_t base, unsigned int reg_num, 519 unsigned int val) 520 { 521 mmio_write_32(base + GICR_IPRIORITYR + (reg_num << 2), val); 522 } 523 524 /* 525 * Accessors to read/write GIC Redistributor ISACTIVER0 register 526 */ 527 static inline unsigned int gicr_read_isactiver0(uintptr_t base) 528 { 529 return mmio_read_32(base + GICR_ISACTIVER0); 530 } 531 532 static inline void gicr_write_isactiver0(uintptr_t base, unsigned int val) 533 { 534 mmio_write_32(base + GICR_ISACTIVER0, val); 535 } 536 537 /* 538 * Accessors to read/write GIC Redistributor ISACTIVER0 and ISACTIVERE 539 * register corresponding to its number 540 */ 541 static inline unsigned int gicr_read_isactiver(uintptr_t base, 542 unsigned int reg_num) 543 { 544 return mmio_read_32(base + GICR_ISACTIVER + (reg_num << 2)); 545 } 546 547 static inline void gicr_write_isactiver(uintptr_t base, unsigned int reg_num, 548 unsigned int val) 549 { 550 mmio_write_32(base + GICR_ISACTIVER + (reg_num << 2), val); 551 } 552 553 /* 554 * Accessors to read/write GIC Redistributor ISENABLER0 register 555 */ 556 static inline unsigned int gicr_read_isenabler0(uintptr_t base) 557 { 558 return mmio_read_32(base + GICR_ISENABLER0); 559 } 560 561 static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val) 562 { 563 mmio_write_32(base + GICR_ISENABLER0, val); 564 } 565 566 /* 567 * Accessors to read/write GIC Redistributor ISENABLER0 and ISENABLERE 568 * register corresponding to its number 569 */ 570 static inline unsigned int gicr_read_isenabler(uintptr_t base, 571 unsigned int reg_num) 572 { 573 return mmio_read_32(base + GICR_ISENABLER + (reg_num << 2)); 574 } 575 576 static inline void gicr_write_isenabler(uintptr_t base, unsigned int reg_num, 577 unsigned int val) 578 { 579 mmio_write_32(base + GICR_ISENABLER + (reg_num << 2), val); 580 } 581 582 /* 583 * Accessors to read/write GIC Redistributor ISPENDR0 register 584 */ 585 static inline unsigned int gicr_read_ispendr0(uintptr_t base) 586 { 587 return mmio_read_32(base + GICR_ISPENDR0); 588 } 589 590 static inline void gicr_write_ispendr0(uintptr_t base, unsigned int val) 591 { 592 mmio_write_32(base + GICR_ISPENDR0, val); 593 } 594 595 /* 596 * Accessors to read/write GIC Redistributor ISPENDR0 and ISPENDRE 597 * register corresponding to its number 598 */ 599 static inline unsigned int gicr_read_ispendr(uintptr_t base, 600 unsigned int reg_num) 601 { 602 return mmio_read_32(base + GICR_ISPENDR + (reg_num << 2)); 603 } 604 605 static inline void gicr_write_ispendr(uintptr_t base, unsigned int reg_num, 606 unsigned int val) 607 { 608 mmio_write_32(base + GICR_ISPENDR + (reg_num << 2), val); 609 } 610 611 /* 612 * Accessors to read/write GIC Redistributor NSACR register 613 */ 614 static inline unsigned int gicr_read_nsacr(uintptr_t base) 615 { 616 return mmio_read_32(base + GICR_NSACR); 617 } 618 619 static inline void gicr_write_nsacr(uintptr_t base, unsigned int val) 620 { 621 mmio_write_32(base + GICR_NSACR, val); 622 } 623 624 /* 625 * Accessors to read/write GIC Redistributor PROPBASER register 626 */ 627 static inline uint64_t gicr_read_propbaser(uintptr_t base) 628 { 629 return mmio_read_64(base + GICR_PROPBASER); 630 } 631 632 static inline void gicr_write_propbaser(uintptr_t base, uint64_t val) 633 { 634 mmio_write_64(base + GICR_PROPBASER, val); 635 } 636 637 /* 638 * Accessors to read/write GIC Redistributor PENDBASER register 639 */ 640 static inline uint64_t gicr_read_pendbaser(uintptr_t base) 641 { 642 return mmio_read_64(base + GICR_PENDBASER); 643 } 644 645 static inline void gicr_write_pendbaser(uintptr_t base, uint64_t val) 646 { 647 mmio_write_64(base + GICR_PENDBASER, val); 648 } 649 650 /******************************************************************************* 651 * GIC ITS functions to read and write entire ITS registers. 652 ******************************************************************************/ 653 static inline uint32_t gits_read_ctlr(uintptr_t base) 654 { 655 return mmio_read_32(base + GITS_CTLR); 656 } 657 658 static inline void gits_write_ctlr(uintptr_t base, uint32_t val) 659 { 660 mmio_write_32(base + GITS_CTLR, val); 661 } 662 663 static inline uint64_t gits_read_cbaser(uintptr_t base) 664 { 665 return mmio_read_64(base + GITS_CBASER); 666 } 667 668 static inline void gits_write_cbaser(uintptr_t base, uint64_t val) 669 { 670 mmio_write_64(base + GITS_CBASER, val); 671 } 672 673 static inline uint64_t gits_read_cwriter(uintptr_t base) 674 { 675 return mmio_read_64(base + GITS_CWRITER); 676 } 677 678 static inline void gits_write_cwriter(uintptr_t base, uint64_t val) 679 { 680 mmio_write_64(base + GITS_CWRITER, val); 681 } 682 683 static inline uint64_t gits_read_baser(uintptr_t base, 684 unsigned int its_table_id) 685 { 686 assert(its_table_id < 8U); 687 return mmio_read_64(base + GITS_BASER + (8U * its_table_id)); 688 } 689 690 static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id, 691 uint64_t val) 692 { 693 assert(its_table_id < 8U); 694 mmio_write_64(base + GITS_BASER + (8U * its_table_id), val); 695 } 696 697 /* 698 * Wait for Quiescent bit when GIC ITS is disabled 699 */ 700 static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base) 701 { 702 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 703 while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0U) { 704 } 705 } 706 707 #endif /* GICV3_PRIVATE_H */ 708