1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GICV3_PRIVATE_H 8 #define GICV3_PRIVATE_H 9 10 #include <assert.h> 11 #include <stdint.h> 12 13 #include <drivers/arm/gic_common.h> 14 #include <drivers/arm/gicv3.h> 15 #include <lib/mmio.h> 16 17 #include "../common/gic_common_private.h" 18 19 /******************************************************************************* 20 * GICv3 private macro definitions 21 ******************************************************************************/ 22 23 /* Constants to indicate the status of the RWP bit */ 24 #define RWP_TRUE U(1) 25 #define RWP_FALSE U(0) 26 27 /* Calculate GIC register bit number corresponding to its interrupt ID */ 28 #define BIT_NUM(REG, id) \ 29 ((id) & ((1U << REG##R_SHIFT) - 1U)) 30 31 /* 32 * Calculate 8, 32 and 64-bit GICD register offset 33 * corresponding to its interrupt ID 34 */ 35 #if GIC_EXT_INTID 36 /* GICv3.1 */ 37 #define GICD_OFFSET_8(REG, id) \ 38 (((id) <= MAX_SPI_ID) ? \ 39 GICD_##REG##R + (uintptr_t)(id) : \ 40 GICD_##REG##RE + (uintptr_t)(id) - MIN_ESPI_ID) 41 42 #define GICD_OFFSET(REG, id) \ 43 (((id) <= MAX_SPI_ID) ? \ 44 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \ 45 GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \ 46 REG##R_SHIFT) << 2)) 47 48 #define GICD_OFFSET_64(REG, id) \ 49 (((id) <= MAX_SPI_ID) ? \ 50 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) : \ 51 GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \ 52 REG##R_SHIFT) << 3)) 53 54 #else /* GICv3 */ 55 #define GICD_OFFSET_8(REG, id) \ 56 (GICD_##REG##R + (uintptr_t)(id)) 57 58 #define GICD_OFFSET(REG, id) \ 59 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2)) 60 61 #define GICD_OFFSET_64(REG, id) \ 62 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3)) 63 #endif /* GIC_EXT_INTID */ 64 65 /* 66 * Read/Write 8, 32 and 64-bit GIC Distributor register 67 * corresponding to its interrupt ID 68 */ 69 #define GICD_READ(REG, base, id) \ 70 mmio_read_32((base) + GICD_OFFSET(REG, (id))) 71 72 #define GICD_READ_64(REG, base, id) \ 73 mmio_read_64((base) + GICD_OFFSET_64(REG, (id))) 74 75 #define GICD_WRITE_8(REG, base, id, val) \ 76 mmio_write_8((base) + GICD_OFFSET_8(REG, (id)), (val)) 77 78 #define GICD_WRITE(REG, base, id, val) \ 79 mmio_write_32((base) + GICD_OFFSET(REG, (id)), (val)) 80 81 #define GICD_WRITE_64(REG, base, id, val) \ 82 mmio_write_64((base) + GICD_OFFSET_64(REG, (id)), (val)) 83 84 /* 85 * Bit operations on GIC Distributor register corresponding 86 * to its interrupt ID 87 */ 88 /* Get bit in GIC Distributor register */ 89 #define GICD_GET_BIT(REG, base, id) \ 90 ((mmio_read_32((base) + GICD_OFFSET(REG, (id))) >> \ 91 BIT_NUM(REG, (id))) & 1U) 92 93 /* Set bit in GIC Distributor register */ 94 #define GICD_SET_BIT(REG, base, id) \ 95 mmio_setbits_32((base) + GICD_OFFSET(REG, (id)), \ 96 ((uint32_t)1 << BIT_NUM(REG, (id)))) 97 98 /* Clear bit in GIC Distributor register */ 99 #define GICD_CLR_BIT(REG, base, id) \ 100 mmio_clrbits_32((base) + GICD_OFFSET(REG, (id)), \ 101 ((uint32_t)1 << BIT_NUM(REG, (id)))) 102 103 /* Write bit in GIC Distributor register */ 104 #define GICD_WRITE_BIT(REG, base, id) \ 105 mmio_write_32((base) + GICD_OFFSET(REG, (id)), \ 106 ((uint32_t)1 << BIT_NUM(REG, (id)))) 107 108 /* 109 * Calculate 8 and 32-bit GICR register offset 110 * corresponding to its interrupt ID 111 */ 112 #if GIC_EXT_INTID 113 /* GICv3.1 */ 114 #define GICR_OFFSET_8(REG, id) \ 115 (((id) <= MAX_PPI_ID) ? \ 116 GICR_##REG##R + (uintptr_t)(id) : \ 117 GICR_##REG##R + (uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID)) 118 119 #define GICR_OFFSET(REG, id) \ 120 (((id) <= MAX_PPI_ID) ? \ 121 GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \ 122 GICR_##REG##R + ((((uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID))\ 123 >> REG##R_SHIFT) << 2)) 124 #else /* GICv3 */ 125 #define GICR_OFFSET_8(REG, id) \ 126 (GICR_##REG##R + (uintptr_t)(id)) 127 128 #define GICR_OFFSET(REG, id) \ 129 (GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2)) 130 #endif /* GIC_EXT_INTID */ 131 132 /* Read/Write GIC Redistributor register corresponding to its interrupt ID */ 133 #define GICR_READ(REG, base, id) \ 134 mmio_read_32((base) + GICR_OFFSET(REG, (id))) 135 136 #define GICR_WRITE_8(REG, base, id, val) \ 137 mmio_write_8((base) + GICR_OFFSET_8(REG, (id)), (val)) 138 139 #define GICR_WRITE(REG, base, id, val) \ 140 mmio_write_32((base) + GICR_OFFSET(REG, (id)), (val)) 141 142 /* 143 * Bit operations on GIC Redistributor register 144 * corresponding to its interrupt ID 145 */ 146 /* Get bit in GIC Redistributor register */ 147 #define GICR_GET_BIT(REG, base, id) \ 148 ((mmio_read_32((base) + GICR_OFFSET(REG, (id))) >> \ 149 BIT_NUM(REG, (id))) & 1U) 150 151 /* Write bit in GIC Redistributor register */ 152 #define GICR_WRITE_BIT(REG, base, id) \ 153 mmio_write_32((base) + GICR_OFFSET(REG, (id)), \ 154 ((uint32_t)1 << BIT_NUM(REG, (id)))) 155 156 /* Set bit in GIC Redistributor register */ 157 #define GICR_SET_BIT(REG, base, id) \ 158 mmio_setbits_32((base) + GICR_OFFSET(REG, (id)), \ 159 ((uint32_t)1 << BIT_NUM(REG, (id)))) 160 161 /* Clear bit in GIC Redistributor register */ 162 #define GICR_CLR_BIT(REG, base, id) \ 163 mmio_clrbits_32((base) + GICR_OFFSET(REG, (id)), \ 164 ((uint32_t)1 << BIT_NUM(REG, (id)))) 165 166 /* 167 * Macro to convert an mpidr to a value suitable for programming into a 168 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant 169 * to GICv3. 170 */ 171 static inline u_register_t gicd_irouter_val_from_mpidr(u_register_t mpidr, 172 unsigned int irm) 173 { 174 return (mpidr & ~(U(0xff) << 24)) | 175 ((irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT); 176 } 177 178 /* 179 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] 180 * are zeroes. 181 */ 182 #ifdef __aarch64__ 183 static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) 184 { 185 return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | 186 ((typer_val >> 32) & U(0xffffff)); 187 } 188 #else 189 static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) 190 { 191 return (((typer_val) >> 32) & U(0xffffff)); 192 } 193 #endif 194 195 /******************************************************************************* 196 * GICv3 private global variables declarations 197 ******************************************************************************/ 198 extern const gicv3_driver_data_t *gicv3_driver_data; 199 200 /******************************************************************************* 201 * Private GICv3 function prototypes for accessing entire registers. 202 * Note: The raw register values correspond to multiple interrupt IDs and 203 * the number of interrupt IDs involved depends on the register accessed. 204 ******************************************************************************/ 205 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id); 206 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id); 207 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); 208 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); 209 210 /******************************************************************************* 211 * Private GICv3 function prototypes for accessing the GIC registers 212 * corresponding to a single interrupt ID. These functions use bitwise 213 * operations or appropriate register accesses to modify or return 214 * the bit-field corresponding the single interrupt ID. 215 ******************************************************************************/ 216 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id); 217 unsigned int gicr_get_igrpmodr(uintptr_t base, unsigned int id); 218 unsigned int gicr_get_igroupr(uintptr_t base, unsigned int id); 219 unsigned int gicr_get_isactiver(uintptr_t base, unsigned int id); 220 void gicd_set_igrpmodr(uintptr_t base, unsigned int id); 221 void gicr_set_igrpmodr(uintptr_t base, unsigned int id); 222 void gicr_set_isenabler(uintptr_t base, unsigned int id); 223 void gicr_set_icenabler(uintptr_t base, unsigned int id); 224 void gicr_set_ispendr(uintptr_t base, unsigned int id); 225 void gicr_set_icpendr(uintptr_t base, unsigned int id); 226 void gicr_set_igroupr(uintptr_t base, unsigned int id); 227 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id); 228 void gicr_clr_igrpmodr(uintptr_t base, unsigned int id); 229 void gicr_clr_igroupr(uintptr_t base, unsigned int id); 230 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); 231 void gicr_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg); 232 233 /******************************************************************************* 234 * Private GICv3 helper function prototypes 235 ******************************************************************************/ 236 void gicv3_spis_config_defaults(uintptr_t gicd_base); 237 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base); 238 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, 239 const interrupt_prop_t *interrupt_props, 240 unsigned int interrupt_props_num); 241 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, 242 const interrupt_prop_t *interrupt_props, 243 unsigned int interrupt_props_num); 244 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 245 unsigned int rdistif_num, 246 uintptr_t gicr_base, 247 mpidr_hash_fn mpidr_to_core_pos); 248 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base); 249 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base); 250 251 /******************************************************************************* 252 * GIC Distributor interface accessors 253 ******************************************************************************/ 254 /* 255 * Wait for updates to: 256 * GICD_CTLR[2:0] - the Group Enables 257 * GICD_CTLR[7:4] - the ARE bits, E1NWF bit and DS bit 258 * GICD_ICENABLER<n> - the clearing of enable state for SPIs 259 */ 260 static inline void gicd_wait_for_pending_write(uintptr_t gicd_base) 261 { 262 while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U) { 263 } 264 } 265 266 static inline uint32_t gicd_read_pidr2(uintptr_t base) 267 { 268 return mmio_read_32(base + GICD_PIDR2_GICV3); 269 } 270 271 static inline uint64_t gicd_read_irouter(uintptr_t base, unsigned int id) 272 { 273 assert(id >= MIN_SPI_ID); 274 return GICD_READ_64(IROUTE, base, id); 275 } 276 277 static inline void gicd_write_irouter(uintptr_t base, 278 unsigned int id, 279 uint64_t affinity) 280 { 281 assert(id >= MIN_SPI_ID); 282 GICD_WRITE_64(IROUTE, base, id, affinity); 283 } 284 285 static inline void gicd_clr_ctlr(uintptr_t base, 286 unsigned int bitmap, 287 unsigned int rwp) 288 { 289 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap); 290 if (rwp != 0U) { 291 gicd_wait_for_pending_write(base); 292 } 293 } 294 295 static inline void gicd_set_ctlr(uintptr_t base, 296 unsigned int bitmap, 297 unsigned int rwp) 298 { 299 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap); 300 if (rwp != 0U) { 301 gicd_wait_for_pending_write(base); 302 } 303 } 304 305 /******************************************************************************* 306 * GIC Redistributor interface accessors 307 ******************************************************************************/ 308 static inline uint32_t gicr_read_ctlr(uintptr_t base) 309 { 310 return mmio_read_32(base + GICR_CTLR); 311 } 312 313 static inline void gicr_write_ctlr(uintptr_t base, uint32_t val) 314 { 315 mmio_write_32(base + GICR_CTLR, val); 316 } 317 318 static inline uint64_t gicr_read_typer(uintptr_t base) 319 { 320 return mmio_read_64(base + GICR_TYPER); 321 } 322 323 static inline uint32_t gicr_read_waker(uintptr_t base) 324 { 325 return mmio_read_32(base + GICR_WAKER); 326 } 327 328 static inline void gicr_write_waker(uintptr_t base, uint32_t val) 329 { 330 mmio_write_32(base + GICR_WAKER, val); 331 } 332 333 /* 334 * Wait for updates to: 335 * GICR_ICENABLER0 336 * GICR_CTLR.DPG1S 337 * GICR_CTLR.DPG1NS 338 * GICR_CTLR.DPG0 339 * GICR_CTLR, which clears EnableLPIs from 1 to 0 340 */ 341 static inline void gicr_wait_for_pending_write(uintptr_t gicr_base) 342 { 343 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) { 344 } 345 } 346 347 static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base) 348 { 349 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U) { 350 } 351 } 352 353 /* Private implementation of Distributor power control hooks */ 354 void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num); 355 void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num); 356 357 /******************************************************************************* 358 * GIC Redistributor functions for accessing entire registers. 359 * Note: The raw register values correspond to multiple interrupt IDs and 360 * the number of interrupt IDs involved depends on the register accessed. 361 ******************************************************************************/ 362 363 /* 364 * Accessors to read/write GIC Redistributor ICENABLER0 register 365 */ 366 static inline unsigned int gicr_read_icenabler0(uintptr_t base) 367 { 368 return mmio_read_32(base + GICR_ICENABLER0); 369 } 370 371 static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val) 372 { 373 mmio_write_32(base + GICR_ICENABLER0, val); 374 } 375 376 /* 377 * Accessors to read/write GIC Redistributor ICENABLER0 and ICENABLERE 378 * register corresponding to its number 379 */ 380 static inline unsigned int gicr_read_icenabler(uintptr_t base, 381 unsigned int reg_num) 382 { 383 return mmio_read_32(base + GICR_ICENABLER + (reg_num << 2)); 384 } 385 386 static inline void gicr_write_icenabler(uintptr_t base, unsigned int reg_num, 387 unsigned int val) 388 { 389 mmio_write_32(base + GICR_ICENABLER + (reg_num << 2), val); 390 } 391 392 /* 393 * Accessors to read/write GIC Redistributor ICFGR0, ICFGR1 registers 394 */ 395 static inline unsigned int gicr_read_icfgr0(uintptr_t base) 396 { 397 return mmio_read_32(base + GICR_ICFGR0); 398 } 399 400 static inline unsigned int gicr_read_icfgr1(uintptr_t base) 401 { 402 return mmio_read_32(base + GICR_ICFGR1); 403 } 404 405 static inline void gicr_write_icfgr0(uintptr_t base, unsigned int val) 406 { 407 mmio_write_32(base + GICR_ICFGR0, val); 408 } 409 410 static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val) 411 { 412 mmio_write_32(base + GICR_ICFGR1, val); 413 } 414 415 /* 416 * Accessors to read/write GIC Redistributor ICFGR0, ICFGR1 and ICFGRE 417 * register corresponding to its number 418 */ 419 static inline unsigned int gicr_read_icfgr(uintptr_t base, unsigned int reg_num) 420 { 421 return mmio_read_32(base + GICR_ICFGR + (reg_num << 2)); 422 } 423 424 static inline void gicr_write_icfgr(uintptr_t base, unsigned int reg_num, 425 unsigned int val) 426 { 427 mmio_write_32(base + GICR_ICFGR + (reg_num << 2), val); 428 } 429 430 /* 431 * Accessor to write GIC Redistributor ICPENDR0 register 432 */ 433 static inline void gicr_write_icpendr0(uintptr_t base, unsigned int val) 434 { 435 mmio_write_32(base + GICR_ICPENDR0, val); 436 } 437 438 /* 439 * Accessor to write GIC Redistributor ICPENDR0 and ICPENDRE 440 * register corresponding to its number 441 */ 442 static inline void gicr_write_icpendr(uintptr_t base, unsigned int reg_num, 443 unsigned int val) 444 { 445 mmio_write_32(base + GICR_ICPENDR + (reg_num << 2), val); 446 } 447 448 /* 449 * Accessors to read/write GIC Redistributor IGROUPR0 register 450 */ 451 static inline unsigned int gicr_read_igroupr0(uintptr_t base) 452 { 453 return mmio_read_32(base + GICR_IGROUPR0); 454 } 455 456 static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val) 457 { 458 mmio_write_32(base + GICR_IGROUPR0, val); 459 } 460 461 /* 462 * Accessors to read/write GIC Redistributor IGROUPR0 and IGROUPRE 463 * register corresponding to its number 464 */ 465 static inline unsigned int gicr_read_igroupr(uintptr_t base, 466 unsigned int reg_num) 467 { 468 return mmio_read_32(base + GICR_IGROUPR + (reg_num << 2)); 469 } 470 471 static inline void gicr_write_igroupr(uintptr_t base, unsigned int reg_num, 472 unsigned int val) 473 { 474 mmio_write_32(base + GICR_IGROUPR + (reg_num << 2), val); 475 } 476 477 /* 478 * Accessors to read/write GIC Redistributor IGRPMODR0 register 479 */ 480 static inline unsigned int gicr_read_igrpmodr0(uintptr_t base) 481 { 482 return mmio_read_32(base + GICR_IGRPMODR0); 483 } 484 485 static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val) 486 { 487 mmio_write_32(base + GICR_IGRPMODR0, val); 488 } 489 490 /* 491 * Accessors to read/write GIC Redistributor IGRPMODR0 and IGRPMODRE 492 * register corresponding to its number 493 */ 494 static inline unsigned int gicr_read_igrpmodr(uintptr_t base, 495 unsigned int reg_num) 496 { 497 return mmio_read_32(base + GICR_IGRPMODR + (reg_num << 2)); 498 } 499 500 static inline void gicr_write_igrpmodr(uintptr_t base, unsigned int reg_num, 501 unsigned int val) 502 { 503 mmio_write_32(base + GICR_IGRPMODR + (reg_num << 2), val); 504 } 505 506 /* 507 * Accessors to read/write the GIC Redistributor IPRIORITYR(E) register 508 * corresponding to its number, 4 interrupts IDs at a time. 509 */ 510 static inline unsigned int gicr_ipriorityr_read(uintptr_t base, 511 unsigned int reg_num) 512 { 513 return mmio_read_32(base + GICR_IPRIORITYR + (reg_num << 2)); 514 } 515 516 static inline void gicr_ipriorityr_write(uintptr_t base, unsigned int reg_num, 517 unsigned int val) 518 { 519 mmio_write_32(base + GICR_IPRIORITYR + (reg_num << 2), val); 520 } 521 522 /* 523 * Accessors to read/write GIC Redistributor ISACTIVER0 register 524 */ 525 static inline unsigned int gicr_read_isactiver0(uintptr_t base) 526 { 527 return mmio_read_32(base + GICR_ISACTIVER0); 528 } 529 530 static inline void gicr_write_isactiver0(uintptr_t base, unsigned int val) 531 { 532 mmio_write_32(base + GICR_ISACTIVER0, val); 533 } 534 535 /* 536 * Accessors to read/write GIC Redistributor ISACTIVER0 and ISACTIVERE 537 * register corresponding to its number 538 */ 539 static inline unsigned int gicr_read_isactiver(uintptr_t base, 540 unsigned int reg_num) 541 { 542 return mmio_read_32(base + GICR_ISACTIVER + (reg_num << 2)); 543 } 544 545 static inline void gicr_write_isactiver(uintptr_t base, unsigned int reg_num, 546 unsigned int val) 547 { 548 mmio_write_32(base + GICR_ISACTIVER + (reg_num << 2), val); 549 } 550 551 /* 552 * Accessors to read/write GIC Redistributor ISENABLER0 register 553 */ 554 static inline unsigned int gicr_read_isenabler0(uintptr_t base) 555 { 556 return mmio_read_32(base + GICR_ISENABLER0); 557 } 558 559 static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val) 560 { 561 mmio_write_32(base + GICR_ISENABLER0, val); 562 } 563 564 /* 565 * Accessors to read/write GIC Redistributor ISENABLER0 and ISENABLERE 566 * register corresponding to its number 567 */ 568 static inline unsigned int gicr_read_isenabler(uintptr_t base, 569 unsigned int reg_num) 570 { 571 return mmio_read_32(base + GICR_ISENABLER + (reg_num << 2)); 572 } 573 574 static inline void gicr_write_isenabler(uintptr_t base, unsigned int reg_num, 575 unsigned int val) 576 { 577 mmio_write_32(base + GICR_ISENABLER + (reg_num << 2), val); 578 } 579 580 /* 581 * Accessors to read/write GIC Redistributor ISPENDR0 register 582 */ 583 static inline unsigned int gicr_read_ispendr0(uintptr_t base) 584 { 585 return mmio_read_32(base + GICR_ISPENDR0); 586 } 587 588 static inline void gicr_write_ispendr0(uintptr_t base, unsigned int val) 589 { 590 mmio_write_32(base + GICR_ISPENDR0, val); 591 } 592 593 /* 594 * Accessors to read/write GIC Redistributor ISPENDR0 and ISPENDRE 595 * register corresponding to its number 596 */ 597 static inline unsigned int gicr_read_ispendr(uintptr_t base, 598 unsigned int reg_num) 599 { 600 return mmio_read_32(base + GICR_ISPENDR + (reg_num << 2)); 601 } 602 603 static inline void gicr_write_ispendr(uintptr_t base, unsigned int reg_num, 604 unsigned int val) 605 { 606 mmio_write_32(base + GICR_ISPENDR + (reg_num << 2), val); 607 } 608 609 /* 610 * Accessors to read/write GIC Redistributor NSACR register 611 */ 612 static inline unsigned int gicr_read_nsacr(uintptr_t base) 613 { 614 return mmio_read_32(base + GICR_NSACR); 615 } 616 617 static inline void gicr_write_nsacr(uintptr_t base, unsigned int val) 618 { 619 mmio_write_32(base + GICR_NSACR, val); 620 } 621 622 /* 623 * Accessors to read/write GIC Redistributor PROPBASER register 624 */ 625 static inline uint64_t gicr_read_propbaser(uintptr_t base) 626 { 627 return mmio_read_64(base + GICR_PROPBASER); 628 } 629 630 static inline void gicr_write_propbaser(uintptr_t base, uint64_t val) 631 { 632 mmio_write_64(base + GICR_PROPBASER, val); 633 } 634 635 /* 636 * Accessors to read/write GIC Redistributor PENDBASER register 637 */ 638 static inline uint64_t gicr_read_pendbaser(uintptr_t base) 639 { 640 return mmio_read_64(base + GICR_PENDBASER); 641 } 642 643 static inline void gicr_write_pendbaser(uintptr_t base, uint64_t val) 644 { 645 mmio_write_64(base + GICR_PENDBASER, val); 646 } 647 648 /******************************************************************************* 649 * GIC ITS functions to read and write entire ITS registers. 650 ******************************************************************************/ 651 static inline uint32_t gits_read_ctlr(uintptr_t base) 652 { 653 return mmio_read_32(base + GITS_CTLR); 654 } 655 656 static inline void gits_write_ctlr(uintptr_t base, uint32_t val) 657 { 658 mmio_write_32(base + GITS_CTLR, val); 659 } 660 661 static inline uint64_t gits_read_cbaser(uintptr_t base) 662 { 663 return mmio_read_64(base + GITS_CBASER); 664 } 665 666 static inline void gits_write_cbaser(uintptr_t base, uint64_t val) 667 { 668 mmio_write_64(base + GITS_CBASER, val); 669 } 670 671 static inline uint64_t gits_read_cwriter(uintptr_t base) 672 { 673 return mmio_read_64(base + GITS_CWRITER); 674 } 675 676 static inline void gits_write_cwriter(uintptr_t base, uint64_t val) 677 { 678 mmio_write_64(base + GITS_CWRITER, val); 679 } 680 681 static inline uint64_t gits_read_baser(uintptr_t base, 682 unsigned int its_table_id) 683 { 684 assert(its_table_id < 8U); 685 return mmio_read_64(base + GITS_BASER + (8U * its_table_id)); 686 } 687 688 static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id, 689 uint64_t val) 690 { 691 assert(its_table_id < 8U); 692 mmio_write_64(base + GITS_BASER + (8U * its_table_id), val); 693 } 694 695 /* 696 * Wait for Quiescent bit when GIC ITS is disabled 697 */ 698 static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base) 699 { 700 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 701 while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0U) { 702 } 703 } 704 705 #endif /* GICV3_PRIVATE_H */ 706