1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GICV3_PRIVATE_H__ 8 #define __GICV3_PRIVATE_H__ 9 10 #include <gic_common.h> 11 #include <gicv3.h> 12 #include <mmio.h> 13 #include <stdint.h> 14 #include "../common/gic_common_private.h" 15 16 /******************************************************************************* 17 * GICv3 private macro definitions 18 ******************************************************************************/ 19 20 /* Constants to indicate the status of the RWP bit */ 21 #define RWP_TRUE 1 22 #define RWP_FALSE 0 23 24 /* 25 * Macro to convert an mpidr to a value suitable for programming into a 26 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant 27 * to GICv3. 28 */ 29 #define gicd_irouter_val_from_mpidr(mpidr, irm) \ 30 ((mpidr & ~(0xff << 24)) | \ 31 (irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT) 32 33 /* 34 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] 35 * are zeroes. 36 */ 37 #ifdef AARCH32 38 #define mpidr_from_gicr_typer(typer_val) (((typer_val) >> 32) & 0xffffff) 39 #else 40 #define mpidr_from_gicr_typer(typer_val) \ 41 (((((typer_val) >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \ 42 (((typer_val) >> 32) & 0xffffff)) 43 #endif 44 45 /******************************************************************************* 46 * Private GICv3 function prototypes for accessing entire registers. 47 * Note: The raw register values correspond to multiple interrupt IDs and 48 * the number of interrupt IDs involved depends on the register accessed. 49 ******************************************************************************/ 50 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id); 51 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id); 52 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); 53 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); 54 55 /******************************************************************************* 56 * Private GICv3 function prototypes for accessing the GIC registers 57 * corresponding to a single interrupt ID. These functions use bitwise 58 * operations or appropriate register accesses to modify or return 59 * the bit-field corresponding the single interrupt ID. 60 ******************************************************************************/ 61 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id); 62 unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id); 63 unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id); 64 void gicd_set_igrpmodr(uintptr_t base, unsigned int id); 65 void gicr_set_igrpmodr0(uintptr_t base, unsigned int id); 66 void gicr_set_isenabler0(uintptr_t base, unsigned int id); 67 void gicr_set_igroupr0(uintptr_t base, unsigned int id); 68 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id); 69 void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id); 70 void gicr_clr_igroupr0(uintptr_t base, unsigned int id); 71 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); 72 73 /******************************************************************************* 74 * Private GICv3 helper function prototypes 75 ******************************************************************************/ 76 void gicv3_spis_configure_defaults(uintptr_t gicd_base); 77 void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base); 78 void gicv3_secure_spis_configure(uintptr_t gicd_base, 79 unsigned int num_ints, 80 const unsigned int *sec_intr_list, 81 unsigned int int_grp); 82 void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base, 83 unsigned int num_ints, 84 const unsigned int *sec_intr_list, 85 unsigned int int_grp); 86 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 87 unsigned int rdistif_num, 88 uintptr_t gicr_base, 89 mpidr_hash_fn mpidr_to_core_pos); 90 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base); 91 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base); 92 93 /******************************************************************************* 94 * GIC Distributor interface accessors 95 ******************************************************************************/ 96 /* 97 * Wait for updates to : 98 * GICD_CTLR[2:0] - the Group Enables 99 * GICD_CTLR[5:4] - the ARE bits 100 * GICD_ICENABLERn - the clearing of enable state for SPIs 101 */ 102 static inline void gicd_wait_for_pending_write(uintptr_t gicd_base) 103 { 104 while (gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) 105 ; 106 } 107 108 static inline unsigned int gicd_read_pidr2(uintptr_t base) 109 { 110 return mmio_read_32(base + GICD_PIDR2_GICV3); 111 } 112 113 static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id) 114 { 115 assert(id >= MIN_SPI_ID); 116 return mmio_read_64(base + GICD_IROUTER + (id << 3)); 117 } 118 119 static inline void gicd_write_irouter(uintptr_t base, 120 unsigned int id, 121 unsigned long long affinity) 122 { 123 assert(id >= MIN_SPI_ID); 124 mmio_write_64(base + GICD_IROUTER + (id << 3), affinity); 125 } 126 127 static inline void gicd_clr_ctlr(uintptr_t base, 128 unsigned int bitmap, 129 unsigned int rwp) 130 { 131 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap); 132 if (rwp) 133 gicd_wait_for_pending_write(base); 134 } 135 136 static inline void gicd_set_ctlr(uintptr_t base, 137 unsigned int bitmap, 138 unsigned int rwp) 139 { 140 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap); 141 if (rwp) 142 gicd_wait_for_pending_write(base); 143 } 144 145 /******************************************************************************* 146 * GIC Redistributor interface accessors 147 ******************************************************************************/ 148 static inline unsigned long long gicr_read_ctlr(uintptr_t base) 149 { 150 return mmio_read_64(base + GICR_CTLR); 151 } 152 153 static inline unsigned long long gicr_read_typer(uintptr_t base) 154 { 155 return mmio_read_64(base + GICR_TYPER); 156 } 157 158 static inline unsigned int gicr_read_waker(uintptr_t base) 159 { 160 return mmio_read_32(base + GICR_WAKER); 161 } 162 163 static inline void gicr_write_waker(uintptr_t base, unsigned int val) 164 { 165 mmio_write_32(base + GICR_WAKER, val); 166 } 167 168 /* 169 * Wait for updates to : 170 * GICR_ICENABLER0 171 * GICR_CTLR.DPG1S 172 * GICR_CTLR.DPG1NS 173 * GICR_CTLR.DPG0 174 */ 175 static inline void gicr_wait_for_pending_write(uintptr_t gicr_base) 176 { 177 while (gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) 178 ; 179 } 180 181 /******************************************************************************* 182 * GIC Re-distributor functions for accessing entire registers. 183 * Note: The raw register values correspond to multiple interrupt IDs and 184 * the number of interrupt IDs involved depends on the register accessed. 185 ******************************************************************************/ 186 static inline unsigned int gicr_read_icenabler0(uintptr_t base) 187 { 188 return mmio_read_32(base + GICR_ICENABLER0); 189 } 190 191 static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val) 192 { 193 mmio_write_32(base + GICR_ICENABLER0, val); 194 } 195 196 static inline unsigned int gicr_read_isenabler0(uintptr_t base) 197 { 198 return mmio_read_32(base + GICR_ISENABLER0); 199 } 200 201 static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val) 202 { 203 mmio_write_32(base + GICR_ISENABLER0, val); 204 } 205 206 static inline unsigned int gicr_read_igroupr0(uintptr_t base) 207 { 208 return mmio_read_32(base + GICR_IGROUPR0); 209 } 210 211 static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val) 212 { 213 mmio_write_32(base + GICR_IGROUPR0, val); 214 } 215 216 static inline unsigned int gicr_read_igrpmodr0(uintptr_t base) 217 { 218 return mmio_read_32(base + GICR_IGRPMODR0); 219 } 220 221 static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val) 222 { 223 mmio_write_32(base + GICR_IGRPMODR0, val); 224 } 225 226 static inline unsigned int gicr_read_icfgr1(uintptr_t base) 227 { 228 return mmio_read_32(base + GICR_ICFGR1); 229 } 230 231 static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val) 232 { 233 mmio_write_32(base + GICR_ICFGR1, val); 234 } 235 236 #endif /* __GICV3_PRIVATE_H__ */ 237