1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef GICV3_PRIVATE_H 9 #define GICV3_PRIVATE_H 10 11 #include <assert.h> 12 #include <stdint.h> 13 14 #include <drivers/arm/gic_common.h> 15 #include <drivers/arm/gicv3.h> 16 #include <lib/mmio.h> 17 18 #include "../common/gic_common_private.h" 19 20 /******************************************************************************* 21 * GICv3 private macro definitions 22 ******************************************************************************/ 23 24 /* Constants to indicate the status of the RWP bit */ 25 #define RWP_TRUE U(1) 26 #define RWP_FALSE U(0) 27 28 /* Calculate GIC register bit number corresponding to its interrupt ID */ 29 #define BIT_NUM(REG, id) \ 30 ((id) & ((1U << REG##R_SHIFT) - 1U)) 31 32 /* 33 * Calculate 8, 32 and 64-bit GICD register offset 34 * corresponding to its interrupt ID 35 */ 36 #if GIC_EXT_INTID 37 /* GICv3.1 */ 38 #define GICD_OFFSET_8(REG, id) \ 39 (((id) <= MAX_SPI_ID) ? \ 40 GICD_##REG##R + (uintptr_t)(id) : \ 41 GICD_##REG##RE + (uintptr_t)(id) - MIN_ESPI_ID) 42 43 #define GICD_OFFSET(REG, id) \ 44 (((id) <= MAX_SPI_ID) ? \ 45 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \ 46 GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \ 47 REG##R_SHIFT) << 2)) 48 49 #define GICD_OFFSET_64(REG, id) \ 50 (((id) <= MAX_SPI_ID) ? \ 51 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) : \ 52 GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \ 53 REG##R_SHIFT) << 3)) 54 55 #else /* GICv3 */ 56 #define GICD_OFFSET_8(REG, id) \ 57 (GICD_##REG##R + (uintptr_t)(id)) 58 59 #define GICD_OFFSET(REG, id) \ 60 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2)) 61 62 #define GICD_OFFSET_64(REG, id) \ 63 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3)) 64 #endif /* GIC_EXT_INTID */ 65 66 /* 67 * Read/Write 8, 32 and 64-bit GIC Distributor register 68 * corresponding to its interrupt ID 69 */ 70 #define GICD_READ(REG, base, id) \ 71 mmio_read_32((base) + GICD_OFFSET(REG, (id))) 72 73 #define GICD_READ_64(REG, base, id) \ 74 mmio_read_64((base) + GICD_OFFSET_64(REG, (id))) 75 76 #define GICD_WRITE_8(REG, base, id, val) \ 77 mmio_write_8((base) + GICD_OFFSET_8(REG, (id)), (val)) 78 79 #define GICD_WRITE(REG, base, id, val) \ 80 mmio_write_32((base) + GICD_OFFSET(REG, (id)), (val)) 81 82 #define GICD_WRITE_64(REG, base, id, val) \ 83 mmio_write_64((base) + GICD_OFFSET_64(REG, (id)), (val)) 84 85 /* 86 * Bit operations on GIC Distributor register corresponding 87 * to its interrupt ID 88 */ 89 /* Get bit in GIC Distributor register */ 90 #define GICD_GET_BIT(REG, base, id) \ 91 ((mmio_read_32((base) + GICD_OFFSET(REG, (id))) >> \ 92 BIT_NUM(REG, (id))) & 1U) 93 94 /* Set bit in GIC Distributor register */ 95 #define GICD_SET_BIT(REG, base, id) \ 96 mmio_setbits_32((base) + GICD_OFFSET(REG, (id)), \ 97 ((uint32_t)1 << BIT_NUM(REG, (id)))) 98 99 /* Clear bit in GIC Distributor register */ 100 #define GICD_CLR_BIT(REG, base, id) \ 101 mmio_clrbits_32((base) + GICD_OFFSET(REG, (id)), \ 102 ((uint32_t)1 << BIT_NUM(REG, (id)))) 103 104 /* Write bit in GIC Distributor register */ 105 #define GICD_WRITE_BIT(REG, base, id) \ 106 mmio_write_32((base) + GICD_OFFSET(REG, (id)), \ 107 ((uint32_t)1 << BIT_NUM(REG, (id)))) 108 109 /* 110 * Calculate 8 and 32-bit GICR register offset 111 * corresponding to its interrupt ID 112 */ 113 #if GIC_EXT_INTID 114 /* GICv3.1 */ 115 #define GICR_OFFSET_8(REG, id) \ 116 (((id) <= MAX_PPI_ID) ? \ 117 GICR_##REG##R + (uintptr_t)(id) : \ 118 GICR_##REG##R + (uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID)) 119 120 #define GICR_OFFSET(REG, id) \ 121 (((id) <= MAX_PPI_ID) ? \ 122 GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \ 123 GICR_##REG##R + ((((uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID))\ 124 >> REG##R_SHIFT) << 2)) 125 #else /* GICv3 */ 126 #define GICR_OFFSET_8(REG, id) \ 127 (GICR_##REG##R + (uintptr_t)(id)) 128 129 #define GICR_OFFSET(REG, id) \ 130 (GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2)) 131 #endif /* GIC_EXT_INTID */ 132 133 /* Read/Write GIC Redistributor register corresponding to its interrupt ID */ 134 #define GICR_READ(REG, base, id) \ 135 mmio_read_32((base) + GICR_OFFSET(REG, (id))) 136 137 #define GICR_WRITE_8(REG, base, id, val) \ 138 mmio_write_8((base) + GICR_OFFSET_8(REG, (id)), (val)) 139 140 #define GICR_WRITE(REG, base, id, val) \ 141 mmio_write_32((base) + GICR_OFFSET(REG, (id)), (val)) 142 143 /* 144 * Bit operations on GIC Redistributor register 145 * corresponding to its interrupt ID 146 */ 147 /* Get bit in GIC Redistributor register */ 148 #define GICR_GET_BIT(REG, base, id) \ 149 ((mmio_read_32((base) + GICR_OFFSET(REG, (id))) >> \ 150 BIT_NUM(REG, (id))) & 1U) 151 152 /* Write bit in GIC Redistributor register */ 153 #define GICR_WRITE_BIT(REG, base, id) \ 154 mmio_write_32((base) + GICR_OFFSET(REG, (id)), \ 155 ((uint32_t)1 << BIT_NUM(REG, (id)))) 156 157 /* Set bit in GIC Redistributor register */ 158 #define GICR_SET_BIT(REG, base, id) \ 159 mmio_setbits_32((base) + GICR_OFFSET(REG, (id)), \ 160 ((uint32_t)1 << BIT_NUM(REG, (id)))) 161 162 /* Clear bit in GIC Redistributor register */ 163 #define GICR_CLR_BIT(REG, base, id) \ 164 mmio_clrbits_32((base) + GICR_OFFSET(REG, (id)), \ 165 ((uint32_t)1 << BIT_NUM(REG, (id)))) 166 167 /* 168 * Macro to convert an mpidr to a value suitable for programming into a 169 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant 170 * to GICv3. 171 */ 172 static inline u_register_t gicd_irouter_val_from_mpidr(u_register_t mpidr, 173 unsigned int irm) 174 { 175 return (mpidr & MPIDR_AFFINITY_MASK) | 176 ((irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT); 177 } 178 179 /* 180 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] 181 * are zeroes. 182 */ 183 #ifdef __aarch64__ 184 static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) 185 { 186 return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | 187 ((typer_val >> 32) & U(0xffffff)); 188 } 189 #else 190 static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) 191 { 192 return (((typer_val) >> 32) & U(0xffffff)); 193 } 194 #endif 195 196 /******************************************************************************* 197 * GICv3 private global variables declarations 198 ******************************************************************************/ 199 extern const gicv3_driver_data_t *gicv3_driver_data; 200 201 /******************************************************************************* 202 * Private GICv3 function prototypes for accessing entire registers. 203 * Note: The raw register values correspond to multiple interrupt IDs and 204 * the number of interrupt IDs involved depends on the register accessed. 205 ******************************************************************************/ 206 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id); 207 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id); 208 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); 209 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); 210 211 /******************************************************************************* 212 * Private GICv3 function prototypes for accessing the GIC registers 213 * corresponding to a single interrupt ID. These functions use bitwise 214 * operations or appropriate register accesses to modify or return 215 * the bit-field corresponding the single interrupt ID. 216 ******************************************************************************/ 217 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id); 218 unsigned int gicr_get_igrpmodr(uintptr_t base, unsigned int id); 219 unsigned int gicr_get_igroupr(uintptr_t base, unsigned int id); 220 unsigned int gicr_get_isactiver(uintptr_t base, unsigned int id); 221 void gicd_set_igrpmodr(uintptr_t base, unsigned int id); 222 void gicr_set_igrpmodr(uintptr_t base, unsigned int id); 223 void gicr_set_isenabler(uintptr_t base, unsigned int id); 224 void gicr_set_icenabler(uintptr_t base, unsigned int id); 225 void gicr_set_ispendr(uintptr_t base, unsigned int id); 226 void gicr_set_icpendr(uintptr_t base, unsigned int id); 227 void gicr_set_igroupr(uintptr_t base, unsigned int id); 228 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id); 229 void gicr_clr_igrpmodr(uintptr_t base, unsigned int id); 230 void gicr_clr_igroupr(uintptr_t base, unsigned int id); 231 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); 232 void gicr_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg); 233 234 /******************************************************************************* 235 * Private GICv3 helper function prototypes 236 ******************************************************************************/ 237 uintptr_t gicv3_get_multichip_base(uint32_t spi_id, uintptr_t gicd_base); 238 unsigned int gicv3_get_spi_limit(uintptr_t gicd_base); 239 unsigned int gicv3_get_espi_limit(uintptr_t gicd_base); 240 void gicv3_spis_config_defaults(uintptr_t gicd_base); 241 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base); 242 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, 243 const interrupt_prop_t *interrupt_props, 244 unsigned int interrupt_props_num); 245 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, 246 const interrupt_prop_t *interrupt_props, 247 unsigned int interrupt_props_num); 248 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 249 unsigned int rdistif_num, 250 uintptr_t gicr_base, 251 mpidr_hash_fn mpidr_to_core_pos); 252 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base); 253 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base); 254 255 /******************************************************************************* 256 * GIC Distributor interface accessors 257 ******************************************************************************/ 258 /* 259 * Wait for updates to: 260 * GICD_CTLR[2:0] - the Group Enables 261 * GICD_CTLR[7:4] - the ARE bits, E1NWF bit and DS bit 262 * GICD_ICENABLER<n> - the clearing of enable state for SPIs 263 */ 264 static inline void gicd_wait_for_pending_write(uintptr_t gicd_base) 265 { 266 while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U) { 267 } 268 } 269 270 static inline uint32_t gicd_read_pidr2(uintptr_t base) 271 { 272 return mmio_read_32(base + GICD_PIDR2_GICV3); 273 } 274 275 static inline uint64_t gicd_read_irouter(uintptr_t base, unsigned int id) 276 { 277 assert(id >= MIN_SPI_ID); 278 return GICD_READ_64(IROUTE, base, id); 279 } 280 281 static inline void gicd_write_irouter(uintptr_t base, 282 unsigned int id, 283 uint64_t affinity) 284 { 285 assert(id >= MIN_SPI_ID); 286 GICD_WRITE_64(IROUTE, base, id, affinity); 287 } 288 289 static inline void gicd_clr_ctlr(uintptr_t base, 290 unsigned int bitmap, 291 unsigned int rwp) 292 { 293 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap); 294 if (rwp != 0U) { 295 gicd_wait_for_pending_write(base); 296 } 297 } 298 299 static inline void gicd_set_ctlr(uintptr_t base, 300 unsigned int bitmap, 301 unsigned int rwp) 302 { 303 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap); 304 if (rwp != 0U) { 305 gicd_wait_for_pending_write(base); 306 } 307 } 308 309 /******************************************************************************* 310 * GIC Redistributor interface accessors 311 ******************************************************************************/ 312 static inline uint32_t gicr_read_ctlr(uintptr_t base) 313 { 314 return mmio_read_32(base + GICR_CTLR); 315 } 316 317 static inline void gicr_write_ctlr(uintptr_t base, uint32_t val) 318 { 319 mmio_write_32(base + GICR_CTLR, val); 320 } 321 322 static inline uint64_t gicr_read_typer(uintptr_t base) 323 { 324 return mmio_read_64(base + GICR_TYPER); 325 } 326 327 static inline uint32_t gicr_read_waker(uintptr_t base) 328 { 329 return mmio_read_32(base + GICR_WAKER); 330 } 331 332 static inline void gicr_write_waker(uintptr_t base, uint32_t val) 333 { 334 mmio_write_32(base + GICR_WAKER, val); 335 } 336 337 /* 338 * Wait for updates to: 339 * GICR_ICENABLER0 340 * GICR_CTLR.DPG1S 341 * GICR_CTLR.DPG1NS 342 * GICR_CTLR.DPG0 343 * GICR_CTLR, which clears EnableLPIs from 1 to 0 344 */ 345 static inline void gicr_wait_for_pending_write(uintptr_t gicr_base) 346 { 347 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) { 348 } 349 } 350 351 static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base) 352 { 353 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U) { 354 } 355 } 356 357 /* Private implementation of Distributor power control hooks */ 358 void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num); 359 void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num); 360 361 /******************************************************************************* 362 * GIC Redistributor functions for accessing entire registers. 363 * Note: The raw register values correspond to multiple interrupt IDs and 364 * the number of interrupt IDs involved depends on the register accessed. 365 ******************************************************************************/ 366 367 /* 368 * Accessors to read/write GIC Redistributor ICENABLER0 register 369 */ 370 static inline unsigned int gicr_read_icenabler0(uintptr_t base) 371 { 372 return mmio_read_32(base + GICR_ICENABLER0); 373 } 374 375 static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val) 376 { 377 mmio_write_32(base + GICR_ICENABLER0, val); 378 } 379 380 /* 381 * Accessors to read/write GIC Redistributor ICENABLER0 and ICENABLERE 382 * register corresponding to its number 383 */ 384 static inline unsigned int gicr_read_icenabler(uintptr_t base, 385 unsigned int reg_num) 386 { 387 return mmio_read_32(base + GICR_ICENABLER + (reg_num << 2)); 388 } 389 390 static inline void gicr_write_icenabler(uintptr_t base, unsigned int reg_num, 391 unsigned int val) 392 { 393 mmio_write_32(base + GICR_ICENABLER + (reg_num << 2), val); 394 } 395 396 /* 397 * Accessors to read/write GIC Redistributor ICFGR0, ICFGR1 registers 398 */ 399 static inline unsigned int gicr_read_icfgr0(uintptr_t base) 400 { 401 return mmio_read_32(base + GICR_ICFGR0); 402 } 403 404 static inline unsigned int gicr_read_icfgr1(uintptr_t base) 405 { 406 return mmio_read_32(base + GICR_ICFGR1); 407 } 408 409 static inline void gicr_write_icfgr0(uintptr_t base, unsigned int val) 410 { 411 mmio_write_32(base + GICR_ICFGR0, val); 412 } 413 414 static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val) 415 { 416 mmio_write_32(base + GICR_ICFGR1, val); 417 } 418 419 /* 420 * Accessors to read/write GIC Redistributor ICFGR0, ICFGR1 and ICFGRE 421 * register corresponding to its number 422 */ 423 static inline unsigned int gicr_read_icfgr(uintptr_t base, unsigned int reg_num) 424 { 425 return mmio_read_32(base + GICR_ICFGR + (reg_num << 2)); 426 } 427 428 static inline void gicr_write_icfgr(uintptr_t base, unsigned int reg_num, 429 unsigned int val) 430 { 431 mmio_write_32(base + GICR_ICFGR + (reg_num << 2), val); 432 } 433 434 /* 435 * Accessor to write GIC Redistributor ICPENDR0 register 436 */ 437 static inline void gicr_write_icpendr0(uintptr_t base, unsigned int val) 438 { 439 mmio_write_32(base + GICR_ICPENDR0, val); 440 } 441 442 /* 443 * Accessor to write GIC Redistributor ICPENDR0 and ICPENDRE 444 * register corresponding to its number 445 */ 446 static inline void gicr_write_icpendr(uintptr_t base, unsigned int reg_num, 447 unsigned int val) 448 { 449 mmio_write_32(base + GICR_ICPENDR + (reg_num << 2), val); 450 } 451 452 /* 453 * Accessors to read/write GIC Redistributor IGROUPR0 register 454 */ 455 static inline unsigned int gicr_read_igroupr0(uintptr_t base) 456 { 457 return mmio_read_32(base + GICR_IGROUPR0); 458 } 459 460 static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val) 461 { 462 mmio_write_32(base + GICR_IGROUPR0, val); 463 } 464 465 /* 466 * Accessors to read/write GIC Redistributor IGROUPR0 and IGROUPRE 467 * register corresponding to its number 468 */ 469 static inline unsigned int gicr_read_igroupr(uintptr_t base, 470 unsigned int reg_num) 471 { 472 return mmio_read_32(base + GICR_IGROUPR + (reg_num << 2)); 473 } 474 475 static inline void gicr_write_igroupr(uintptr_t base, unsigned int reg_num, 476 unsigned int val) 477 { 478 mmio_write_32(base + GICR_IGROUPR + (reg_num << 2), val); 479 } 480 481 /* 482 * Accessors to read/write GIC Redistributor IGRPMODR0 register 483 */ 484 static inline unsigned int gicr_read_igrpmodr0(uintptr_t base) 485 { 486 return mmio_read_32(base + GICR_IGRPMODR0); 487 } 488 489 static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val) 490 { 491 mmio_write_32(base + GICR_IGRPMODR0, val); 492 } 493 494 /* 495 * Accessors to read/write GIC Redistributor IGRPMODR0 and IGRPMODRE 496 * register corresponding to its number 497 */ 498 static inline unsigned int gicr_read_igrpmodr(uintptr_t base, 499 unsigned int reg_num) 500 { 501 return mmio_read_32(base + GICR_IGRPMODR + (reg_num << 2)); 502 } 503 504 static inline void gicr_write_igrpmodr(uintptr_t base, unsigned int reg_num, 505 unsigned int val) 506 { 507 mmio_write_32(base + GICR_IGRPMODR + (reg_num << 2), val); 508 } 509 510 /* 511 * Accessors to read/write the GIC Redistributor IPRIORITYR(E) register 512 * corresponding to its number, 4 interrupts IDs at a time. 513 */ 514 static inline unsigned int gicr_ipriorityr_read(uintptr_t base, 515 unsigned int reg_num) 516 { 517 return mmio_read_32(base + GICR_IPRIORITYR + (reg_num << 2)); 518 } 519 520 static inline void gicr_ipriorityr_write(uintptr_t base, unsigned int reg_num, 521 unsigned int val) 522 { 523 mmio_write_32(base + GICR_IPRIORITYR + (reg_num << 2), val); 524 } 525 526 /* 527 * Accessors to read/write GIC Redistributor ISACTIVER0 register 528 */ 529 static inline unsigned int gicr_read_isactiver0(uintptr_t base) 530 { 531 return mmio_read_32(base + GICR_ISACTIVER0); 532 } 533 534 static inline void gicr_write_isactiver0(uintptr_t base, unsigned int val) 535 { 536 mmio_write_32(base + GICR_ISACTIVER0, val); 537 } 538 539 /* 540 * Accessors to read/write GIC Redistributor ISACTIVER0 and ISACTIVERE 541 * register corresponding to its number 542 */ 543 static inline unsigned int gicr_read_isactiver(uintptr_t base, 544 unsigned int reg_num) 545 { 546 return mmio_read_32(base + GICR_ISACTIVER + (reg_num << 2)); 547 } 548 549 static inline void gicr_write_isactiver(uintptr_t base, unsigned int reg_num, 550 unsigned int val) 551 { 552 mmio_write_32(base + GICR_ISACTIVER + (reg_num << 2), val); 553 } 554 555 /* 556 * Accessors to read/write GIC Redistributor ISENABLER0 register 557 */ 558 static inline unsigned int gicr_read_isenabler0(uintptr_t base) 559 { 560 return mmio_read_32(base + GICR_ISENABLER0); 561 } 562 563 static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val) 564 { 565 mmio_write_32(base + GICR_ISENABLER0, val); 566 } 567 568 /* 569 * Accessors to read/write GIC Redistributor ISENABLER0 and ISENABLERE 570 * register corresponding to its number 571 */ 572 static inline unsigned int gicr_read_isenabler(uintptr_t base, 573 unsigned int reg_num) 574 { 575 return mmio_read_32(base + GICR_ISENABLER + (reg_num << 2)); 576 } 577 578 static inline void gicr_write_isenabler(uintptr_t base, unsigned int reg_num, 579 unsigned int val) 580 { 581 mmio_write_32(base + GICR_ISENABLER + (reg_num << 2), val); 582 } 583 584 /* 585 * Accessors to read/write GIC Redistributor ISPENDR0 register 586 */ 587 static inline unsigned int gicr_read_ispendr0(uintptr_t base) 588 { 589 return mmio_read_32(base + GICR_ISPENDR0); 590 } 591 592 static inline void gicr_write_ispendr0(uintptr_t base, unsigned int val) 593 { 594 mmio_write_32(base + GICR_ISPENDR0, val); 595 } 596 597 /* 598 * Accessors to read/write GIC Redistributor ISPENDR0 and ISPENDRE 599 * register corresponding to its number 600 */ 601 static inline unsigned int gicr_read_ispendr(uintptr_t base, 602 unsigned int reg_num) 603 { 604 return mmio_read_32(base + GICR_ISPENDR + (reg_num << 2)); 605 } 606 607 static inline void gicr_write_ispendr(uintptr_t base, unsigned int reg_num, 608 unsigned int val) 609 { 610 mmio_write_32(base + GICR_ISPENDR + (reg_num << 2), val); 611 } 612 613 /* 614 * Accessors to read/write GIC Redistributor NSACR register 615 */ 616 static inline unsigned int gicr_read_nsacr(uintptr_t base) 617 { 618 return mmio_read_32(base + GICR_NSACR); 619 } 620 621 static inline void gicr_write_nsacr(uintptr_t base, unsigned int val) 622 { 623 mmio_write_32(base + GICR_NSACR, val); 624 } 625 626 /* 627 * Accessors to read/write GIC Redistributor PROPBASER register 628 */ 629 static inline uint64_t gicr_read_propbaser(uintptr_t base) 630 { 631 return mmio_read_64(base + GICR_PROPBASER); 632 } 633 634 static inline void gicr_write_propbaser(uintptr_t base, uint64_t val) 635 { 636 mmio_write_64(base + GICR_PROPBASER, val); 637 } 638 639 /* 640 * Accessors to read/write GIC Redistributor PENDBASER register 641 */ 642 static inline uint64_t gicr_read_pendbaser(uintptr_t base) 643 { 644 return mmio_read_64(base + GICR_PENDBASER); 645 } 646 647 static inline void gicr_write_pendbaser(uintptr_t base, uint64_t val) 648 { 649 mmio_write_64(base + GICR_PENDBASER, val); 650 } 651 652 /******************************************************************************* 653 * GIC ITS functions to read and write entire ITS registers. 654 ******************************************************************************/ 655 static inline uint32_t gits_read_ctlr(uintptr_t base) 656 { 657 return mmio_read_32(base + GITS_CTLR); 658 } 659 660 static inline void gits_write_ctlr(uintptr_t base, uint32_t val) 661 { 662 mmio_write_32(base + GITS_CTLR, val); 663 } 664 665 static inline uint64_t gits_read_cbaser(uintptr_t base) 666 { 667 return mmio_read_64(base + GITS_CBASER); 668 } 669 670 static inline void gits_write_cbaser(uintptr_t base, uint64_t val) 671 { 672 mmio_write_64(base + GITS_CBASER, val); 673 } 674 675 static inline uint64_t gits_read_cwriter(uintptr_t base) 676 { 677 return mmio_read_64(base + GITS_CWRITER); 678 } 679 680 static inline void gits_write_cwriter(uintptr_t base, uint64_t val) 681 { 682 mmio_write_64(base + GITS_CWRITER, val); 683 } 684 685 static inline uint64_t gits_read_baser(uintptr_t base, 686 unsigned int its_table_id) 687 { 688 assert(its_table_id < 8U); 689 return mmio_read_64(base + GITS_BASER + (8U * its_table_id)); 690 } 691 692 static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id, 693 uint64_t val) 694 { 695 assert(its_table_id < 8U); 696 mmio_write_64(base + GITS_BASER + (8U * its_table_id), val); 697 } 698 699 /* 700 * Wait for Quiescent bit when GIC ITS is disabled 701 */ 702 static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base) 703 { 704 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 705 while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0U) { 706 } 707 } 708 709 #endif /* GICV3_PRIVATE_H */ 710