1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GICV3_PRIVATE_H 8 #define GICV3_PRIVATE_H 9 10 #include <assert.h> 11 #include <stdint.h> 12 13 #include <drivers/arm/gic_common.h> 14 #include <drivers/arm/gicv3.h> 15 #include <lib/mmio.h> 16 17 #include "../common/gic_common_private.h" 18 19 /******************************************************************************* 20 * GICv3 private macro definitions 21 ******************************************************************************/ 22 23 /* Constants to indicate the status of the RWP bit */ 24 #define RWP_TRUE U(1) 25 #define RWP_FALSE U(0) 26 27 /* 28 * Macro to convert an mpidr to a value suitable for programming into a 29 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant 30 * to GICv3. 31 */ 32 static inline u_register_t gicd_irouter_val_from_mpidr(u_register_t mpidr, 33 unsigned int irm) 34 { 35 return (mpidr & ~(U(0xff) << 24)) | 36 ((irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT); 37 } 38 39 /* 40 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] 41 * are zeroes. 42 */ 43 #ifdef __aarch64__ 44 static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) 45 { 46 return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | 47 ((typer_val >> 32) & U(0xffffff)); 48 } 49 #else 50 static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) 51 { 52 return (((typer_val) >> 32) & U(0xffffff)); 53 } 54 #endif 55 56 /******************************************************************************* 57 * GICv3 private global variables declarations 58 ******************************************************************************/ 59 extern const gicv3_driver_data_t *gicv3_driver_data; 60 61 /******************************************************************************* 62 * Private GICv3 function prototypes for accessing entire registers. 63 * Note: The raw register values correspond to multiple interrupt IDs and 64 * the number of interrupt IDs involved depends on the register accessed. 65 ******************************************************************************/ 66 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id); 67 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id); 68 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); 69 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); 70 71 /******************************************************************************* 72 * Private GICv3 function prototypes for accessing the GIC registers 73 * corresponding to a single interrupt ID. These functions use bitwise 74 * operations or appropriate register accesses to modify or return 75 * the bit-field corresponding the single interrupt ID. 76 ******************************************************************************/ 77 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id); 78 unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id); 79 unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id); 80 unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id); 81 void gicd_set_igrpmodr(uintptr_t base, unsigned int id); 82 void gicr_set_igrpmodr0(uintptr_t base, unsigned int id); 83 void gicr_set_isenabler0(uintptr_t base, unsigned int id); 84 void gicr_set_icenabler0(uintptr_t base, unsigned int id); 85 void gicr_set_ispendr0(uintptr_t base, unsigned int id); 86 void gicr_set_icpendr0(uintptr_t base, unsigned int id); 87 void gicr_set_igroupr0(uintptr_t base, unsigned int id); 88 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id); 89 void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id); 90 void gicr_clr_igroupr0(uintptr_t base, unsigned int id); 91 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); 92 void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg); 93 void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg); 94 95 /******************************************************************************* 96 * Private GICv3 helper function prototypes 97 ******************************************************************************/ 98 void gicv3_spis_config_defaults(uintptr_t gicd_base); 99 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base); 100 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, 101 const interrupt_prop_t *interrupt_props, 102 unsigned int interrupt_props_num); 103 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, 104 const interrupt_prop_t *interrupt_props, 105 unsigned int interrupt_props_num); 106 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 107 unsigned int rdistif_num, 108 uintptr_t gicr_base, 109 mpidr_hash_fn mpidr_to_core_pos); 110 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base); 111 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base); 112 113 /******************************************************************************* 114 * GIC Distributor interface accessors 115 ******************************************************************************/ 116 /* 117 * Wait for updates to : 118 * GICD_CTLR[2:0] - the Group Enables 119 * GICD_CTLR[5:4] - the ARE bits 120 * GICD_ICENABLERn - the clearing of enable state for SPIs 121 */ 122 static inline void gicd_wait_for_pending_write(uintptr_t gicd_base) 123 { 124 while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U) 125 ; 126 } 127 128 static inline unsigned int gicd_read_pidr2(uintptr_t base) 129 { 130 return mmio_read_32(base + GICD_PIDR2_GICV3); 131 } 132 133 static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id) 134 { 135 assert(id >= MIN_SPI_ID); 136 return mmio_read_64(base + GICD_IROUTER + (id << 3)); 137 } 138 139 static inline void gicd_write_irouter(uintptr_t base, 140 unsigned int id, 141 unsigned long long affinity) 142 { 143 assert(id >= MIN_SPI_ID); 144 mmio_write_64(base + GICD_IROUTER + (id << 3), affinity); 145 } 146 147 static inline void gicd_clr_ctlr(uintptr_t base, 148 unsigned int bitmap, 149 unsigned int rwp) 150 { 151 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap); 152 if (rwp != 0U) 153 gicd_wait_for_pending_write(base); 154 } 155 156 static inline void gicd_set_ctlr(uintptr_t base, 157 unsigned int bitmap, 158 unsigned int rwp) 159 { 160 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap); 161 if (rwp != 0U) 162 gicd_wait_for_pending_write(base); 163 } 164 165 /******************************************************************************* 166 * GIC Redistributor interface accessors 167 ******************************************************************************/ 168 static inline uint32_t gicr_read_ctlr(uintptr_t base) 169 { 170 return mmio_read_32(base + GICR_CTLR); 171 } 172 173 static inline void gicr_write_ctlr(uintptr_t base, uint32_t val) 174 { 175 mmio_write_32(base + GICR_CTLR, val); 176 } 177 178 static inline unsigned long long gicr_read_typer(uintptr_t base) 179 { 180 return mmio_read_64(base + GICR_TYPER); 181 } 182 183 static inline unsigned int gicr_read_waker(uintptr_t base) 184 { 185 return mmio_read_32(base + GICR_WAKER); 186 } 187 188 static inline void gicr_write_waker(uintptr_t base, unsigned int val) 189 { 190 mmio_write_32(base + GICR_WAKER, val); 191 } 192 193 /* 194 * Wait for updates to : 195 * GICR_ICENABLER0 196 * GICR_CTLR.DPG1S 197 * GICR_CTLR.DPG1NS 198 * GICR_CTLR.DPG0 199 */ 200 static inline void gicr_wait_for_pending_write(uintptr_t gicr_base) 201 { 202 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) 203 ; 204 } 205 206 static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base) 207 { 208 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U) 209 ; 210 } 211 212 /* Private implementation of Distributor power control hooks */ 213 void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num); 214 void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num); 215 216 /******************************************************************************* 217 * GIC Re-distributor functions for accessing entire registers. 218 * Note: The raw register values correspond to multiple interrupt IDs and 219 * the number of interrupt IDs involved depends on the register accessed. 220 ******************************************************************************/ 221 static inline unsigned int gicr_read_icenabler0(uintptr_t base) 222 { 223 return mmio_read_32(base + GICR_ICENABLER0); 224 } 225 226 static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val) 227 { 228 mmio_write_32(base + GICR_ICENABLER0, val); 229 } 230 231 static inline unsigned int gicr_read_isenabler0(uintptr_t base) 232 { 233 return mmio_read_32(base + GICR_ISENABLER0); 234 } 235 236 static inline void gicr_write_icpendr0(uintptr_t base, unsigned int val) 237 { 238 mmio_write_32(base + GICR_ICPENDR0, val); 239 } 240 241 static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val) 242 { 243 mmio_write_32(base + GICR_ISENABLER0, val); 244 } 245 246 static inline unsigned int gicr_read_igroupr0(uintptr_t base) 247 { 248 return mmio_read_32(base + GICR_IGROUPR0); 249 } 250 251 static inline unsigned int gicr_read_ispendr0(uintptr_t base) 252 { 253 return mmio_read_32(base + GICR_ISPENDR0); 254 } 255 256 static inline void gicr_write_ispendr0(uintptr_t base, unsigned int val) 257 { 258 mmio_write_32(base + GICR_ISPENDR0, val); 259 } 260 261 static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val) 262 { 263 mmio_write_32(base + GICR_IGROUPR0, val); 264 } 265 266 static inline unsigned int gicr_read_igrpmodr0(uintptr_t base) 267 { 268 return mmio_read_32(base + GICR_IGRPMODR0); 269 } 270 271 static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val) 272 { 273 mmio_write_32(base + GICR_IGRPMODR0, val); 274 } 275 276 static inline unsigned int gicr_read_nsacr(uintptr_t base) 277 { 278 return mmio_read_32(base + GICR_NSACR); 279 } 280 281 static inline void gicr_write_nsacr(uintptr_t base, unsigned int val) 282 { 283 mmio_write_32(base + GICR_NSACR, val); 284 } 285 286 static inline unsigned int gicr_read_isactiver0(uintptr_t base) 287 { 288 return mmio_read_32(base + GICR_ISACTIVER0); 289 } 290 291 static inline void gicr_write_isactiver0(uintptr_t base, unsigned int val) 292 { 293 mmio_write_32(base + GICR_ISACTIVER0, val); 294 } 295 296 static inline unsigned int gicr_read_icfgr0(uintptr_t base) 297 { 298 return mmio_read_32(base + GICR_ICFGR0); 299 } 300 301 static inline unsigned int gicr_read_icfgr1(uintptr_t base) 302 { 303 return mmio_read_32(base + GICR_ICFGR1); 304 } 305 306 static inline void gicr_write_icfgr0(uintptr_t base, unsigned int val) 307 { 308 mmio_write_32(base + GICR_ICFGR0, val); 309 } 310 311 static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val) 312 { 313 mmio_write_32(base + GICR_ICFGR1, val); 314 } 315 316 static inline uint64_t gicr_read_propbaser(uintptr_t base) 317 { 318 return mmio_read_64(base + GICR_PROPBASER); 319 } 320 321 static inline void gicr_write_propbaser(uintptr_t base, uint64_t val) 322 { 323 mmio_write_64(base + GICR_PROPBASER, val); 324 } 325 326 static inline uint64_t gicr_read_pendbaser(uintptr_t base) 327 { 328 return mmio_read_64(base + GICR_PENDBASER); 329 } 330 331 static inline void gicr_write_pendbaser(uintptr_t base, uint64_t val) 332 { 333 mmio_write_64(base + GICR_PENDBASER, val); 334 } 335 336 /******************************************************************************* 337 * GIC ITS functions to read and write entire ITS registers. 338 ******************************************************************************/ 339 static inline uint32_t gits_read_ctlr(uintptr_t base) 340 { 341 return mmio_read_32(base + GITS_CTLR); 342 } 343 344 static inline void gits_write_ctlr(uintptr_t base, unsigned int val) 345 { 346 mmio_write_32(base + GITS_CTLR, val); 347 } 348 349 static inline uint64_t gits_read_cbaser(uintptr_t base) 350 { 351 return mmio_read_64(base + GITS_CBASER); 352 } 353 354 static inline void gits_write_cbaser(uintptr_t base, uint64_t val) 355 { 356 mmio_write_64(base + GITS_CBASER, val); 357 } 358 359 static inline uint64_t gits_read_cwriter(uintptr_t base) 360 { 361 return mmio_read_64(base + GITS_CWRITER); 362 } 363 364 static inline void gits_write_cwriter(uintptr_t base, uint64_t val) 365 { 366 mmio_write_64(base + GITS_CWRITER, val); 367 } 368 369 static inline uint64_t gits_read_baser(uintptr_t base, unsigned int its_table_id) 370 { 371 assert(its_table_id < 8U); 372 return mmio_read_64(base + GITS_BASER + (8U * its_table_id)); 373 } 374 375 static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id, uint64_t val) 376 { 377 assert(its_table_id < 8U); 378 mmio_write_64(base + GITS_BASER + (8U * its_table_id), val); 379 } 380 381 /* 382 * Wait for Quiescent bit when GIC ITS is disabled 383 */ 384 static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base) 385 { 386 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 387 while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0U) 388 ; 389 } 390 391 392 #endif /* GICV3_PRIVATE_H */ 393