1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __GICV3_PRIVATE_H__ 32 #define __GICV3_PRIVATE_H__ 33 34 #include <gicv3.h> 35 #include <mmio.h> 36 #include <stdint.h> 37 38 /******************************************************************************* 39 * GICv3 private macro definitions 40 ******************************************************************************/ 41 42 /* Constants to indicate the status of the RWP bit */ 43 #define RWP_TRUE 1 44 #define RWP_FALSE 0 45 46 /* 47 * Macro to wait for updates to : 48 * GICD_CTLR[2:0] - the Group Enables 49 * GICD_CTLR[5:4] - the ARE bits 50 * GICD_ICENABLERn - the clearing of enable state for SPIs 51 */ 52 #define gicd_wait_for_pending_write(gicd_base) \ 53 do { \ 54 ; \ 55 } while (gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) 56 57 /* 58 * Macro to convert an mpidr to a value suitable for programming into a 59 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant 60 * to GICv3. 61 */ 62 #define gicd_irouter_val_from_mpidr(mpidr, irm) \ 63 ((mpidr & ~(0xff << 24)) | \ 64 (irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT) 65 66 /* 67 * Macro to wait for updates to : 68 * GICR_ICENABLER0 69 * GICR_CTLR.DPG1S 70 * GICR_CTLR.DPG1NS 71 * GICR_CTLR.DPG0 72 */ 73 #define gicr_wait_for_pending_write(gicr_base) \ 74 do { \ 75 ; \ 76 } while (gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) 77 78 /* 79 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] 80 * are zeroes. 81 */ 82 #define mpidr_from_gicr_typer(typer_val) \ 83 ((((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \ 84 ((typer_val >> 32) & 0xffffff)) 85 86 /******************************************************************************* 87 * Private GICv3 function prototypes for accessing entire registers. 88 * Note: The raw register values correspond to multiple interrupt IDs and 89 * the number of interrupt IDs involved depends on the register accessed. 90 ******************************************************************************/ 91 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id); 92 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id); 93 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); 94 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); 95 96 /******************************************************************************* 97 * Private GICv3 function prototypes for accessing the GIC registers 98 * corresponding to a single interrupt ID. These functions use bitwise 99 * operations or appropriate register accesses to modify or return 100 * the bit-field corresponding the single interrupt ID. 101 ******************************************************************************/ 102 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id); 103 unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id); 104 unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id); 105 void gicd_set_igrpmodr(uintptr_t base, unsigned int id); 106 void gicr_set_igrpmodr0(uintptr_t base, unsigned int id); 107 void gicr_set_isenabler0(uintptr_t base, unsigned int id); 108 void gicr_set_igroupr0(uintptr_t base, unsigned int id); 109 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id); 110 void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id); 111 void gicr_clr_igroupr0(uintptr_t base, unsigned int id); 112 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); 113 114 /******************************************************************************* 115 * Private GICv3 helper function prototypes 116 ******************************************************************************/ 117 void gicv3_spis_configure_defaults(uintptr_t gicd_base); 118 void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base); 119 void gicv3_secure_spis_configure(uintptr_t gicd_base, 120 unsigned int num_ints, 121 const unsigned int *sec_intr_list, 122 unsigned int int_grp); 123 void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base, 124 unsigned int num_ints, 125 const unsigned int *sec_intr_list, 126 unsigned int int_grp); 127 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 128 unsigned int rdistif_num, 129 uintptr_t gicr_base, 130 mpidr_hash_fn mpidr_to_core_pos); 131 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base); 132 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base); 133 134 /******************************************************************************* 135 * GIC Distributor interface accessors 136 ******************************************************************************/ 137 static inline unsigned int gicd_read_pidr2(uintptr_t base) 138 { 139 return mmio_read_32(base + GICD_PIDR2_GICV3); 140 } 141 142 static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id) 143 { 144 return mmio_read_64(base + GICD_IROUTER + (id << 3)); 145 } 146 147 static inline void gicd_write_irouter(uintptr_t base, 148 unsigned int id, 149 unsigned long long affinity) 150 { 151 mmio_write_64(base + GICD_IROUTER + (id << 3), affinity); 152 } 153 154 static inline void gicd_clr_ctlr(uintptr_t base, 155 unsigned int bitmap, 156 unsigned int rwp) 157 { 158 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap); 159 if (rwp) 160 gicd_wait_for_pending_write(base); 161 } 162 163 static inline void gicd_set_ctlr(uintptr_t base, 164 unsigned int bitmap, 165 unsigned int rwp) 166 { 167 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap); 168 if (rwp) 169 gicd_wait_for_pending_write(base); 170 } 171 172 /******************************************************************************* 173 * GIC Redistributor interface accessors 174 ******************************************************************************/ 175 static inline unsigned long long gicr_read_ctlr(uintptr_t base) 176 { 177 return mmio_read_64(base + GICR_CTLR); 178 } 179 180 static inline unsigned long long gicr_read_typer(uintptr_t base) 181 { 182 return mmio_read_64(base + GICR_TYPER); 183 } 184 185 static inline unsigned int gicr_read_waker(uintptr_t base) 186 { 187 return mmio_read_32(base + GICR_WAKER); 188 } 189 190 static inline void gicr_write_waker(uintptr_t base, unsigned int val) 191 { 192 mmio_write_32(base + GICR_WAKER, val); 193 } 194 195 /******************************************************************************* 196 * GIC Re-distributor functions for accessing entire registers. 197 * Note: The raw register values correspond to multiple interrupt IDs and 198 * the number of interrupt IDs involved depends on the register accessed. 199 ******************************************************************************/ 200 static inline unsigned int gicr_read_icenabler0(uintptr_t base) 201 { 202 return mmio_read_32(base + GICR_ICENABLER0); 203 } 204 205 static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val) 206 { 207 mmio_write_32(base + GICR_ICENABLER0, val); 208 } 209 210 static inline unsigned int gicr_read_isenabler0(uintptr_t base) 211 { 212 return mmio_read_32(base + GICR_ISENABLER0); 213 } 214 215 static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val) 216 { 217 mmio_write_32(base + GICR_ISENABLER0, val); 218 } 219 220 static inline unsigned int gicr_read_igroupr0(uintptr_t base) 221 { 222 return mmio_read_32(base + GICR_IGROUPR0); 223 } 224 225 static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val) 226 { 227 mmio_write_32(base + GICR_IGROUPR0, val); 228 } 229 230 static inline unsigned int gicr_read_igrpmodr0(uintptr_t base) 231 { 232 return mmio_read_32(base + GICR_IGRPMODR0); 233 } 234 235 static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val) 236 { 237 mmio_write_32(base + GICR_IGRPMODR0, val); 238 } 239 240 static inline unsigned int gicr_read_icfgr1(uintptr_t base) 241 { 242 return mmio_read_32(base + GICR_ICFGR1); 243 } 244 245 static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val) 246 { 247 mmio_write_32(base + GICR_ICFGR1, val); 248 } 249 250 #endif /* __GICV3_PRIVATE_H__ */ 251