1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __GICV3_PRIVATE_H__ 32 #define __GICV3_PRIVATE_H__ 33 34 #include <gicv3.h> 35 #include <mmio.h> 36 #include <stdint.h> 37 38 /******************************************************************************* 39 * GICv3 private macro definitions 40 ******************************************************************************/ 41 42 /* Constants to indicate the status of the RWP bit */ 43 #define RWP_TRUE 1 44 #define RWP_FALSE 0 45 46 /* 47 * Macro to wait for updates to : 48 * GICD_CTLR[2:0] - the Group Enables 49 * GICD_CTLR[5:4] - the ARE bits 50 * GICD_ICENABLERn - the clearing of enable state for SPIs 51 */ 52 #define gicd_wait_for_pending_write(gicd_base) \ 53 do { \ 54 ; \ 55 } while (gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) 56 57 /* 58 * Macro to convert an mpidr to a value suitable for programming into a 59 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant 60 * to GICv3. 61 */ 62 #define gicd_irouter_val_from_mpidr(mpidr, irm) \ 63 ((mpidr & ~(0xff << 24)) | \ 64 (irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT) 65 66 /* 67 * Macro to wait for updates to : 68 * GICR_ICENABLER0 69 * GICR_CTLR.DPG1S 70 * GICR_CTLR.DPG1NS 71 * GICR_CTLR.DPG0 72 */ 73 #define gicr_wait_for_pending_write(gicr_base) \ 74 do { \ 75 ; \ 76 } while (gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) 77 78 /* 79 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] 80 * are zeroes. 81 */ 82 #define mpidr_from_gicr_typer(typer_val) \ 83 ((((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \ 84 ((typer_val >> 32) & 0xffffff)) 85 86 /******************************************************************************* 87 * Private function prototypes 88 ******************************************************************************/ 89 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id); 90 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id); 91 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id); 92 unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id); 93 unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id); 94 unsigned int gicv3_get_pending_grp1_interrupt_id(unsigned int pending_grp); 95 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); 96 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); 97 void gicd_set_igrpmodr(uintptr_t base, unsigned int id); 98 void gicr_set_igrpmodr0(uintptr_t base, unsigned int id); 99 void gicr_set_isenabler0(uintptr_t base, unsigned int id); 100 void gicr_set_igroupr0(uintptr_t base, unsigned int id); 101 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id); 102 void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id); 103 void gicr_clr_igroupr0(uintptr_t base, unsigned int id); 104 void gicv3_spis_configure_defaults(uintptr_t gicd_base); 105 void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base); 106 void gicv3_secure_spis_configure(uintptr_t gicd_base, 107 unsigned int num_ints, 108 const unsigned int *sec_intr_list, 109 unsigned int int_grp); 110 void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base, 111 unsigned int num_ints, 112 const unsigned int *sec_intr_list, 113 unsigned int int_grp); 114 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 115 unsigned int rdistif_num, 116 uintptr_t gicr_base, 117 mpidr_hash_fn mpidr_to_core_pos); 118 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base); 119 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base); 120 121 /******************************************************************************* 122 * GIC Distributor interface accessors 123 ******************************************************************************/ 124 static inline unsigned int gicd_read_pidr2(uintptr_t base) 125 { 126 return mmio_read_32(base + GICD_PIDR2_GICV3); 127 } 128 129 static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id) 130 { 131 return mmio_read_64(base + GICD_IROUTER + (id << 3)); 132 } 133 134 static inline void gicd_write_irouter(uintptr_t base, 135 unsigned int id, 136 unsigned long long affinity) 137 { 138 mmio_write_64(base + GICD_IROUTER + (id << 3), affinity); 139 } 140 141 static inline void gicd_clr_ctlr(uintptr_t base, 142 unsigned int bitmap, 143 unsigned int rwp) 144 { 145 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap); 146 if (rwp) 147 gicd_wait_for_pending_write(base); 148 } 149 150 static inline void gicd_set_ctlr(uintptr_t base, 151 unsigned int bitmap, 152 unsigned int rwp) 153 { 154 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap); 155 if (rwp) 156 gicd_wait_for_pending_write(base); 157 } 158 159 /******************************************************************************* 160 * GIC Redistributor interface accessors 161 ******************************************************************************/ 162 static inline unsigned long long gicr_read_ctlr(uintptr_t base) 163 { 164 return mmio_read_64(base + GICR_CTLR); 165 } 166 167 static inline unsigned long long gicr_read_typer(uintptr_t base) 168 { 169 return mmio_read_64(base + GICR_TYPER); 170 } 171 172 static inline unsigned int gicr_read_waker(uintptr_t base) 173 { 174 return mmio_read_32(base + GICR_WAKER); 175 } 176 177 static inline void gicr_write_waker(uintptr_t base, unsigned int val) 178 { 179 mmio_write_32(base + GICR_WAKER, val); 180 } 181 182 static inline unsigned int gicr_read_icenabler0(uintptr_t base) 183 { 184 return mmio_read_32(base + GICR_ICENABLER0); 185 } 186 187 static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val) 188 { 189 mmio_write_32(base + GICR_ICENABLER0, val); 190 } 191 192 static inline unsigned int gicr_read_isenabler0(uintptr_t base) 193 { 194 return mmio_read_32(base + GICR_ISENABLER0); 195 } 196 197 static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val) 198 { 199 mmio_write_32(base + GICR_ISENABLER0, val); 200 } 201 202 static inline unsigned int gicr_read_igroupr0(uintptr_t base) 203 { 204 return mmio_read_32(base + GICR_IGROUPR0); 205 } 206 207 static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val) 208 { 209 mmio_write_32(base + GICR_IGROUPR0, val); 210 } 211 212 static inline unsigned int gicr_read_igrpmodr0(uintptr_t base) 213 { 214 return mmio_read_32(base + GICR_IGRPMODR0); 215 } 216 217 static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val) 218 { 219 mmio_write_32(base + GICR_IGRPMODR0, val); 220 } 221 222 static inline unsigned int gicr_read_icfgr1(uintptr_t base) 223 { 224 return mmio_read_32(base + GICR_ICFGR1); 225 } 226 227 static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val) 228 { 229 mmio_write_32(base + GICR_ICFGR1, val); 230 } 231 232 #endif /* __GICV3_PRIVATE_H__ */ 233