1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <debug.h> 35 #include <gic_common.h> 36 #include <gicv3.h> 37 #include "../common/gic_common_private.h" 38 #include "gicv3_private.h" 39 40 static const gicv3_driver_data_t *driver_data; 41 static unsigned int gicv2_compat; 42 43 /******************************************************************************* 44 * This function initialises the ARM GICv3 driver in EL3 with provided platform 45 * inputs. 46 ******************************************************************************/ 47 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 48 { 49 unsigned int gic_version; 50 51 assert(plat_driver_data); 52 assert(plat_driver_data->gicd_base); 53 assert(plat_driver_data->gicr_base); 54 assert(plat_driver_data->rdistif_num); 55 assert(plat_driver_data->rdistif_base_addrs); 56 57 assert(IS_IN_EL3()); 58 59 /* 60 * The platform should provide a list of at least one type of 61 * interrupts 62 */ 63 assert(plat_driver_data->g0_interrupt_array || 64 plat_driver_data->g1s_interrupt_array); 65 66 /* 67 * If there are no interrupts of a particular type, then the number of 68 * interrupts of that type should be 0 and vice-versa. 69 */ 70 assert(plat_driver_data->g0_interrupt_array ? 71 plat_driver_data->g0_interrupt_num : 72 plat_driver_data->g0_interrupt_num == 0); 73 assert(plat_driver_data->g1s_interrupt_array ? 74 plat_driver_data->g1s_interrupt_num : 75 plat_driver_data->g1s_interrupt_num == 0); 76 77 /* Check for system register support */ 78 #ifdef AARCH32 79 assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)); 80 #else 81 assert(read_id_aa64pfr0_el1() & 82 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)); 83 #endif /* AARCH32 */ 84 85 /* The GIC version should be 3.0 */ 86 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 87 gic_version >>= PIDR2_ARCH_REV_SHIFT; 88 gic_version &= PIDR2_ARCH_REV_MASK; 89 assert(gic_version == ARCH_REV_GICV3); 90 91 /* 92 * Find out whether the GIC supports the GICv2 compatibility mode. The 93 * ARE_S bit resets to 0 if supported 94 */ 95 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 96 gicv2_compat >>= CTLR_ARE_S_SHIFT; 97 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); 98 99 /* 100 * Find the base address of each implemented Redistributor interface. 101 * The number of interfaces should be equal to the number of CPUs in the 102 * system. The memory for saving these addresses has to be allocated by 103 * the platform port 104 */ 105 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 106 plat_driver_data->rdistif_num, 107 plat_driver_data->gicr_base, 108 plat_driver_data->mpidr_to_core_pos); 109 110 driver_data = plat_driver_data; 111 112 INFO("GICv3 %s legacy support detected." 113 " ARM GICV3 driver initialized in EL3\n", 114 gicv2_compat ? "with" : "without"); 115 } 116 117 /******************************************************************************* 118 * This function initialises the GIC distributor interface based upon the data 119 * provided by the platform while initialising the driver. 120 ******************************************************************************/ 121 void gicv3_distif_init(void) 122 { 123 unsigned int bitmap = 0; 124 125 assert(driver_data); 126 assert(driver_data->gicd_base); 127 assert(driver_data->g1s_interrupt_array || 128 driver_data->g0_interrupt_array); 129 130 assert(IS_IN_EL3()); 131 132 /* 133 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 134 * the ARE_S bit. The Distributor might generate a system error 135 * otherwise. 136 */ 137 gicd_clr_ctlr(driver_data->gicd_base, 138 CTLR_ENABLE_G0_BIT | 139 CTLR_ENABLE_G1S_BIT | 140 CTLR_ENABLE_G1NS_BIT, 141 RWP_TRUE); 142 143 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 144 gicd_set_ctlr(driver_data->gicd_base, 145 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 146 147 /* Set the default attribute of all SPIs */ 148 gicv3_spis_configure_defaults(driver_data->gicd_base); 149 150 /* Configure the G1S SPIs */ 151 if (driver_data->g1s_interrupt_array) { 152 gicv3_secure_spis_configure(driver_data->gicd_base, 153 driver_data->g1s_interrupt_num, 154 driver_data->g1s_interrupt_array, 155 INTR_GROUP1S); 156 bitmap |= CTLR_ENABLE_G1S_BIT; 157 } 158 159 /* Configure the G0 SPIs */ 160 if (driver_data->g0_interrupt_array) { 161 gicv3_secure_spis_configure(driver_data->gicd_base, 162 driver_data->g0_interrupt_num, 163 driver_data->g0_interrupt_array, 164 INTR_GROUP0); 165 bitmap |= CTLR_ENABLE_G0_BIT; 166 } 167 168 /* Enable the secure SPIs now that they have been configured */ 169 gicd_set_ctlr(driver_data->gicd_base, bitmap, RWP_TRUE); 170 } 171 172 /******************************************************************************* 173 * This function initialises the GIC Redistributor interface of the calling CPU 174 * (identified by the 'proc_num' parameter) based upon the data provided by the 175 * platform while initialising the driver. 176 ******************************************************************************/ 177 void gicv3_rdistif_init(unsigned int proc_num) 178 { 179 uintptr_t gicr_base; 180 181 assert(driver_data); 182 assert(proc_num < driver_data->rdistif_num); 183 assert(driver_data->rdistif_base_addrs); 184 assert(driver_data->gicd_base); 185 assert(gicd_read_ctlr(driver_data->gicd_base) & CTLR_ARE_S_BIT); 186 assert(driver_data->g1s_interrupt_array || 187 driver_data->g0_interrupt_array); 188 189 assert(IS_IN_EL3()); 190 191 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 192 193 /* Set the default attribute of all SGIs and PPIs */ 194 gicv3_ppi_sgi_configure_defaults(gicr_base); 195 196 /* Configure the G1S SGIs/PPIs */ 197 if (driver_data->g1s_interrupt_array) { 198 gicv3_secure_ppi_sgi_configure(gicr_base, 199 driver_data->g1s_interrupt_num, 200 driver_data->g1s_interrupt_array, 201 INTR_GROUP1S); 202 } 203 204 /* Configure the G0 SGIs/PPIs */ 205 if (driver_data->g0_interrupt_array) { 206 gicv3_secure_ppi_sgi_configure(gicr_base, 207 driver_data->g0_interrupt_num, 208 driver_data->g0_interrupt_array, 209 INTR_GROUP0); 210 } 211 } 212 213 /******************************************************************************* 214 * This function enables the GIC CPU interface of the calling CPU using only 215 * system register accesses. 216 ******************************************************************************/ 217 void gicv3_cpuif_enable(unsigned int proc_num) 218 { 219 uintptr_t gicr_base; 220 unsigned int scr_el3; 221 unsigned int icc_sre_el3; 222 223 assert(driver_data); 224 assert(proc_num < driver_data->rdistif_num); 225 assert(driver_data->rdistif_base_addrs); 226 assert(IS_IN_EL3()); 227 228 /* Mark the connected core as awake */ 229 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 230 gicv3_rdistif_mark_core_awake(gicr_base); 231 232 /* Disable the legacy interrupt bypass */ 233 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 234 235 /* 236 * Enable system register access for EL3 and allow lower exception 237 * levels to configure the same for themselves. If the legacy mode is 238 * not supported, the SRE bit is RAO/WI 239 */ 240 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 241 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 242 243 scr_el3 = read_scr_el3(); 244 245 /* 246 * Switch to NS state to write Non secure ICC_SRE_EL1 and 247 * ICC_SRE_EL2 registers. 248 */ 249 write_scr_el3(scr_el3 | SCR_NS_BIT); 250 isb(); 251 252 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 253 write_icc_sre_el1(ICC_SRE_SRE_BIT); 254 isb(); 255 256 /* Switch to secure state. */ 257 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 258 isb(); 259 260 /* Program the idle priority in the PMR */ 261 write_icc_pmr_el1(GIC_PRI_MASK); 262 263 /* Enable Group0 interrupts */ 264 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 265 266 /* Enable Group1 Secure interrupts */ 267 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 268 IGRPEN1_EL3_ENABLE_G1S_BIT); 269 270 /* Write the secure ICC_SRE_EL1 register */ 271 write_icc_sre_el1(ICC_SRE_SRE_BIT); 272 isb(); 273 } 274 275 /******************************************************************************* 276 * This function disables the GIC CPU interface of the calling CPU using 277 * only system register accesses. 278 ******************************************************************************/ 279 void gicv3_cpuif_disable(unsigned int proc_num) 280 { 281 uintptr_t gicr_base; 282 283 assert(driver_data); 284 assert(proc_num < driver_data->rdistif_num); 285 assert(driver_data->rdistif_base_addrs); 286 287 assert(IS_IN_EL3()); 288 289 /* Disable legacy interrupt bypass */ 290 write_icc_sre_el3(read_icc_sre_el3() | 291 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 292 293 /* Disable Group0 interrupts */ 294 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 295 ~IGRPEN1_EL1_ENABLE_G0_BIT); 296 297 /* Disable Group1 Secure and Non-Secure interrupts */ 298 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 299 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 300 IGRPEN1_EL3_ENABLE_G1S_BIT)); 301 302 /* Synchronise accesses to group enable registers */ 303 isb(); 304 305 /* Mark the connected core as asleep */ 306 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 307 gicv3_rdistif_mark_core_asleep(gicr_base); 308 } 309 310 /******************************************************************************* 311 * This function returns the id of the highest priority pending interrupt at 312 * the GIC cpu interface. 313 ******************************************************************************/ 314 unsigned int gicv3_get_pending_interrupt_id(void) 315 { 316 unsigned int id; 317 318 assert(IS_IN_EL3()); 319 id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 320 321 /* 322 * If the ID is special identifier corresponding to G1S or G1NS 323 * interrupt, then read the highest pending group 1 interrupt. 324 */ 325 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) 326 return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 327 328 return id; 329 } 330 331 /******************************************************************************* 332 * This function returns the type of the highest priority pending interrupt at 333 * the GIC cpu interface. The return values can be one of the following : 334 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 335 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 336 * 0 - 1019 : The interrupt type is secure Group 0. 337 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 338 * sufficient priority to be signaled 339 ******************************************************************************/ 340 unsigned int gicv3_get_pending_interrupt_type(void) 341 { 342 assert(IS_IN_EL3()); 343 return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 344 } 345 346 /******************************************************************************* 347 * This function returns the type of the interrupt id depending upon the group 348 * this interrupt has been configured under by the interrupt controller i.e. 349 * group0 or group1 Secure / Non Secure. The return value can be one of the 350 * following : 351 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 352 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 353 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 354 * interrupt. 355 ******************************************************************************/ 356 unsigned int gicv3_get_interrupt_type(unsigned int id, 357 unsigned int proc_num) 358 { 359 unsigned int igroup, grpmodr; 360 uintptr_t gicr_base; 361 362 assert(IS_IN_EL3()); 363 assert(driver_data); 364 365 /* Ensure the parameters are valid */ 366 assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID); 367 assert(proc_num < driver_data->rdistif_num); 368 369 /* All LPI interrupts are Group 1 non secure */ 370 if (id >= MIN_LPI_ID) 371 return INTR_GROUP1NS; 372 373 if (id < MIN_SPI_ID) { 374 assert(driver_data->rdistif_base_addrs); 375 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 376 igroup = gicr_get_igroupr0(gicr_base, id); 377 grpmodr = gicr_get_igrpmodr0(gicr_base, id); 378 } else { 379 assert(driver_data->gicd_base); 380 igroup = gicd_get_igroupr(driver_data->gicd_base, id); 381 grpmodr = gicd_get_igrpmodr(driver_data->gicd_base, id); 382 } 383 384 /* 385 * If the IGROUP bit is set, then it is a Group 1 Non secure 386 * interrupt 387 */ 388 if (igroup) 389 return INTR_GROUP1NS; 390 391 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 392 if (grpmodr) 393 return INTR_GROUP1S; 394 395 /* Else it is a Group 0 Secure interrupt */ 396 return INTR_GROUP0; 397 } 398