1 /* 2 * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/interrupt_props.h> 13 #include <drivers/arm/gicv3.h> 14 #include <lib/spinlock.h> 15 #include <plat/common/platform.h> 16 17 #include "gicv3_private.h" 18 19 const gicv3_driver_data_t *gicv3_driver_data; 20 21 /* 22 * Spinlock to guard registers needing read-modify-write. APIs protected by this 23 * spinlock are used either at boot time (when only a single CPU is active), or 24 * when the system is fully coherent. 25 */ 26 static spinlock_t gic_lock; 27 28 /* 29 * Redistributor power operations are weakly bound so that they can be 30 * overridden 31 */ 32 #pragma weak gicv3_rdistif_off 33 #pragma weak gicv3_rdistif_on 34 35 /* Check interrupt ID for SGI/(E)PPI and (E)SPIs */ 36 static bool is_sgi_ppi(unsigned int id); 37 38 /* 39 * Helper macros to save and restore GICR and GICD registers 40 * corresponding to their numbers to and from the context 41 */ 42 #define RESTORE_GICR_REG(base, ctx, name, i) \ 43 gicr_write_##name((base), (i), (ctx)->gicr_##name[(i)]) 44 45 #define SAVE_GICR_REG(base, ctx, name, i) \ 46 (ctx)->gicr_##name[(i)] = gicr_read_##name((base), (i)) 47 48 /* Helper macros to save and restore GICD registers to and from the context */ 49 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 50 do { \ 51 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 52 int_id += (1U << REG##R_SHIFT)) { \ 53 gicd_write_##reg((base), int_id, \ 54 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 55 REG##R_SHIFT]); \ 56 } \ 57 } while (false) 58 59 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 60 do { \ 61 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 62 int_id += (1U << REG##R_SHIFT)) { \ 63 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 64 REG##R_SHIFT] = gicd_read_##reg((base), int_id); \ 65 } \ 66 } while (false) 67 68 #if GIC_EXT_INTID 69 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 70 do { \ 71 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 72 int_id += (1U << REG##R_SHIFT)) { \ 73 gicd_write_##reg((base), int_id, \ 74 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ 75 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ 76 >> REG##R_SHIFT]); \ 77 } \ 78 } while (false) 79 80 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 81 do { \ 82 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 83 int_id += (1U << REG##R_SHIFT)) { \ 84 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ 85 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ 86 >> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\ 87 } \ 88 } while (false) 89 #else 90 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) 91 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) 92 #endif /* GIC_EXT_INTID */ 93 94 /******************************************************************************* 95 * This function initialises the ARM GICv3 driver in EL3 with provided platform 96 * inputs. 97 ******************************************************************************/ 98 void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 99 { 100 unsigned int gic_version; 101 unsigned int gicv2_compat; 102 103 assert(plat_driver_data != NULL); 104 assert(plat_driver_data->gicd_base != 0U); 105 assert(plat_driver_data->rdistif_num != 0U); 106 assert(plat_driver_data->rdistif_base_addrs != NULL); 107 108 assert(IS_IN_EL3()); 109 110 assert((plat_driver_data->interrupt_props_num != 0U) ? 111 (plat_driver_data->interrupt_props != NULL) : 1); 112 113 /* Check for system register support */ 114 #ifndef __aarch64__ 115 assert((read_id_pfr1() & 116 (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); 117 #else 118 assert((read_id_aa64pfr0_el1() & 119 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U); 120 #endif /* !__aarch64__ */ 121 122 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 123 gic_version >>= PIDR2_ARCH_REV_SHIFT; 124 gic_version &= PIDR2_ARCH_REV_MASK; 125 126 /* Check GIC version */ 127 #if !GIC_ENABLE_V4_EXTN 128 assert(gic_version == ARCH_REV_GICV3); 129 #endif 130 /* 131 * Find out whether the GIC supports the GICv2 compatibility mode. 132 * The ARE_S bit resets to 0 if supported 133 */ 134 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 135 gicv2_compat >>= CTLR_ARE_S_SHIFT; 136 gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK; 137 138 if (plat_driver_data->gicr_base != 0U) { 139 /* 140 * Find the base address of each implemented Redistributor interface. 141 * The number of interfaces should be equal to the number of CPUs in the 142 * system. The memory for saving these addresses has to be allocated by 143 * the platform port 144 */ 145 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 146 plat_driver_data->rdistif_num, 147 plat_driver_data->gicr_base, 148 plat_driver_data->mpidr_to_core_pos); 149 #if !HW_ASSISTED_COHERENCY 150 /* 151 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 152 */ 153 flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs), 154 plat_driver_data->rdistif_num * 155 sizeof(*(plat_driver_data->rdistif_base_addrs))); 156 #endif 157 } 158 gicv3_driver_data = plat_driver_data; 159 160 /* 161 * The GIC driver data is initialized by the primary CPU with caches 162 * enabled. When the secondary CPU boots up, it initializes the 163 * GICC/GICR interface with the caches disabled. Hence flush the 164 * driver data to ensure coherency. This is not required if the 165 * platform has HW_ASSISTED_COHERENCY enabled. 166 */ 167 #if !HW_ASSISTED_COHERENCY 168 flush_dcache_range((uintptr_t)&gicv3_driver_data, 169 sizeof(gicv3_driver_data)); 170 flush_dcache_range((uintptr_t)gicv3_driver_data, 171 sizeof(*gicv3_driver_data)); 172 #endif 173 gicv3_check_erratas_applies(plat_driver_data->gicd_base); 174 175 INFO("GICv%u with%s legacy support detected.\n", gic_version, 176 (gicv2_compat == 0U) ? "" : "out"); 177 INFO("ARM GICv%u driver initialized in EL3\n", gic_version); 178 } 179 180 /******************************************************************************* 181 * This function initialises the GIC distributor interface based upon the data 182 * provided by the platform while initialising the driver. 183 ******************************************************************************/ 184 void __init gicv3_distif_init(void) 185 { 186 unsigned int bitmap; 187 188 assert(gicv3_driver_data != NULL); 189 assert(gicv3_driver_data->gicd_base != 0U); 190 191 assert(IS_IN_EL3()); 192 193 /* 194 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 195 * the ARE_S bit. The Distributor might generate a system error 196 * otherwise. 197 */ 198 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 199 CTLR_ENABLE_G0_BIT | 200 CTLR_ENABLE_G1S_BIT | 201 CTLR_ENABLE_G1NS_BIT, 202 RWP_TRUE); 203 204 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 205 gicd_set_ctlr(gicv3_driver_data->gicd_base, 206 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 207 208 /* Set the default attribute of all (E)SPIs */ 209 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); 210 211 bitmap = gicv3_secure_spis_config_props( 212 gicv3_driver_data->gicd_base, 213 gicv3_driver_data->interrupt_props, 214 gicv3_driver_data->interrupt_props_num); 215 216 /* Enable the secure (E)SPIs now that they have been configured */ 217 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 218 } 219 220 /******************************************************************************* 221 * This function initialises the GIC Redistributor interface of the calling CPU 222 * (identified by the 'proc_num' parameter) based upon the data provided by the 223 * platform while initialising the driver. 224 ******************************************************************************/ 225 void gicv3_rdistif_init(unsigned int proc_num) 226 { 227 uintptr_t gicr_base; 228 unsigned int bitmap; 229 uint32_t ctlr; 230 231 assert(gicv3_driver_data != NULL); 232 assert(proc_num < gicv3_driver_data->rdistif_num); 233 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 234 assert(gicv3_driver_data->gicd_base != 0U); 235 236 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base); 237 assert((ctlr & CTLR_ARE_S_BIT) != 0U); 238 239 assert(IS_IN_EL3()); 240 241 /* Power on redistributor */ 242 gicv3_rdistif_on(proc_num); 243 244 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 245 assert(gicr_base != 0U); 246 247 /* Set the default attribute of all SGIs and (E)PPIs */ 248 gicv3_ppi_sgi_config_defaults(gicr_base); 249 250 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, 251 gicv3_driver_data->interrupt_props, 252 gicv3_driver_data->interrupt_props_num); 253 254 /* Enable interrupt groups as required, if not already */ 255 if ((ctlr & bitmap) != bitmap) { 256 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 257 } 258 } 259 260 /******************************************************************************* 261 * Functions to perform power operations on GIC Redistributor 262 ******************************************************************************/ 263 void gicv3_rdistif_off(unsigned int proc_num) 264 { 265 } 266 267 void gicv3_rdistif_on(unsigned int proc_num) 268 { 269 } 270 271 /******************************************************************************* 272 * This function enables the GIC CPU interface of the calling CPU using only 273 * system register accesses. 274 ******************************************************************************/ 275 void gicv3_cpuif_enable(unsigned int proc_num) 276 { 277 uintptr_t gicr_base; 278 u_register_t scr_el3; 279 unsigned int icc_sre_el3; 280 281 assert(gicv3_driver_data != NULL); 282 assert(proc_num < gicv3_driver_data->rdistif_num); 283 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 284 assert(IS_IN_EL3()); 285 286 /* Mark the connected core as awake */ 287 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 288 gicv3_rdistif_mark_core_awake(gicr_base); 289 290 /* Disable the legacy interrupt bypass */ 291 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 292 293 /* 294 * Enable system register access for EL3 and allow lower exception 295 * levels to configure the same for themselves. If the legacy mode is 296 * not supported, the SRE bit is RAO/WI 297 */ 298 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 299 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 300 301 scr_el3 = read_scr_el3(); 302 303 /* 304 * Switch to NS state to write Non secure ICC_SRE_EL1 and 305 * ICC_SRE_EL2 registers. 306 */ 307 write_scr_el3(scr_el3 | SCR_NS_BIT); 308 isb(); 309 310 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 311 write_icc_sre_el1(ICC_SRE_SRE_BIT); 312 isb(); 313 314 /* Switch to secure state. */ 315 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 316 isb(); 317 318 /* Write the secure ICC_SRE_EL1 register */ 319 write_icc_sre_el1(ICC_SRE_SRE_BIT); 320 isb(); 321 322 /* Program the idle priority in the PMR */ 323 write_icc_pmr_el1(GIC_PRI_MASK); 324 325 /* Enable Group0 interrupts */ 326 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 327 328 /* Enable Group1 Secure interrupts */ 329 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 330 IGRPEN1_EL3_ENABLE_G1S_BIT); 331 isb(); 332 /* Add DSB to ensure visibility of System register writes */ 333 dsb(); 334 } 335 336 /******************************************************************************* 337 * This function disables the GIC CPU interface of the calling CPU using 338 * only system register accesses. 339 ******************************************************************************/ 340 void gicv3_cpuif_disable(unsigned int proc_num) 341 { 342 uintptr_t gicr_base; 343 344 assert(gicv3_driver_data != NULL); 345 assert(proc_num < gicv3_driver_data->rdistif_num); 346 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 347 348 assert(IS_IN_EL3()); 349 350 /* Disable legacy interrupt bypass */ 351 write_icc_sre_el3(read_icc_sre_el3() | 352 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 353 354 /* Disable Group0 interrupts */ 355 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 356 ~IGRPEN1_EL1_ENABLE_G0_BIT); 357 358 /* Disable Group1 Secure and Non-Secure interrupts */ 359 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 360 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 361 IGRPEN1_EL3_ENABLE_G1S_BIT)); 362 363 /* Synchronise accesses to group enable registers */ 364 isb(); 365 /* Add DSB to ensure visibility of System register writes */ 366 dsb(); 367 368 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 369 assert(gicr_base != 0UL); 370 371 /* 372 * dsb() already issued previously after clearing the CPU group 373 * enabled, apply below workaround to toggle the "DPG*" 374 * bits of GICR_CTLR register for unblocking event. 375 */ 376 gicv3_apply_errata_wa_2384374(gicr_base); 377 378 /* Mark the connected core as asleep */ 379 gicv3_rdistif_mark_core_asleep(gicr_base); 380 } 381 382 /******************************************************************************* 383 * This function returns the id of the highest priority pending interrupt at 384 * the GIC cpu interface. 385 ******************************************************************************/ 386 unsigned int gicv3_get_pending_interrupt_id(void) 387 { 388 unsigned int id; 389 390 assert(IS_IN_EL3()); 391 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 392 393 /* 394 * If the ID is special identifier corresponding to G1S or G1NS 395 * interrupt, then read the highest pending group 1 interrupt. 396 */ 397 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) { 398 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 399 } 400 401 return id; 402 } 403 404 /******************************************************************************* 405 * This function returns the type of the highest priority pending interrupt at 406 * the GIC cpu interface. The return values can be one of the following : 407 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 408 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 409 * 0 - 1019 : The interrupt type is secure Group 0. 410 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 411 * sufficient priority to be signaled 412 ******************************************************************************/ 413 unsigned int gicv3_get_pending_interrupt_type(void) 414 { 415 assert(IS_IN_EL3()); 416 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 417 } 418 419 /******************************************************************************* 420 * This function returns the type of the interrupt id depending upon the group 421 * this interrupt has been configured under by the interrupt controller i.e. 422 * group0 or group1 Secure / Non Secure. The return value can be one of the 423 * following : 424 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 425 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 426 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 427 * interrupt. 428 ******************************************************************************/ 429 unsigned int gicv3_get_interrupt_type(unsigned int id, unsigned int proc_num) 430 { 431 unsigned int igroup, grpmodr; 432 uintptr_t gicr_base; 433 434 assert(IS_IN_EL3()); 435 assert(gicv3_driver_data != NULL); 436 437 /* Ensure the parameters are valid */ 438 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID)); 439 assert(proc_num < gicv3_driver_data->rdistif_num); 440 441 /* All LPI interrupts are Group 1 non secure */ 442 if (id >= MIN_LPI_ID) { 443 return INTR_GROUP1NS; 444 } 445 446 /* Check interrupt ID */ 447 if (is_sgi_ppi(id)) { 448 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 449 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 450 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 451 igroup = gicr_get_igroupr(gicr_base, id); 452 grpmodr = gicr_get_igrpmodr(gicr_base, id); 453 } else { 454 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 455 assert(gicv3_driver_data->gicd_base != 0U); 456 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id); 457 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id); 458 } 459 460 /* 461 * If the IGROUP bit is set, then it is a Group 1 Non secure 462 * interrupt 463 */ 464 if (igroup != 0U) { 465 return INTR_GROUP1NS; 466 } 467 468 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 469 if (grpmodr != 0U) { 470 return INTR_GROUP1S; 471 } 472 473 /* Else it is a Group 0 Secure interrupt */ 474 return INTR_GROUP0; 475 } 476 477 /***************************************************************************** 478 * Function to save and disable the GIC ITS register context. The power 479 * management of GIC ITS is implementation-defined and this function doesn't 480 * save any memory structures required to support ITS. As the sequence to save 481 * this state is implementation defined, it should be executed in platform 482 * specific code. Calling this function alone and then powering down the GIC and 483 * ITS without implementing the aforementioned platform specific code will 484 * corrupt the ITS state. 485 * 486 * This function must be invoked after the GIC CPU interface is disabled. 487 *****************************************************************************/ 488 void gicv3_its_save_disable(uintptr_t gits_base, 489 gicv3_its_ctx_t * const its_ctx) 490 { 491 unsigned int i; 492 493 assert(gicv3_driver_data != NULL); 494 assert(IS_IN_EL3()); 495 assert(its_ctx != NULL); 496 assert(gits_base != 0U); 497 498 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 499 500 /* Disable the ITS */ 501 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 502 503 /* Wait for quiescent state */ 504 gits_wait_for_quiescent_bit(gits_base); 505 506 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 507 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 508 509 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 510 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 511 } 512 } 513 514 /***************************************************************************** 515 * Function to restore the GIC ITS register context. The power 516 * management of GIC ITS is implementation defined and this function doesn't 517 * restore any memory structures required to support ITS. The assumption is 518 * that these structures are in memory and are retained during system suspend. 519 * 520 * This must be invoked before the GIC CPU interface is enabled. 521 *****************************************************************************/ 522 void gicv3_its_restore(uintptr_t gits_base, 523 const gicv3_its_ctx_t * const its_ctx) 524 { 525 unsigned int i; 526 527 assert(gicv3_driver_data != NULL); 528 assert(IS_IN_EL3()); 529 assert(its_ctx != NULL); 530 assert(gits_base != 0U); 531 532 /* Assert that the GITS is disabled and quiescent */ 533 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 534 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U); 535 536 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 537 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 538 539 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 540 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 541 } 542 543 /* Restore the ITS CTLR but leave the ITS disabled */ 544 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 545 } 546 547 /***************************************************************************** 548 * Function to save the GIC Redistributor register context. This function 549 * must be invoked after CPU interface disable and prior to Distributor save. 550 *****************************************************************************/ 551 void gicv3_rdistif_save(unsigned int proc_num, 552 gicv3_redist_ctx_t * const rdist_ctx) 553 { 554 uintptr_t gicr_base; 555 unsigned int i, ppi_regs_num, regs_num; 556 557 assert(gicv3_driver_data != NULL); 558 assert(proc_num < gicv3_driver_data->rdistif_num); 559 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 560 assert(IS_IN_EL3()); 561 assert(rdist_ctx != NULL); 562 563 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 564 565 #if GIC_EXT_INTID 566 /* Calculate number of PPI registers */ 567 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 568 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 569 /* All other values except PPInum [0-2] are reserved */ 570 if (ppi_regs_num > 3U) { 571 ppi_regs_num = 1U; 572 } 573 #else 574 ppi_regs_num = 1U; 575 #endif 576 /* 577 * Wait for any write to GICR_CTLR to complete before trying to save any 578 * state. 579 */ 580 gicr_wait_for_pending_write(gicr_base); 581 582 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 583 584 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 585 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 586 587 /* 32 interrupt IDs per register */ 588 for (i = 0U; i < ppi_regs_num; ++i) { 589 SAVE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 590 SAVE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 591 SAVE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 592 SAVE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 593 SAVE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 594 } 595 596 /* 16 interrupt IDs per GICR_ICFGR register */ 597 regs_num = ppi_regs_num << 1; 598 for (i = 0U; i < regs_num; ++i) { 599 SAVE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 600 } 601 602 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 603 604 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 605 regs_num = ppi_regs_num << 3; 606 for (i = 0U; i < regs_num; ++i) { 607 rdist_ctx->gicr_ipriorityr[i] = 608 gicr_ipriorityr_read(gicr_base, i); 609 } 610 611 /* 612 * Call the pre-save hook that implements the IMP DEF sequence that may 613 * be required on some GIC implementations. As this may need to access 614 * the Redistributor registers, we pass it proc_num. 615 */ 616 gicv3_distif_pre_save(proc_num); 617 } 618 619 /***************************************************************************** 620 * Function to restore the GIC Redistributor register context. We disable 621 * LPI and per-cpu interrupts before we start restore of the Redistributor. 622 * This function must be invoked after Distributor restore but prior to 623 * CPU interface enable. The pending and active interrupts are restored 624 * after the interrupts are fully configured and enabled. 625 *****************************************************************************/ 626 void gicv3_rdistif_init_restore(unsigned int proc_num, 627 const gicv3_redist_ctx_t * const rdist_ctx) 628 { 629 uintptr_t gicr_base; 630 unsigned int i, ppi_regs_num, regs_num; 631 632 assert(gicv3_driver_data != NULL); 633 assert(proc_num < gicv3_driver_data->rdistif_num); 634 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 635 assert(IS_IN_EL3()); 636 assert(rdist_ctx != NULL); 637 638 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 639 640 #if GIC_EXT_INTID 641 /* Calculate number of PPI registers */ 642 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 643 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 644 /* All other values except PPInum [0-2] are reserved */ 645 if (ppi_regs_num > 3U) { 646 ppi_regs_num = 1U; 647 } 648 #else 649 ppi_regs_num = 1U; 650 #endif 651 /* Power on redistributor */ 652 gicv3_rdistif_on(proc_num); 653 654 /* 655 * Call the post-restore hook that implements the IMP DEF sequence that 656 * may be required on some GIC implementations. As this may need to 657 * access the Redistributor registers, we pass it proc_num. 658 */ 659 gicv3_distif_post_restore(proc_num); 660 661 /* 662 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 663 * This is a more scalable approach as it avoids clearing the enable 664 * bits in the GICD_CTLR. 665 */ 666 for (i = 0U; i < ppi_regs_num; ++i) { 667 gicr_write_icenabler(gicr_base, i, ~0U); 668 } 669 670 /* Wait for pending writes to GICR_ICENABLER */ 671 gicr_wait_for_pending_write(gicr_base); 672 673 /* 674 * Disable the LPIs to avoid unpredictable behavior when writing to 675 * GICR_PROPBASER and GICR_PENDBASER. 676 */ 677 gicr_write_ctlr(gicr_base, 678 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 679 680 /* Restore registers' content */ 681 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 682 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 683 684 /* 32 interrupt IDs per register */ 685 for (i = 0U; i < ppi_regs_num; ++i) { 686 RESTORE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 687 RESTORE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 688 } 689 690 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 691 regs_num = ppi_regs_num << 3; 692 for (i = 0U; i < regs_num; ++i) { 693 gicr_ipriorityr_write(gicr_base, i, 694 rdist_ctx->gicr_ipriorityr[i]); 695 } 696 697 /* 16 interrupt IDs per GICR_ICFGR register */ 698 regs_num = ppi_regs_num << 1; 699 for (i = 0U; i < regs_num; ++i) { 700 RESTORE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 701 } 702 703 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 704 705 /* Restore after group and priorities are set. 706 * 32 interrupt IDs per register 707 */ 708 for (i = 0U; i < ppi_regs_num; ++i) { 709 RESTORE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 710 RESTORE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 711 } 712 713 /* 714 * Wait for all writes to the Distributor to complete before enabling 715 * the SGI and (E)PPIs. 716 */ 717 gicr_wait_for_upstream_pending_write(gicr_base); 718 719 /* 32 interrupt IDs per GICR_ISENABLER register */ 720 for (i = 0U; i < ppi_regs_num; ++i) { 721 RESTORE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 722 } 723 724 /* 725 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 726 * the first write to GICR_CTLR was still in flight (this write only 727 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 728 * bit). 729 */ 730 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 731 gicr_wait_for_pending_write(gicr_base); 732 } 733 734 /***************************************************************************** 735 * Function to save the GIC Distributor register context. This function 736 * must be invoked after CPU interface disable and Redistributor save. 737 *****************************************************************************/ 738 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 739 { 740 assert(gicv3_driver_data != NULL); 741 assert(gicv3_driver_data->gicd_base != 0U); 742 assert(IS_IN_EL3()); 743 assert(dist_ctx != NULL); 744 745 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 746 unsigned int num_ints = gicv3_get_spi_limit(gicd_base); 747 #if GIC_EXT_INTID 748 unsigned int num_eints = gicv3_get_espi_limit(gicd_base); 749 #endif 750 751 /* Wait for pending write to complete */ 752 gicd_wait_for_pending_write(gicd_base); 753 754 /* Save the GICD_CTLR */ 755 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 756 757 /* Save GICD_IGROUPR for INTIDs 32 - 1019 */ 758 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 759 760 /* Save GICD_IGROUPRE for INTIDs 4096 - 5119 */ 761 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 762 763 /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */ 764 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 765 766 /* Save GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 767 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 768 769 /* Save GICD_ISPENDR for INTIDs 32 - 1019 */ 770 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 771 772 /* Save GICD_ISPENDRE for INTIDs 4096 - 5119 */ 773 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 774 775 /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */ 776 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 777 778 /* Save GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 779 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 780 781 /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */ 782 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 783 784 /* Save GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 785 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 786 787 /* Save GICD_ICFGR for INTIDs 32 - 1019 */ 788 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 789 790 /* Save GICD_ICFGRE for INTIDs 4096 - 5119 */ 791 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 792 793 /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */ 794 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 795 796 /* Save GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 797 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 798 799 /* Save GICD_NSACR for INTIDs 32 - 1019 */ 800 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 801 802 /* Save GICD_NSACRE for INTIDs 4096 - 5119 */ 803 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 804 805 /* Save GICD_IROUTER for INTIDs 32 - 1019 */ 806 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 807 808 /* Save GICD_IROUTERE for INTIDs 4096 - 5119 */ 809 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 810 811 /* 812 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 813 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 814 * driver. 815 */ 816 } 817 818 /***************************************************************************** 819 * Function to restore the GIC Distributor register context. We disable G0, G1S 820 * and G1NS interrupt groups before we start restore of the Distributor. This 821 * function must be invoked prior to Redistributor restore and CPU interface 822 * enable. The pending and active interrupts are restored after the interrupts 823 * are fully configured and enabled. 824 *****************************************************************************/ 825 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 826 { 827 assert(gicv3_driver_data != NULL); 828 assert(gicv3_driver_data->gicd_base != 0U); 829 assert(IS_IN_EL3()); 830 assert(dist_ctx != NULL); 831 832 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 833 834 /* 835 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 836 * the ARE_S bit. The Distributor might generate a system error 837 * otherwise. 838 */ 839 gicd_clr_ctlr(gicd_base, 840 CTLR_ENABLE_G0_BIT | 841 CTLR_ENABLE_G1S_BIT | 842 CTLR_ENABLE_G1NS_BIT, 843 RWP_TRUE); 844 845 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 846 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 847 848 unsigned int num_ints = gicv3_get_spi_limit(gicd_base); 849 #if GIC_EXT_INTID 850 unsigned int num_eints = gicv3_get_espi_limit(gicd_base); 851 #endif 852 /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */ 853 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 854 855 /* Restore GICD_IGROUPRE for INTIDs 4096 - 5119 */ 856 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 857 858 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */ 859 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 860 861 /* Restore GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 862 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 863 864 /* Restore GICD_ICFGR for INTIDs 32 - 1019 */ 865 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 866 867 /* Restore GICD_ICFGRE for INTIDs 4096 - 5119 */ 868 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 869 870 /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */ 871 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 872 873 /* Restore GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 874 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 875 876 /* Restore GICD_NSACR for INTIDs 32 - 1019 */ 877 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 878 879 /* Restore GICD_NSACRE for INTIDs 4096 - 5119 */ 880 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 881 882 /* Restore GICD_IROUTER for INTIDs 32 - 1019 */ 883 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 884 885 /* Restore GICD_IROUTERE for INTIDs 4096 - 5119 */ 886 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 887 888 /* 889 * Restore ISENABLER(E), ISPENDR(E) and ISACTIVER(E) after 890 * the interrupts are configured. 891 */ 892 893 /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */ 894 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 895 896 /* Restore GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 897 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 898 899 /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */ 900 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 901 902 /* Restore GICD_ISPENDRE for INTIDs 4096 - 5119 */ 903 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 904 905 /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */ 906 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 907 908 /* Restore GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 909 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 910 911 /* Restore the GICD_CTLR */ 912 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 913 gicd_wait_for_pending_write(gicd_base); 914 } 915 916 /******************************************************************************* 917 * This function gets the priority of the interrupt the processor is currently 918 * servicing. 919 ******************************************************************************/ 920 unsigned int gicv3_get_running_priority(void) 921 { 922 return (unsigned int)read_icc_rpr_el1(); 923 } 924 925 /******************************************************************************* 926 * This function checks if the interrupt identified by id is active (whether the 927 * state is either active, or active and pending). The proc_num is used if the 928 * interrupt is SGI or (E)PPI and programs the corresponding Redistributor 929 * interface. 930 ******************************************************************************/ 931 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) 932 { 933 assert(gicv3_driver_data != NULL); 934 assert(gicv3_driver_data->gicd_base != 0U); 935 assert(proc_num < gicv3_driver_data->rdistif_num); 936 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 937 938 /* Check interrupt ID */ 939 if (is_sgi_ppi(id)) { 940 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 941 return gicr_get_isactiver( 942 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 943 } 944 945 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 946 return gicd_get_isactiver(gicv3_driver_data->gicd_base, id); 947 } 948 949 /******************************************************************************* 950 * This function enables the interrupt identified by id. The proc_num 951 * is used if the interrupt is SGI or PPI, and programs the corresponding 952 * Redistributor interface. 953 ******************************************************************************/ 954 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) 955 { 956 assert(gicv3_driver_data != NULL); 957 assert(gicv3_driver_data->gicd_base != 0U); 958 assert(proc_num < gicv3_driver_data->rdistif_num); 959 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 960 961 /* 962 * Ensure that any shared variable updates depending on out of band 963 * interrupt trigger are observed before enabling interrupt. 964 */ 965 dsbishst(); 966 967 /* Check interrupt ID */ 968 if (is_sgi_ppi(id)) { 969 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 970 gicr_set_isenabler( 971 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 972 } else { 973 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 974 gicd_set_isenabler(gicv3_driver_data->gicd_base, id); 975 } 976 } 977 978 /******************************************************************************* 979 * This function disables the interrupt identified by id. The proc_num 980 * is used if the interrupt is SGI or PPI, and programs the corresponding 981 * Redistributor interface. 982 ******************************************************************************/ 983 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) 984 { 985 assert(gicv3_driver_data != NULL); 986 assert(gicv3_driver_data->gicd_base != 0U); 987 assert(proc_num < gicv3_driver_data->rdistif_num); 988 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 989 990 /* 991 * Disable interrupt, and ensure that any shared variable updates 992 * depending on out of band interrupt trigger are observed afterwards. 993 */ 994 995 /* Check interrupt ID */ 996 if (is_sgi_ppi(id)) { 997 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 998 gicr_set_icenabler( 999 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1000 1001 /* Write to clear enable requires waiting for pending writes */ 1002 gicr_wait_for_pending_write( 1003 gicv3_driver_data->rdistif_base_addrs[proc_num]); 1004 } else { 1005 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1006 gicd_set_icenabler(gicv3_driver_data->gicd_base, id); 1007 1008 /* Write to clear enable requires waiting for pending writes */ 1009 gicd_wait_for_pending_write(gicv3_driver_data->gicd_base); 1010 } 1011 1012 dsbishst(); 1013 } 1014 1015 /******************************************************************************* 1016 * This function sets the interrupt priority as supplied for the given interrupt 1017 * id. 1018 ******************************************************************************/ 1019 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 1020 unsigned int priority) 1021 { 1022 uintptr_t gicr_base; 1023 1024 assert(gicv3_driver_data != NULL); 1025 assert(gicv3_driver_data->gicd_base != 0U); 1026 assert(proc_num < gicv3_driver_data->rdistif_num); 1027 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1028 1029 /* Check interrupt ID */ 1030 if (is_sgi_ppi(id)) { 1031 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1032 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1033 gicr_set_ipriorityr(gicr_base, id, priority); 1034 } else { 1035 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1036 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority); 1037 } 1038 } 1039 1040 /******************************************************************************* 1041 * This function assigns group for the interrupt identified by id. The proc_num 1042 * is used if the interrupt is SGI or (E)PPI, and programs the corresponding 1043 * Redistributor interface. The group can be any of GICV3_INTR_GROUP* 1044 ******************************************************************************/ 1045 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 1046 unsigned int type) 1047 { 1048 bool igroup = false, grpmod = false; 1049 uintptr_t gicr_base; 1050 1051 assert(gicv3_driver_data != NULL); 1052 assert(gicv3_driver_data->gicd_base != 0U); 1053 assert(proc_num < gicv3_driver_data->rdistif_num); 1054 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1055 1056 switch (type) { 1057 case INTR_GROUP1S: 1058 igroup = false; 1059 grpmod = true; 1060 break; 1061 case INTR_GROUP0: 1062 igroup = false; 1063 grpmod = false; 1064 break; 1065 case INTR_GROUP1NS: 1066 igroup = true; 1067 grpmod = false; 1068 break; 1069 default: 1070 assert(false); 1071 break; 1072 } 1073 1074 /* Check interrupt ID */ 1075 if (is_sgi_ppi(id)) { 1076 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1077 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1078 1079 igroup ? gicr_set_igroupr(gicr_base, id) : 1080 gicr_clr_igroupr(gicr_base, id); 1081 grpmod ? gicr_set_igrpmodr(gicr_base, id) : 1082 gicr_clr_igrpmodr(gicr_base, id); 1083 } else { 1084 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1085 1086 /* Serialize read-modify-write to Distributor registers */ 1087 spin_lock(&gic_lock); 1088 1089 igroup ? gicd_set_igroupr(gicv3_driver_data->gicd_base, id) : 1090 gicd_clr_igroupr(gicv3_driver_data->gicd_base, id); 1091 grpmod ? gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id) : 1092 gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id); 1093 1094 spin_unlock(&gic_lock); 1095 } 1096 } 1097 1098 /******************************************************************************* 1099 * This function raises the specified SGI of the specified group. 1100 * 1101 * The target parameter must be a valid MPIDR in the system. 1102 ******************************************************************************/ 1103 void gicv3_raise_sgi(unsigned int sgi_num, gicv3_irq_group_t group, 1104 u_register_t target) 1105 { 1106 unsigned int tgt, aff3, aff2, aff1, aff0; 1107 uint64_t sgi_val; 1108 1109 /* Verify interrupt number is in the SGI range */ 1110 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID)); 1111 1112 /* Extract affinity fields from target */ 1113 aff0 = MPIDR_AFFLVL0_VAL(target); 1114 aff1 = MPIDR_AFFLVL1_VAL(target); 1115 aff2 = MPIDR_AFFLVL2_VAL(target); 1116 aff3 = MPIDR_AFFLVL3_VAL(target); 1117 1118 /* 1119 * Make target list from affinity 0, and ensure GICv3 SGI can target 1120 * this PE. 1121 */ 1122 assert(aff0 < GICV3_MAX_SGI_TARGETS); 1123 tgt = BIT_32(aff0); 1124 1125 /* Raise SGI to PE specified by its affinity */ 1126 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF, 1127 tgt); 1128 1129 /* 1130 * Ensure that any shared variable updates depending on out of band 1131 * interrupt trigger are observed before raising SGI. 1132 */ 1133 dsbishst(); 1134 1135 switch (group) { 1136 case GICV3_G0: 1137 write_icc_sgi0r_el1(sgi_val); 1138 break; 1139 case GICV3_G1NS: 1140 write_icc_asgi1r(sgi_val); 1141 break; 1142 case GICV3_G1S: 1143 write_icc_sgi1r(sgi_val); 1144 break; 1145 default: 1146 assert(false); 1147 break; 1148 } 1149 1150 isb(); 1151 } 1152 1153 /******************************************************************************* 1154 * This function sets the interrupt routing for the given (E)SPI interrupt id. 1155 * The interrupt routing is specified in routing mode and mpidr. 1156 * 1157 * The routing mode can be either of: 1158 * - GICV3_IRM_ANY 1159 * - GICV3_IRM_PE 1160 * 1161 * The mpidr is the affinity of the PE to which the interrupt will be routed, 1162 * and is ignored for routing mode GICV3_IRM_ANY. 1163 ******************************************************************************/ 1164 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr) 1165 { 1166 unsigned long long aff; 1167 uint64_t router; 1168 1169 assert(gicv3_driver_data != NULL); 1170 assert(gicv3_driver_data->gicd_base != 0U); 1171 1172 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE)); 1173 1174 assert(IS_SPI(id)); 1175 1176 aff = gicd_irouter_val_from_mpidr(mpidr, irm); 1177 gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff); 1178 1179 /* 1180 * In implementations that do not require 1 of N distribution of SPIs, 1181 * IRM might be RAZ/WI. Read back and verify IRM bit. 1182 */ 1183 if (irm == GICV3_IRM_ANY) { 1184 router = gicd_read_irouter(gicv3_driver_data->gicd_base, id); 1185 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) { 1186 ERROR("GICv3 implementation doesn't support routing ANY\n"); 1187 panic(); 1188 } 1189 } 1190 } 1191 1192 /******************************************************************************* 1193 * This function clears the pending status of an interrupt identified by id. 1194 * The proc_num is used if the interrupt is SGI or (E)PPI, and programs the 1195 * corresponding Redistributor interface. 1196 ******************************************************************************/ 1197 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num) 1198 { 1199 assert(gicv3_driver_data != NULL); 1200 assert(gicv3_driver_data->gicd_base != 0U); 1201 assert(proc_num < gicv3_driver_data->rdistif_num); 1202 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1203 1204 /* 1205 * Clear pending interrupt, and ensure that any shared variable updates 1206 * depending on out of band interrupt trigger are observed afterwards. 1207 */ 1208 1209 /* Check interrupt ID */ 1210 if (is_sgi_ppi(id)) { 1211 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1212 gicr_set_icpendr( 1213 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1214 } else { 1215 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1216 gicd_set_icpendr(gicv3_driver_data->gicd_base, id); 1217 } 1218 1219 dsbishst(); 1220 } 1221 1222 /******************************************************************************* 1223 * This function sets the pending status of an interrupt identified by id. 1224 * The proc_num is used if the interrupt is SGI or PPI and programs the 1225 * corresponding Redistributor interface. 1226 ******************************************************************************/ 1227 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num) 1228 { 1229 assert(gicv3_driver_data != NULL); 1230 assert(gicv3_driver_data->gicd_base != 0U); 1231 assert(proc_num < gicv3_driver_data->rdistif_num); 1232 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1233 1234 /* 1235 * Ensure that any shared variable updates depending on out of band 1236 * interrupt trigger are observed before setting interrupt pending. 1237 */ 1238 dsbishst(); 1239 1240 /* Check interrupt ID */ 1241 if (is_sgi_ppi(id)) { 1242 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1243 gicr_set_ispendr( 1244 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1245 } else { 1246 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1247 gicd_set_ispendr(gicv3_driver_data->gicd_base, id); 1248 } 1249 } 1250 1251 /******************************************************************************* 1252 * This function sets the PMR register with the supplied value. Returns the 1253 * original PMR. 1254 ******************************************************************************/ 1255 unsigned int gicv3_set_pmr(unsigned int mask) 1256 { 1257 unsigned int old_mask; 1258 1259 old_mask = (unsigned int)read_icc_pmr_el1(); 1260 1261 /* 1262 * Order memory updates w.r.t. PMR write, and ensure they're visible 1263 * before potential out of band interrupt trigger because of PMR update. 1264 * PMR system register writes are self-synchronizing, so no ISB required 1265 * thereafter. 1266 */ 1267 dsbishst(); 1268 write_icc_pmr_el1(mask); 1269 1270 return old_mask; 1271 } 1272 1273 /******************************************************************************* 1274 * This function delegates the responsibility of discovering the corresponding 1275 * Redistributor frames to each CPU itself. It is a modified version of 1276 * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform 1277 * unlike the previous way in which only the Primary CPU did the discovery of 1278 * all the Redistributor frames for every CPU. It also handles the scenario in 1279 * which the frames of various CPUs are not contiguous in physical memory. 1280 ******************************************************************************/ 1281 int gicv3_rdistif_probe(const uintptr_t gicr_frame) 1282 { 1283 u_register_t mpidr, mpidr_self; 1284 unsigned int proc_num; 1285 uint64_t typer_val; 1286 uintptr_t rdistif_base; 1287 bool gicr_frame_found = false; 1288 1289 assert(gicv3_driver_data->gicr_base == 0U); 1290 1291 if (plat_can_cmo()) { 1292 /* Ensure this function is called with Data Cache enabled */ 1293 #ifndef __aarch64__ 1294 assert((read_sctlr() & SCTLR_C_BIT) != 0U); 1295 #else 1296 assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U); 1297 #endif /* !__aarch64__ */ 1298 } 1299 1300 mpidr_self = read_mpidr_el1() & MPIDR_AFFINITY_MASK; 1301 rdistif_base = gicr_frame; 1302 do { 1303 typer_val = gicr_read_typer(rdistif_base); 1304 mpidr = mpidr_from_gicr_typer(typer_val); 1305 if (gicv3_driver_data->mpidr_to_core_pos != NULL) { 1306 proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr); 1307 } else { 1308 proc_num = (unsigned int)(typer_val >> 1309 TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK; 1310 } 1311 if (mpidr == mpidr_self) { 1312 /* The base address doesn't need to be initialized on 1313 * every warm boot. 1314 */ 1315 if (gicv3_driver_data->rdistif_base_addrs[proc_num] 1316 != 0U) { 1317 return 0; 1318 } 1319 gicv3_driver_data->rdistif_base_addrs[proc_num] = 1320 rdistif_base; 1321 gicr_frame_found = true; 1322 break; 1323 } 1324 rdistif_base += gicv3_redist_size(typer_val); 1325 } while ((typer_val & TYPER_LAST_BIT) == 0U); 1326 1327 if (!gicr_frame_found) { 1328 return -1; 1329 } 1330 1331 /* 1332 * Flush the driver data to ensure coherency. This is 1333 * not required if platform has HW_ASSISTED_COHERENCY 1334 * enabled. 1335 */ 1336 #if !HW_ASSISTED_COHERENCY 1337 /* 1338 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 1339 */ 1340 flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]), 1341 sizeof(*(gicv3_driver_data->rdistif_base_addrs))); 1342 #endif 1343 return 0; /* Found matching GICR frame */ 1344 } 1345 1346 /****************************************************************************** 1347 * This function checks the interrupt ID and returns true for SGIs and (E)PPIs 1348 * and false for (E)SPIs IDs. 1349 *****************************************************************************/ 1350 static bool is_sgi_ppi(unsigned int id) 1351 { 1352 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 1353 if (IS_SGI_PPI(id)) { 1354 return true; 1355 } 1356 1357 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 1358 if (IS_SPI(id)) { 1359 return false; 1360 } 1361 1362 assert(false); 1363 panic(); 1364 } 1365