1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/interrupt_props.h> 13 #include <drivers/arm/gicv3.h> 14 #include <lib/spinlock.h> 15 16 #include "gicv3_private.h" 17 18 const gicv3_driver_data_t *gicv3_driver_data; 19 static unsigned int gicv2_compat; 20 21 /* 22 * Spinlock to guard registers needing read-modify-write. APIs protected by this 23 * spinlock are used either at boot time (when only a single CPU is active), or 24 * when the system is fully coherent. 25 */ 26 static spinlock_t gic_lock; 27 28 /* 29 * Redistributor power operations are weakly bound so that they can be 30 * overridden 31 */ 32 #pragma weak gicv3_rdistif_off 33 #pragma weak gicv3_rdistif_on 34 35 36 /* Helper macros to save and restore GICD registers to and from the context */ 37 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 38 do { \ 39 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \ 40 int_id += (1U << REG##_SHIFT)) { \ 41 gicd_write_##reg(base, int_id, \ 42 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT]); \ 43 } \ 44 } while (false) 45 46 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 47 do { \ 48 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \ 49 int_id += (1U << REG##_SHIFT)) { \ 50 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT] =\ 51 gicd_read_##reg(base, int_id); \ 52 } \ 53 } while (false) 54 55 56 /******************************************************************************* 57 * This function initialises the ARM GICv3 driver in EL3 with provided platform 58 * inputs. 59 ******************************************************************************/ 60 void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 61 { 62 unsigned int gic_version; 63 64 assert(plat_driver_data != NULL); 65 assert(plat_driver_data->gicd_base != 0U); 66 assert(plat_driver_data->gicr_base != 0U); 67 assert(plat_driver_data->rdistif_num != 0U); 68 assert(plat_driver_data->rdistif_base_addrs != NULL); 69 70 assert(IS_IN_EL3()); 71 72 assert(plat_driver_data->interrupt_props_num > 0 ? 73 plat_driver_data->interrupt_props != NULL : 1); 74 75 /* Check for system register support */ 76 #ifdef AARCH32 77 assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); 78 #else 79 assert((read_id_aa64pfr0_el1() & 80 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U); 81 #endif /* AARCH32 */ 82 83 /* The GIC version should be 3.0 */ 84 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 85 gic_version >>= PIDR2_ARCH_REV_SHIFT; 86 gic_version &= PIDR2_ARCH_REV_MASK; 87 assert(gic_version == ARCH_REV_GICV3); 88 89 /* 90 * Find out whether the GIC supports the GICv2 compatibility mode. The 91 * ARE_S bit resets to 0 if supported 92 */ 93 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 94 gicv2_compat >>= CTLR_ARE_S_SHIFT; 95 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); 96 97 /* 98 * Find the base address of each implemented Redistributor interface. 99 * The number of interfaces should be equal to the number of CPUs in the 100 * system. The memory for saving these addresses has to be allocated by 101 * the platform port 102 */ 103 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 104 plat_driver_data->rdistif_num, 105 plat_driver_data->gicr_base, 106 plat_driver_data->mpidr_to_core_pos); 107 108 gicv3_driver_data = plat_driver_data; 109 110 /* 111 * The GIC driver data is initialized by the primary CPU with caches 112 * enabled. When the secondary CPU boots up, it initializes the 113 * GICC/GICR interface with the caches disabled. Hence flush the 114 * driver data to ensure coherency. This is not required if the 115 * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY 116 * enabled. 117 */ 118 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 119 flush_dcache_range((uintptr_t) &gicv3_driver_data, 120 sizeof(gicv3_driver_data)); 121 flush_dcache_range((uintptr_t) gicv3_driver_data, 122 sizeof(*gicv3_driver_data)); 123 #endif 124 125 INFO("GICv3 %s legacy support detected." 126 " ARM GICV3 driver initialized in EL3\n", 127 gicv2_compat ? "with" : "without"); 128 } 129 130 /******************************************************************************* 131 * This function initialises the GIC distributor interface based upon the data 132 * provided by the platform while initialising the driver. 133 ******************************************************************************/ 134 void __init gicv3_distif_init(void) 135 { 136 unsigned int bitmap = 0; 137 138 assert(gicv3_driver_data != NULL); 139 assert(gicv3_driver_data->gicd_base != 0U); 140 141 assert(IS_IN_EL3()); 142 143 /* 144 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 145 * the ARE_S bit. The Distributor might generate a system error 146 * otherwise. 147 */ 148 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 149 CTLR_ENABLE_G0_BIT | 150 CTLR_ENABLE_G1S_BIT | 151 CTLR_ENABLE_G1NS_BIT, 152 RWP_TRUE); 153 154 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 155 gicd_set_ctlr(gicv3_driver_data->gicd_base, 156 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 157 158 /* Set the default attribute of all SPIs */ 159 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); 160 161 bitmap = gicv3_secure_spis_config_props( 162 gicv3_driver_data->gicd_base, 163 gicv3_driver_data->interrupt_props, 164 gicv3_driver_data->interrupt_props_num); 165 166 /* Enable the secure SPIs now that they have been configured */ 167 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 168 } 169 170 /******************************************************************************* 171 * This function initialises the GIC Redistributor interface of the calling CPU 172 * (identified by the 'proc_num' parameter) based upon the data provided by the 173 * platform while initialising the driver. 174 ******************************************************************************/ 175 void gicv3_rdistif_init(unsigned int proc_num) 176 { 177 uintptr_t gicr_base; 178 unsigned int bitmap = 0U; 179 uint32_t ctlr; 180 181 assert(gicv3_driver_data != NULL); 182 assert(proc_num < gicv3_driver_data->rdistif_num); 183 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 184 assert(gicv3_driver_data->gicd_base != 0U); 185 186 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base); 187 assert((ctlr & CTLR_ARE_S_BIT) != 0U); 188 189 assert(IS_IN_EL3()); 190 191 /* Power on redistributor */ 192 gicv3_rdistif_on(proc_num); 193 194 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 195 196 /* Set the default attribute of all SGIs and PPIs */ 197 gicv3_ppi_sgi_config_defaults(gicr_base); 198 199 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, 200 gicv3_driver_data->interrupt_props, 201 gicv3_driver_data->interrupt_props_num); 202 203 /* Enable interrupt groups as required, if not already */ 204 if ((ctlr & bitmap) != bitmap) 205 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 206 } 207 208 /******************************************************************************* 209 * Functions to perform power operations on GIC Redistributor 210 ******************************************************************************/ 211 void gicv3_rdistif_off(unsigned int proc_num) 212 { 213 return; 214 } 215 216 void gicv3_rdistif_on(unsigned int proc_num) 217 { 218 return; 219 } 220 221 /******************************************************************************* 222 * This function enables the GIC CPU interface of the calling CPU using only 223 * system register accesses. 224 ******************************************************************************/ 225 void gicv3_cpuif_enable(unsigned int proc_num) 226 { 227 uintptr_t gicr_base; 228 unsigned int scr_el3; 229 unsigned int icc_sre_el3; 230 231 assert(gicv3_driver_data != NULL); 232 assert(proc_num < gicv3_driver_data->rdistif_num); 233 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 234 assert(IS_IN_EL3()); 235 236 /* Mark the connected core as awake */ 237 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 238 gicv3_rdistif_mark_core_awake(gicr_base); 239 240 /* Disable the legacy interrupt bypass */ 241 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 242 243 /* 244 * Enable system register access for EL3 and allow lower exception 245 * levels to configure the same for themselves. If the legacy mode is 246 * not supported, the SRE bit is RAO/WI 247 */ 248 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 249 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 250 251 scr_el3 = (uint32_t) read_scr_el3(); 252 253 /* 254 * Switch to NS state to write Non secure ICC_SRE_EL1 and 255 * ICC_SRE_EL2 registers. 256 */ 257 write_scr_el3(scr_el3 | SCR_NS_BIT); 258 isb(); 259 260 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 261 write_icc_sre_el1(ICC_SRE_SRE_BIT); 262 isb(); 263 264 /* Switch to secure state. */ 265 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 266 isb(); 267 268 /* Program the idle priority in the PMR */ 269 write_icc_pmr_el1(GIC_PRI_MASK); 270 271 /* Enable Group0 interrupts */ 272 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 273 274 /* Enable Group1 Secure interrupts */ 275 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 276 IGRPEN1_EL3_ENABLE_G1S_BIT); 277 278 /* Write the secure ICC_SRE_EL1 register */ 279 write_icc_sre_el1(ICC_SRE_SRE_BIT); 280 isb(); 281 } 282 283 /******************************************************************************* 284 * This function disables the GIC CPU interface of the calling CPU using 285 * only system register accesses. 286 ******************************************************************************/ 287 void gicv3_cpuif_disable(unsigned int proc_num) 288 { 289 uintptr_t gicr_base; 290 291 assert(gicv3_driver_data != NULL); 292 assert(proc_num < gicv3_driver_data->rdistif_num); 293 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 294 295 assert(IS_IN_EL3()); 296 297 /* Disable legacy interrupt bypass */ 298 write_icc_sre_el3(read_icc_sre_el3() | 299 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 300 301 /* Disable Group0 interrupts */ 302 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 303 ~IGRPEN1_EL1_ENABLE_G0_BIT); 304 305 /* Disable Group1 Secure and Non-Secure interrupts */ 306 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 307 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 308 IGRPEN1_EL3_ENABLE_G1S_BIT)); 309 310 /* Synchronise accesses to group enable registers */ 311 isb(); 312 313 /* Mark the connected core as asleep */ 314 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 315 gicv3_rdistif_mark_core_asleep(gicr_base); 316 } 317 318 /******************************************************************************* 319 * This function returns the id of the highest priority pending interrupt at 320 * the GIC cpu interface. 321 ******************************************************************************/ 322 unsigned int gicv3_get_pending_interrupt_id(void) 323 { 324 unsigned int id; 325 326 assert(IS_IN_EL3()); 327 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 328 329 /* 330 * If the ID is special identifier corresponding to G1S or G1NS 331 * interrupt, then read the highest pending group 1 interrupt. 332 */ 333 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) 334 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 335 336 return id; 337 } 338 339 /******************************************************************************* 340 * This function returns the type of the highest priority pending interrupt at 341 * the GIC cpu interface. The return values can be one of the following : 342 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 343 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 344 * 0 - 1019 : The interrupt type is secure Group 0. 345 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 346 * sufficient priority to be signaled 347 ******************************************************************************/ 348 unsigned int gicv3_get_pending_interrupt_type(void) 349 { 350 assert(IS_IN_EL3()); 351 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 352 } 353 354 /******************************************************************************* 355 * This function returns the type of the interrupt id depending upon the group 356 * this interrupt has been configured under by the interrupt controller i.e. 357 * group0 or group1 Secure / Non Secure. The return value can be one of the 358 * following : 359 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 360 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 361 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 362 * interrupt. 363 ******************************************************************************/ 364 unsigned int gicv3_get_interrupt_type(unsigned int id, 365 unsigned int proc_num) 366 { 367 unsigned int igroup, grpmodr; 368 uintptr_t gicr_base; 369 370 assert(IS_IN_EL3()); 371 assert(gicv3_driver_data != NULL); 372 373 /* Ensure the parameters are valid */ 374 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID)); 375 assert(proc_num < gicv3_driver_data->rdistif_num); 376 377 /* All LPI interrupts are Group 1 non secure */ 378 if (id >= MIN_LPI_ID) 379 return INTR_GROUP1NS; 380 381 if (id < MIN_SPI_ID) { 382 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 383 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 384 igroup = gicr_get_igroupr0(gicr_base, id); 385 grpmodr = gicr_get_igrpmodr0(gicr_base, id); 386 } else { 387 assert(gicv3_driver_data->gicd_base != 0U); 388 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id); 389 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id); 390 } 391 392 /* 393 * If the IGROUP bit is set, then it is a Group 1 Non secure 394 * interrupt 395 */ 396 if (igroup != 0U) 397 return INTR_GROUP1NS; 398 399 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 400 if (grpmodr != 0U) 401 return INTR_GROUP1S; 402 403 /* Else it is a Group 0 Secure interrupt */ 404 return INTR_GROUP0; 405 } 406 407 /***************************************************************************** 408 * Function to save and disable the GIC ITS register context. The power 409 * management of GIC ITS is implementation-defined and this function doesn't 410 * save any memory structures required to support ITS. As the sequence to save 411 * this state is implementation defined, it should be executed in platform 412 * specific code. Calling this function alone and then powering down the GIC and 413 * ITS without implementing the aforementioned platform specific code will 414 * corrupt the ITS state. 415 * 416 * This function must be invoked after the GIC CPU interface is disabled. 417 *****************************************************************************/ 418 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx) 419 { 420 unsigned int i; 421 422 assert(gicv3_driver_data != NULL); 423 assert(IS_IN_EL3()); 424 assert(its_ctx != NULL); 425 assert(gits_base != 0U); 426 427 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 428 429 /* Disable the ITS */ 430 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & 431 (~GITS_CTLR_ENABLED_BIT)); 432 433 /* Wait for quiescent state */ 434 gits_wait_for_quiescent_bit(gits_base); 435 436 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 437 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 438 439 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++) 440 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 441 } 442 443 /***************************************************************************** 444 * Function to restore the GIC ITS register context. The power 445 * management of GIC ITS is implementation defined and this function doesn't 446 * restore any memory structures required to support ITS. The assumption is 447 * that these structures are in memory and are retained during system suspend. 448 * 449 * This must be invoked before the GIC CPU interface is enabled. 450 *****************************************************************************/ 451 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx) 452 { 453 unsigned int i; 454 455 assert(gicv3_driver_data != NULL); 456 assert(IS_IN_EL3()); 457 assert(its_ctx != NULL); 458 assert(gits_base != 0U); 459 460 /* Assert that the GITS is disabled and quiescent */ 461 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 462 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U); 463 464 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 465 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 466 467 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++) 468 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 469 470 /* Restore the ITS CTLR but leave the ITS disabled */ 471 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & 472 (~GITS_CTLR_ENABLED_BIT)); 473 } 474 475 /***************************************************************************** 476 * Function to save the GIC Redistributor register context. This function 477 * must be invoked after CPU interface disable and prior to Distributor save. 478 *****************************************************************************/ 479 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx) 480 { 481 uintptr_t gicr_base; 482 unsigned int int_id; 483 484 assert(gicv3_driver_data != NULL); 485 assert(proc_num < gicv3_driver_data->rdistif_num); 486 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 487 assert(IS_IN_EL3()); 488 assert(rdist_ctx != NULL); 489 490 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 491 492 /* 493 * Wait for any write to GICR_CTLR to complete before trying to save any 494 * state. 495 */ 496 gicr_wait_for_pending_write(gicr_base); 497 498 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 499 500 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 501 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 502 503 rdist_ctx->gicr_igroupr0 = gicr_read_igroupr0(gicr_base); 504 rdist_ctx->gicr_isenabler0 = gicr_read_isenabler0(gicr_base); 505 rdist_ctx->gicr_ispendr0 = gicr_read_ispendr0(gicr_base); 506 rdist_ctx->gicr_isactiver0 = gicr_read_isactiver0(gicr_base); 507 rdist_ctx->gicr_icfgr0 = gicr_read_icfgr0(gicr_base); 508 rdist_ctx->gicr_icfgr1 = gicr_read_icfgr1(gicr_base); 509 rdist_ctx->gicr_igrpmodr0 = gicr_read_igrpmodr0(gicr_base); 510 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 511 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 512 int_id += (1U << IPRIORITYR_SHIFT)) { 513 rdist_ctx->gicr_ipriorityr[(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT] = 514 gicr_read_ipriorityr(gicr_base, int_id); 515 } 516 517 518 /* 519 * Call the pre-save hook that implements the IMP DEF sequence that may 520 * be required on some GIC implementations. As this may need to access 521 * the Redistributor registers, we pass it proc_num. 522 */ 523 gicv3_distif_pre_save(proc_num); 524 } 525 526 /***************************************************************************** 527 * Function to restore the GIC Redistributor register context. We disable 528 * LPI and per-cpu interrupts before we start restore of the Redistributor. 529 * This function must be invoked after Distributor restore but prior to 530 * CPU interface enable. The pending and active interrupts are restored 531 * after the interrupts are fully configured and enabled. 532 *****************************************************************************/ 533 void gicv3_rdistif_init_restore(unsigned int proc_num, 534 const gicv3_redist_ctx_t * const rdist_ctx) 535 { 536 uintptr_t gicr_base; 537 unsigned int int_id; 538 539 assert(gicv3_driver_data != NULL); 540 assert(proc_num < gicv3_driver_data->rdistif_num); 541 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 542 assert(IS_IN_EL3()); 543 assert(rdist_ctx != NULL); 544 545 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 546 547 /* Power on redistributor */ 548 gicv3_rdistif_on(proc_num); 549 550 /* 551 * Call the post-restore hook that implements the IMP DEF sequence that 552 * may be required on some GIC implementations. As this may need to 553 * access the Redistributor registers, we pass it proc_num. 554 */ 555 gicv3_distif_post_restore(proc_num); 556 557 /* 558 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a 559 * more scalable approach as it avoids clearing the enable bits in the 560 * GICD_CTLR 561 */ 562 gicr_write_icenabler0(gicr_base, ~0U); 563 /* Wait for pending writes to GICR_ICENABLER */ 564 gicr_wait_for_pending_write(gicr_base); 565 566 /* 567 * Disable the LPIs to avoid unpredictable behavior when writing to 568 * GICR_PROPBASER and GICR_PENDBASER. 569 */ 570 gicr_write_ctlr(gicr_base, 571 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 572 573 /* Restore registers' content */ 574 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 575 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 576 577 gicr_write_igroupr0(gicr_base, rdist_ctx->gicr_igroupr0); 578 579 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 580 int_id += (1U << IPRIORITYR_SHIFT)) { 581 gicr_write_ipriorityr(gicr_base, int_id, 582 rdist_ctx->gicr_ipriorityr[ 583 (int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT]); 584 } 585 586 gicr_write_icfgr0(gicr_base, rdist_ctx->gicr_icfgr0); 587 gicr_write_icfgr1(gicr_base, rdist_ctx->gicr_icfgr1); 588 gicr_write_igrpmodr0(gicr_base, rdist_ctx->gicr_igrpmodr0); 589 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 590 591 /* Restore after group and priorities are set */ 592 gicr_write_ispendr0(gicr_base, rdist_ctx->gicr_ispendr0); 593 gicr_write_isactiver0(gicr_base, rdist_ctx->gicr_isactiver0); 594 595 /* 596 * Wait for all writes to the Distributor to complete before enabling 597 * the SGI and PPIs. 598 */ 599 gicr_wait_for_upstream_pending_write(gicr_base); 600 gicr_write_isenabler0(gicr_base, rdist_ctx->gicr_isenabler0); 601 602 /* 603 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 604 * the first write to GICR_CTLR was still in flight (this write only 605 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 606 * bit). 607 */ 608 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 609 gicr_wait_for_pending_write(gicr_base); 610 } 611 612 /***************************************************************************** 613 * Function to save the GIC Distributor register context. This function 614 * must be invoked after CPU interface disable and Redistributor save. 615 *****************************************************************************/ 616 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 617 { 618 unsigned int num_ints; 619 620 assert(gicv3_driver_data != NULL); 621 assert(gicv3_driver_data->gicd_base != 0U); 622 assert(IS_IN_EL3()); 623 assert(dist_ctx != NULL); 624 625 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 626 627 num_ints = gicd_read_typer(gicd_base); 628 num_ints &= TYPER_IT_LINES_NO_MASK; 629 num_ints = (num_ints + 1U) << 5; 630 631 assert(num_ints <= (MAX_SPI_ID + 1U)); 632 633 /* Wait for pending write to complete */ 634 gicd_wait_for_pending_write(gicd_base); 635 636 /* Save the GICD_CTLR */ 637 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 638 639 /* Save GICD_IGROUPR for INTIDs 32 - 1020 */ 640 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 641 642 /* Save GICD_ISENABLER for INT_IDs 32 - 1020 */ 643 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 644 645 /* Save GICD_ISPENDR for INTIDs 32 - 1020 */ 646 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 647 648 /* Save GICD_ISACTIVER for INTIDs 32 - 1020 */ 649 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 650 651 /* Save GICD_IPRIORITYR for INTIDs 32 - 1020 */ 652 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 653 654 /* Save GICD_ICFGR for INTIDs 32 - 1020 */ 655 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 656 657 /* Save GICD_IGRPMODR for INTIDs 32 - 1020 */ 658 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 659 660 /* Save GICD_NSACR for INTIDs 32 - 1020 */ 661 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 662 663 /* Save GICD_IROUTER for INTIDs 32 - 1024 */ 664 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 665 666 /* 667 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 668 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 669 * driver. 670 */ 671 } 672 673 /***************************************************************************** 674 * Function to restore the GIC Distributor register context. We disable G0, G1S 675 * and G1NS interrupt groups before we start restore of the Distributor. This 676 * function must be invoked prior to Redistributor restore and CPU interface 677 * enable. The pending and active interrupts are restored after the interrupts 678 * are fully configured and enabled. 679 *****************************************************************************/ 680 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 681 { 682 unsigned int num_ints = 0U; 683 684 assert(gicv3_driver_data != NULL); 685 assert(gicv3_driver_data->gicd_base != 0U); 686 assert(IS_IN_EL3()); 687 assert(dist_ctx != NULL); 688 689 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 690 691 /* 692 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 693 * the ARE_S bit. The Distributor might generate a system error 694 * otherwise. 695 */ 696 gicd_clr_ctlr(gicd_base, 697 CTLR_ENABLE_G0_BIT | 698 CTLR_ENABLE_G1S_BIT | 699 CTLR_ENABLE_G1NS_BIT, 700 RWP_TRUE); 701 702 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 703 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 704 705 num_ints = gicd_read_typer(gicd_base); 706 num_ints &= TYPER_IT_LINES_NO_MASK; 707 num_ints = (num_ints + 1U) << 5; 708 709 assert(num_ints <= (MAX_SPI_ID + 1U)); 710 711 /* Restore GICD_IGROUPR for INTIDs 32 - 1020 */ 712 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 713 714 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1020 */ 715 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 716 717 /* Restore GICD_ICFGR for INTIDs 32 - 1020 */ 718 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 719 720 /* Restore GICD_IGRPMODR for INTIDs 32 - 1020 */ 721 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 722 723 /* Restore GICD_NSACR for INTIDs 32 - 1020 */ 724 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 725 726 /* Restore GICD_IROUTER for INTIDs 32 - 1020 */ 727 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 728 729 /* 730 * Restore ISENABLER, ISPENDR and ISACTIVER after the interrupts are 731 * configured. 732 */ 733 734 /* Restore GICD_ISENABLER for INT_IDs 32 - 1020 */ 735 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 736 737 /* Restore GICD_ISPENDR for INTIDs 32 - 1020 */ 738 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 739 740 /* Restore GICD_ISACTIVER for INTIDs 32 - 1020 */ 741 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 742 743 /* Restore the GICD_CTLR */ 744 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 745 gicd_wait_for_pending_write(gicd_base); 746 747 } 748 749 /******************************************************************************* 750 * This function gets the priority of the interrupt the processor is currently 751 * servicing. 752 ******************************************************************************/ 753 unsigned int gicv3_get_running_priority(void) 754 { 755 return (unsigned int)read_icc_rpr_el1(); 756 } 757 758 /******************************************************************************* 759 * This function checks if the interrupt identified by id is active (whether the 760 * state is either active, or active and pending). The proc_num is used if the 761 * interrupt is SGI or PPI and programs the corresponding Redistributor 762 * interface. 763 ******************************************************************************/ 764 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) 765 { 766 unsigned int value; 767 768 assert(gicv3_driver_data != NULL); 769 assert(gicv3_driver_data->gicd_base != 0U); 770 assert(proc_num < gicv3_driver_data->rdistif_num); 771 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 772 assert(id <= MAX_SPI_ID); 773 774 if (id < MIN_SPI_ID) { 775 /* For SGIs and PPIs */ 776 value = gicr_get_isactiver0( 777 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 778 } else { 779 value = gicd_get_isactiver(gicv3_driver_data->gicd_base, id); 780 } 781 782 return value; 783 } 784 785 /******************************************************************************* 786 * This function enables the interrupt identified by id. The proc_num 787 * is used if the interrupt is SGI or PPI, and programs the corresponding 788 * Redistributor interface. 789 ******************************************************************************/ 790 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) 791 { 792 assert(gicv3_driver_data != NULL); 793 assert(gicv3_driver_data->gicd_base != 0U); 794 assert(proc_num < gicv3_driver_data->rdistif_num); 795 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 796 assert(id <= MAX_SPI_ID); 797 798 /* 799 * Ensure that any shared variable updates depending on out of band 800 * interrupt trigger are observed before enabling interrupt. 801 */ 802 dsbishst(); 803 if (id < MIN_SPI_ID) { 804 /* For SGIs and PPIs */ 805 gicr_set_isenabler0( 806 gicv3_driver_data->rdistif_base_addrs[proc_num], 807 id); 808 } else { 809 gicd_set_isenabler(gicv3_driver_data->gicd_base, id); 810 } 811 } 812 813 /******************************************************************************* 814 * This function disables the interrupt identified by id. The proc_num 815 * is used if the interrupt is SGI or PPI, and programs the corresponding 816 * Redistributor interface. 817 ******************************************************************************/ 818 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) 819 { 820 assert(gicv3_driver_data != NULL); 821 assert(gicv3_driver_data->gicd_base != 0U); 822 assert(proc_num < gicv3_driver_data->rdistif_num); 823 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 824 assert(id <= MAX_SPI_ID); 825 826 /* 827 * Disable interrupt, and ensure that any shared variable updates 828 * depending on out of band interrupt trigger are observed afterwards. 829 */ 830 if (id < MIN_SPI_ID) { 831 /* For SGIs and PPIs */ 832 gicr_set_icenabler0( 833 gicv3_driver_data->rdistif_base_addrs[proc_num], 834 id); 835 836 /* Write to clear enable requires waiting for pending writes */ 837 gicr_wait_for_pending_write( 838 gicv3_driver_data->rdistif_base_addrs[proc_num]); 839 } else { 840 gicd_set_icenabler(gicv3_driver_data->gicd_base, id); 841 842 /* Write to clear enable requires waiting for pending writes */ 843 gicd_wait_for_pending_write(gicv3_driver_data->gicd_base); 844 } 845 846 dsbishst(); 847 } 848 849 /******************************************************************************* 850 * This function sets the interrupt priority as supplied for the given interrupt 851 * id. 852 ******************************************************************************/ 853 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 854 unsigned int priority) 855 { 856 uintptr_t gicr_base; 857 858 assert(gicv3_driver_data != NULL); 859 assert(gicv3_driver_data->gicd_base != 0U); 860 assert(proc_num < gicv3_driver_data->rdistif_num); 861 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 862 assert(id <= MAX_SPI_ID); 863 864 if (id < MIN_SPI_ID) { 865 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 866 gicr_set_ipriorityr(gicr_base, id, priority); 867 } else { 868 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority); 869 } 870 } 871 872 /******************************************************************************* 873 * This function assigns group for the interrupt identified by id. The proc_num 874 * is used if the interrupt is SGI or PPI, and programs the corresponding 875 * Redistributor interface. The group can be any of GICV3_INTR_GROUP* 876 ******************************************************************************/ 877 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 878 unsigned int type) 879 { 880 bool igroup = false, grpmod = false; 881 uintptr_t gicr_base; 882 883 assert(gicv3_driver_data != NULL); 884 assert(gicv3_driver_data->gicd_base != 0U); 885 assert(proc_num < gicv3_driver_data->rdistif_num); 886 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 887 888 switch (type) { 889 case INTR_GROUP1S: 890 igroup = false; 891 grpmod = true; 892 break; 893 case INTR_GROUP0: 894 igroup = false; 895 grpmod = false; 896 break; 897 case INTR_GROUP1NS: 898 igroup = true; 899 grpmod = false; 900 break; 901 default: 902 assert(false); 903 break; 904 } 905 906 if (id < MIN_SPI_ID) { 907 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 908 if (igroup) 909 gicr_set_igroupr0(gicr_base, id); 910 else 911 gicr_clr_igroupr0(gicr_base, id); 912 913 if (grpmod) 914 gicr_set_igrpmodr0(gicr_base, id); 915 else 916 gicr_clr_igrpmodr0(gicr_base, id); 917 } else { 918 /* Serialize read-modify-write to Distributor registers */ 919 spin_lock(&gic_lock); 920 if (igroup) 921 gicd_set_igroupr(gicv3_driver_data->gicd_base, id); 922 else 923 gicd_clr_igroupr(gicv3_driver_data->gicd_base, id); 924 925 if (grpmod) 926 gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id); 927 else 928 gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id); 929 spin_unlock(&gic_lock); 930 } 931 } 932 933 /******************************************************************************* 934 * This function raises the specified Secure Group 0 SGI. 935 * 936 * The target parameter must be a valid MPIDR in the system. 937 ******************************************************************************/ 938 void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target) 939 { 940 unsigned int tgt, aff3, aff2, aff1, aff0; 941 uint64_t sgi_val; 942 943 /* Verify interrupt number is in the SGI range */ 944 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID)); 945 946 /* Extract affinity fields from target */ 947 aff0 = MPIDR_AFFLVL0_VAL(target); 948 aff1 = MPIDR_AFFLVL1_VAL(target); 949 aff2 = MPIDR_AFFLVL2_VAL(target); 950 aff3 = MPIDR_AFFLVL3_VAL(target); 951 952 /* 953 * Make target list from affinity 0, and ensure GICv3 SGI can target 954 * this PE. 955 */ 956 assert(aff0 < GICV3_MAX_SGI_TARGETS); 957 tgt = BIT_32(aff0); 958 959 /* Raise SGI to PE specified by its affinity */ 960 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF, 961 tgt); 962 963 /* 964 * Ensure that any shared variable updates depending on out of band 965 * interrupt trigger are observed before raising SGI. 966 */ 967 dsbishst(); 968 write_icc_sgi0r_el1(sgi_val); 969 isb(); 970 } 971 972 /******************************************************************************* 973 * This function sets the interrupt routing for the given SPI interrupt id. 974 * The interrupt routing is specified in routing mode and mpidr. 975 * 976 * The routing mode can be either of: 977 * - GICV3_IRM_ANY 978 * - GICV3_IRM_PE 979 * 980 * The mpidr is the affinity of the PE to which the interrupt will be routed, 981 * and is ignored for routing mode GICV3_IRM_ANY. 982 ******************************************************************************/ 983 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr) 984 { 985 unsigned long long aff; 986 uint64_t router; 987 988 assert(gicv3_driver_data != NULL); 989 assert(gicv3_driver_data->gicd_base != 0U); 990 991 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE)); 992 assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID)); 993 994 aff = gicd_irouter_val_from_mpidr(mpidr, irm); 995 gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff); 996 997 /* 998 * In implementations that do not require 1 of N distribution of SPIs, 999 * IRM might be RAZ/WI. Read back and verify IRM bit. 1000 */ 1001 if (irm == GICV3_IRM_ANY) { 1002 router = gicd_read_irouter(gicv3_driver_data->gicd_base, id); 1003 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) { 1004 ERROR("GICv3 implementation doesn't support routing ANY\n"); 1005 panic(); 1006 } 1007 } 1008 } 1009 1010 /******************************************************************************* 1011 * This function clears the pending status of an interrupt identified by id. 1012 * The proc_num is used if the interrupt is SGI or PPI, and programs the 1013 * corresponding Redistributor interface. 1014 ******************************************************************************/ 1015 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num) 1016 { 1017 assert(gicv3_driver_data != NULL); 1018 assert(gicv3_driver_data->gicd_base != 0U); 1019 assert(proc_num < gicv3_driver_data->rdistif_num); 1020 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1021 1022 /* 1023 * Clear pending interrupt, and ensure that any shared variable updates 1024 * depending on out of band interrupt trigger are observed afterwards. 1025 */ 1026 if (id < MIN_SPI_ID) { 1027 /* For SGIs and PPIs */ 1028 gicr_set_icpendr0(gicv3_driver_data->rdistif_base_addrs[proc_num], 1029 id); 1030 } else { 1031 gicd_set_icpendr(gicv3_driver_data->gicd_base, id); 1032 } 1033 dsbishst(); 1034 } 1035 1036 /******************************************************************************* 1037 * This function sets the pending status of an interrupt identified by id. 1038 * The proc_num is used if the interrupt is SGI or PPI and programs the 1039 * corresponding Redistributor interface. 1040 ******************************************************************************/ 1041 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num) 1042 { 1043 assert(gicv3_driver_data != NULL); 1044 assert(gicv3_driver_data->gicd_base != 0U); 1045 assert(proc_num < gicv3_driver_data->rdistif_num); 1046 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1047 1048 /* 1049 * Ensure that any shared variable updates depending on out of band 1050 * interrupt trigger are observed before setting interrupt pending. 1051 */ 1052 dsbishst(); 1053 if (id < MIN_SPI_ID) { 1054 /* For SGIs and PPIs */ 1055 gicr_set_ispendr0(gicv3_driver_data->rdistif_base_addrs[proc_num], 1056 id); 1057 } else { 1058 gicd_set_ispendr(gicv3_driver_data->gicd_base, id); 1059 } 1060 } 1061 1062 /******************************************************************************* 1063 * This function sets the PMR register with the supplied value. Returns the 1064 * original PMR. 1065 ******************************************************************************/ 1066 unsigned int gicv3_set_pmr(unsigned int mask) 1067 { 1068 unsigned int old_mask; 1069 1070 old_mask = (uint32_t) read_icc_pmr_el1(); 1071 1072 /* 1073 * Order memory updates w.r.t. PMR write, and ensure they're visible 1074 * before potential out of band interrupt trigger because of PMR update. 1075 * PMR system register writes are self-synchronizing, so no ISB required 1076 * thereafter. 1077 */ 1078 dsbishst(); 1079 write_icc_pmr_el1(mask); 1080 1081 return old_mask; 1082 } 1083