1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <common/interrupt_props.h> 14 #include <drivers/arm/gic600_multichip.h> 15 #include <drivers/arm/gicv3.h> 16 #include <lib/spinlock.h> 17 #include <plat/common/platform.h> 18 19 #include "gicv3_private.h" 20 21 const gicv3_driver_data_t *gicv3_driver_data; 22 23 /* 24 * Spinlock to guard registers needing read-modify-write. APIs protected by this 25 * spinlock are used either at boot time (when only a single CPU is active), or 26 * when the system is fully coherent. 27 */ 28 static spinlock_t gic_lock; 29 30 /* 31 * Redistributor power operations are weakly bound so that they can be 32 * overridden 33 */ 34 #pragma weak gicv3_rdistif_off 35 #pragma weak gicv3_rdistif_on 36 37 /* Check for valid SGI/PPI or SPI interrupt ID */ 38 static bool is_valid_interrupt(unsigned int id); 39 40 /* 41 * Helper macros to save and restore GICR and GICD registers 42 * corresponding to their numbers to and from the context 43 */ 44 #define RESTORE_GICR_REG(base, ctx, name, i) \ 45 gicr_write_##name((base), (i), (ctx)->gicr_##name[(i)]) 46 47 #define SAVE_GICR_REG(base, ctx, name, i) \ 48 (ctx)->gicr_##name[(i)] = gicr_read_##name((base), (i)) 49 50 /* Helper macros to save and restore GICD registers to and from the context */ 51 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 52 do { \ 53 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 54 int_id += (1U << REG##R_SHIFT)) { \ 55 gicd_write_##reg((base), int_id, \ 56 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 57 REG##R_SHIFT]); \ 58 } \ 59 } while (false) 60 61 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 62 do { \ 63 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 64 int_id += (1U << REG##R_SHIFT)) { \ 65 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 66 REG##R_SHIFT] = gicd_read_##reg((base), int_id); \ 67 } \ 68 } while (false) 69 70 #if GIC_EXT_INTID 71 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 72 do { \ 73 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 74 int_id += (1U << REG##R_SHIFT)) { \ 75 gicd_write_##reg((base), int_id, \ 76 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ 77 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ 78 >> REG##R_SHIFT]); \ 79 } \ 80 } while (false) 81 82 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 83 do { \ 84 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 85 int_id += (1U << REG##R_SHIFT)) { \ 86 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ 87 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ 88 >> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\ 89 } \ 90 } while (false) 91 #else 92 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) 93 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) 94 #endif /* GIC_EXT_INTID */ 95 96 /******************************************************************************* 97 * This function initialises the ARM GICv3 driver in EL3 with provided platform 98 * inputs. 99 ******************************************************************************/ 100 void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 101 { 102 unsigned int gic_version; 103 unsigned int gicv2_compat; 104 105 assert(plat_driver_data != NULL); 106 assert(plat_driver_data->gicd_base != 0U); 107 assert(plat_driver_data->rdistif_num != 0U); 108 assert(plat_driver_data->rdistif_base_addrs != NULL); 109 110 assert(IS_IN_EL3()); 111 112 assert((plat_driver_data->interrupt_props_num != 0U) ? 113 (plat_driver_data->interrupt_props != NULL) : 1); 114 115 /* Check for system register support */ 116 #ifndef __aarch64__ 117 assert((read_id_pfr1() & 118 (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); 119 #else 120 assert((read_id_aa64pfr0_el1() & 121 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U); 122 #endif /* !__aarch64__ */ 123 124 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 125 gic_version >>= PIDR2_ARCH_REV_SHIFT; 126 gic_version &= PIDR2_ARCH_REV_MASK; 127 128 /* Check GIC version */ 129 #if !GIC_ENABLE_V4_EXTN 130 assert(gic_version == ARCH_REV_GICV3); 131 #endif 132 /* 133 * Find out whether the GIC supports the GICv2 compatibility mode. 134 * The ARE_S bit resets to 0 if supported 135 */ 136 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 137 gicv2_compat >>= CTLR_ARE_S_SHIFT; 138 gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK; 139 140 if (plat_driver_data->gicr_base != 0U) { 141 /* 142 * Find the base address of each implemented Redistributor interface. 143 * The number of interfaces should be equal to the number of CPUs in the 144 * system. The memory for saving these addresses has to be allocated by 145 * the platform port 146 */ 147 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 148 plat_driver_data->rdistif_num, 149 plat_driver_data->gicr_base, 150 plat_driver_data->mpidr_to_core_pos); 151 #if !HW_ASSISTED_COHERENCY 152 /* 153 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 154 */ 155 flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs), 156 plat_driver_data->rdistif_num * 157 sizeof(*(plat_driver_data->rdistif_base_addrs))); 158 #endif 159 } 160 gicv3_driver_data = plat_driver_data; 161 162 /* 163 * The GIC driver data is initialized by the primary CPU with caches 164 * enabled. When the secondary CPU boots up, it initializes the 165 * GICC/GICR interface with the caches disabled. Hence flush the 166 * driver data to ensure coherency. This is not required if the 167 * platform has HW_ASSISTED_COHERENCY enabled. 168 */ 169 #if !HW_ASSISTED_COHERENCY 170 flush_dcache_range((uintptr_t)&gicv3_driver_data, 171 sizeof(gicv3_driver_data)); 172 flush_dcache_range((uintptr_t)gicv3_driver_data, 173 sizeof(*gicv3_driver_data)); 174 #endif 175 gicv3_check_erratas_applies(plat_driver_data->gicd_base); 176 177 INFO("GICv%u with%s legacy support detected.\n", gic_version, 178 (gicv2_compat == 0U) ? "" : "out"); 179 INFO("ARM GICv%u driver initialized in EL3\n", gic_version); 180 } 181 182 /******************************************************************************* 183 * This function initialises the GIC distributor interface based upon the data 184 * provided by the platform while initialising the driver. 185 ******************************************************************************/ 186 void __init gicv3_distif_init(void) 187 { 188 unsigned int bitmap; 189 190 assert(gicv3_driver_data != NULL); 191 assert(gicv3_driver_data->gicd_base != 0U); 192 193 assert(IS_IN_EL3()); 194 195 /* 196 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 197 * the ARE_S bit. The Distributor might generate a system error 198 * otherwise. 199 */ 200 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 201 CTLR_ENABLE_G0_BIT | 202 CTLR_ENABLE_G1S_BIT | 203 CTLR_ENABLE_G1NS_BIT, 204 RWP_TRUE); 205 206 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 207 gicd_set_ctlr(gicv3_driver_data->gicd_base, 208 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 209 210 /* Set the default attribute of all (E)SPIs */ 211 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); 212 213 bitmap = gicv3_secure_spis_config_props( 214 gicv3_driver_data->gicd_base, 215 gicv3_driver_data->interrupt_props, 216 gicv3_driver_data->interrupt_props_num); 217 218 /* Enable the secure (E)SPIs now that they have been configured */ 219 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 220 } 221 222 /******************************************************************************* 223 * This function initialises the GIC Redistributor interface of the calling CPU 224 * (identified by the 'proc_num' parameter) based upon the data provided by the 225 * platform while initialising the driver. 226 ******************************************************************************/ 227 void gicv3_rdistif_init(unsigned int proc_num) 228 { 229 uintptr_t gicr_base; 230 unsigned int bitmap; 231 uint32_t ctlr; 232 233 assert(gicv3_driver_data != NULL); 234 assert(proc_num < gicv3_driver_data->rdistif_num); 235 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 236 assert(gicv3_driver_data->gicd_base != 0U); 237 238 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base); 239 assert((ctlr & CTLR_ARE_S_BIT) != 0U); 240 241 assert(IS_IN_EL3()); 242 243 /* Power on redistributor */ 244 gicv3_rdistif_on(proc_num); 245 246 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 247 assert(gicr_base != 0U); 248 249 /* Set the default attribute of all SGIs and (E)PPIs */ 250 gicv3_ppi_sgi_config_defaults(gicr_base); 251 252 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, 253 gicv3_driver_data->interrupt_props, 254 gicv3_driver_data->interrupt_props_num); 255 256 /* Enable interrupt groups as required, if not already */ 257 if ((ctlr & bitmap) != bitmap) { 258 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 259 } 260 } 261 262 /******************************************************************************* 263 * Functions to perform power operations on GIC Redistributor 264 ******************************************************************************/ 265 void gicv3_rdistif_off(unsigned int proc_num) 266 { 267 } 268 269 void gicv3_rdistif_on(unsigned int proc_num) 270 { 271 } 272 273 /******************************************************************************* 274 * This function enables the GIC CPU interface of the calling CPU using only 275 * system register accesses. 276 ******************************************************************************/ 277 void gicv3_cpuif_enable(unsigned int proc_num) 278 { 279 uintptr_t gicr_base; 280 u_register_t scr_el3; 281 unsigned int icc_sre_el3; 282 283 assert(gicv3_driver_data != NULL); 284 assert(proc_num < gicv3_driver_data->rdistif_num); 285 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 286 assert(IS_IN_EL3()); 287 288 /* Mark the connected core as awake */ 289 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 290 gicv3_rdistif_mark_core_awake(gicr_base); 291 292 /* Disable the legacy interrupt bypass */ 293 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 294 295 /* 296 * Enable system register access for EL3 and allow lower exception 297 * levels to configure the same for themselves. If the legacy mode is 298 * not supported, the SRE bit is RAO/WI 299 */ 300 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 301 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 302 303 scr_el3 = read_scr_el3(); 304 305 /* 306 * Switch to NS state to write Non secure ICC_SRE_EL1 and 307 * ICC_SRE_EL2 registers. 308 */ 309 write_scr_el3(scr_el3 | SCR_NS_BIT); 310 isb(); 311 312 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 313 write_icc_sre_el1(ICC_SRE_SRE_BIT); 314 isb(); 315 316 /* Switch to secure state. */ 317 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 318 isb(); 319 320 /* Write the secure ICC_SRE_EL1 register */ 321 write_icc_sre_el1(ICC_SRE_SRE_BIT); 322 isb(); 323 324 /* Program the idle priority in the PMR */ 325 write_icc_pmr_el1(GIC_PRI_MASK); 326 327 /* Enable Group0 interrupts */ 328 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 329 330 /* Enable Group1 Secure interrupts */ 331 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 332 IGRPEN1_EL3_ENABLE_G1S_BIT); 333 /* and restore the original */ 334 write_scr_el3(scr_el3); 335 isb(); 336 /* Add DSB to ensure visibility of System register writes */ 337 dsb(); 338 } 339 340 /******************************************************************************* 341 * This function disables the GIC CPU interface of the calling CPU using 342 * only system register accesses. 343 ******************************************************************************/ 344 void gicv3_cpuif_disable(unsigned int proc_num) 345 { 346 uintptr_t gicr_base; 347 348 assert(gicv3_driver_data != NULL); 349 assert(proc_num < gicv3_driver_data->rdistif_num); 350 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 351 352 assert(IS_IN_EL3()); 353 354 /* Disable legacy interrupt bypass */ 355 write_icc_sre_el3(read_icc_sre_el3() | 356 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 357 358 /* Disable Group0 interrupts */ 359 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 360 ~IGRPEN1_EL1_ENABLE_G0_BIT); 361 362 /* Disable Group1 Secure and Non-Secure interrupts */ 363 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 364 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 365 IGRPEN1_EL3_ENABLE_G1S_BIT)); 366 367 /* Synchronise accesses to group enable registers */ 368 isb(); 369 /* Add DSB to ensure visibility of System register writes */ 370 dsb(); 371 372 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 373 assert(gicr_base != 0UL); 374 375 /* 376 * dsb() already issued previously after clearing the CPU group 377 * enabled, apply below workaround to toggle the "DPG*" 378 * bits of GICR_CTLR register for unblocking event. 379 */ 380 gicv3_apply_errata_wa_2384374(gicr_base); 381 382 /* Mark the connected core as asleep */ 383 gicv3_rdistif_mark_core_asleep(gicr_base); 384 } 385 386 /******************************************************************************* 387 * This function returns the id of the highest priority pending interrupt at 388 * the GIC cpu interface. 389 ******************************************************************************/ 390 unsigned int gicv3_get_pending_interrupt_id(void) 391 { 392 unsigned int id; 393 394 assert(IS_IN_EL3()); 395 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 396 397 /* 398 * If the ID is special identifier corresponding to G1S or G1NS 399 * interrupt, then read the highest pending group 1 interrupt. 400 */ 401 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) { 402 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 403 } 404 405 return id; 406 } 407 408 /******************************************************************************* 409 * This function returns the type of the highest priority pending interrupt at 410 * the GIC cpu interface. The return values can be one of the following : 411 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 412 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 413 * 0 - 1019 : The interrupt type is secure Group 0. 414 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 415 * sufficient priority to be signaled 416 ******************************************************************************/ 417 unsigned int gicv3_get_pending_interrupt_type(void) 418 { 419 assert(IS_IN_EL3()); 420 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 421 } 422 423 /******************************************************************************* 424 * This function returns the group that has been configured under by the 425 * interrupt controller for the given interrupt id i.e. either group0 or group1 426 * Secure / Non Secure. The return value can be one of the following : 427 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 428 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 429 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 430 * interrupt. 431 ******************************************************************************/ 432 unsigned int gicv3_get_interrupt_group(unsigned int id, unsigned int proc_num) 433 { 434 unsigned int igroup, grpmodr; 435 uintptr_t gicr_base; 436 uintptr_t gicd_base; 437 438 assert(IS_IN_EL3()); 439 assert(gicv3_driver_data != NULL); 440 441 /* Ensure the parameters are valid */ 442 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID)); 443 assert(proc_num < gicv3_driver_data->rdistif_num); 444 445 /* All LPI interrupts are Group 1 non secure */ 446 if (id >= MIN_LPI_ID) { 447 return INTR_GROUP1NS; 448 } 449 450 if (!is_valid_interrupt(id)) { 451 panic(); 452 } 453 454 /* Check interrupt ID */ 455 if (IS_SGI_PPI(id)) { 456 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 457 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 458 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 459 igroup = gicr_get_igroupr(gicr_base, id); 460 grpmodr = gicr_get_igrpmodr(gicr_base, id); 461 } else { 462 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 463 assert(gicv3_driver_data->gicd_base != 0U); 464 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 465 igroup = gicd_get_igroupr(gicd_base, id); 466 grpmodr = gicd_get_igrpmodr(gicd_base, id); 467 } 468 469 /* 470 * If the IGROUP bit is set, then it is a Group 1 Non secure 471 * interrupt 472 */ 473 if (igroup != 0U) { 474 return INTR_GROUP1NS; 475 } 476 477 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 478 if (grpmodr != 0U) { 479 return INTR_GROUP1S; 480 } 481 482 /* Else it is a Group 0 Secure interrupt */ 483 return INTR_GROUP0; 484 } 485 486 /***************************************************************************** 487 * Function to save and disable the GIC ITS register context. The power 488 * management of GIC ITS is implementation-defined and this function doesn't 489 * save any memory structures required to support ITS. As the sequence to save 490 * this state is implementation defined, it should be executed in platform 491 * specific code. Calling this function alone and then powering down the GIC and 492 * ITS without implementing the aforementioned platform specific code will 493 * corrupt the ITS state. 494 * 495 * This function must be invoked after the GIC CPU interface is disabled. 496 *****************************************************************************/ 497 void gicv3_its_save_disable(uintptr_t gits_base, 498 gicv3_its_ctx_t * const its_ctx) 499 { 500 unsigned int i; 501 502 assert(gicv3_driver_data != NULL); 503 assert(IS_IN_EL3()); 504 assert(its_ctx != NULL); 505 assert(gits_base != 0U); 506 507 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 508 509 /* Disable the ITS */ 510 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 511 512 /* Wait for quiescent state */ 513 gits_wait_for_quiescent_bit(gits_base); 514 515 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 516 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 517 518 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 519 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 520 } 521 } 522 523 /***************************************************************************** 524 * Function to restore the GIC ITS register context. The power 525 * management of GIC ITS is implementation defined and this function doesn't 526 * restore any memory structures required to support ITS. The assumption is 527 * that these structures are in memory and are retained during system suspend. 528 * 529 * This must be invoked before the GIC CPU interface is enabled. 530 *****************************************************************************/ 531 void gicv3_its_restore(uintptr_t gits_base, 532 const gicv3_its_ctx_t * const its_ctx) 533 { 534 unsigned int i; 535 536 assert(gicv3_driver_data != NULL); 537 assert(IS_IN_EL3()); 538 assert(its_ctx != NULL); 539 assert(gits_base != 0U); 540 541 /* Assert that the GITS is disabled and quiescent */ 542 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 543 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U); 544 545 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 546 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 547 548 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 549 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 550 } 551 552 /* Restore the ITS CTLR but leave the ITS disabled */ 553 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 554 } 555 556 /***************************************************************************** 557 * Function to save the GIC Redistributor register context. This function 558 * must be invoked after CPU interface disable and prior to Distributor save. 559 *****************************************************************************/ 560 void gicv3_rdistif_save(unsigned int proc_num, 561 gicv3_redist_ctx_t * const rdist_ctx) 562 { 563 uintptr_t gicr_base; 564 unsigned int i, ppi_regs_num, regs_num; 565 566 assert(gicv3_driver_data != NULL); 567 assert(proc_num < gicv3_driver_data->rdistif_num); 568 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 569 assert(IS_IN_EL3()); 570 assert(rdist_ctx != NULL); 571 572 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 573 574 #if GIC_EXT_INTID 575 /* Calculate number of PPI registers */ 576 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 577 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 578 /* All other values except PPInum [0-2] are reserved */ 579 if (ppi_regs_num > 3U) { 580 ppi_regs_num = 1U; 581 } 582 #else 583 ppi_regs_num = 1U; 584 #endif 585 /* 586 * Wait for any write to GICR_CTLR to complete before trying to save any 587 * state. 588 */ 589 gicr_wait_for_pending_write(gicr_base); 590 591 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 592 593 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 594 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 595 596 /* 32 interrupt IDs per register */ 597 for (i = 0U; i < ppi_regs_num; ++i) { 598 SAVE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 599 SAVE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 600 SAVE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 601 SAVE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 602 SAVE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 603 } 604 605 /* 16 interrupt IDs per GICR_ICFGR register */ 606 regs_num = ppi_regs_num << 1; 607 for (i = 0U; i < regs_num; ++i) { 608 SAVE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 609 } 610 611 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 612 613 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 614 regs_num = ppi_regs_num << 3; 615 for (i = 0U; i < regs_num; ++i) { 616 rdist_ctx->gicr_ipriorityr[i] = 617 gicr_ipriorityr_read(gicr_base, i); 618 } 619 620 /* 621 * Call the pre-save hook that implements the IMP DEF sequence that may 622 * be required on some GIC implementations. As this may need to access 623 * the Redistributor registers, we pass it proc_num. 624 */ 625 gicv3_distif_pre_save(proc_num); 626 } 627 628 /***************************************************************************** 629 * Function to restore the GIC Redistributor register context. We disable 630 * LPI and per-cpu interrupts before we start restore of the Redistributor. 631 * This function must be invoked after Distributor restore but prior to 632 * CPU interface enable. The pending and active interrupts are restored 633 * after the interrupts are fully configured and enabled. 634 *****************************************************************************/ 635 void gicv3_rdistif_init_restore(unsigned int proc_num, 636 const gicv3_redist_ctx_t * const rdist_ctx) 637 { 638 uintptr_t gicr_base; 639 unsigned int i, ppi_regs_num, regs_num; 640 641 assert(gicv3_driver_data != NULL); 642 assert(proc_num < gicv3_driver_data->rdistif_num); 643 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 644 assert(IS_IN_EL3()); 645 assert(rdist_ctx != NULL); 646 647 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 648 649 #if GIC_EXT_INTID 650 /* Calculate number of PPI registers */ 651 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 652 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 653 /* All other values except PPInum [0-2] are reserved */ 654 if (ppi_regs_num > 3U) { 655 ppi_regs_num = 1U; 656 } 657 #else 658 ppi_regs_num = 1U; 659 #endif 660 /* Power on redistributor */ 661 gicv3_rdistif_on(proc_num); 662 663 /* 664 * Call the post-restore hook that implements the IMP DEF sequence that 665 * may be required on some GIC implementations. As this may need to 666 * access the Redistributor registers, we pass it proc_num. 667 */ 668 gicv3_distif_post_restore(proc_num); 669 670 /* 671 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 672 * This is a more scalable approach as it avoids clearing the enable 673 * bits in the GICD_CTLR. 674 */ 675 for (i = 0U; i < ppi_regs_num; ++i) { 676 gicr_write_icenabler(gicr_base, i, ~0U); 677 } 678 679 /* Wait for pending writes to GICR_ICENABLER */ 680 gicr_wait_for_pending_write(gicr_base); 681 682 /* 683 * Disable the LPIs to avoid unpredictable behavior when writing to 684 * GICR_PROPBASER and GICR_PENDBASER. 685 */ 686 gicr_write_ctlr(gicr_base, 687 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 688 689 /* Restore registers' content */ 690 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 691 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 692 693 /* 32 interrupt IDs per register */ 694 for (i = 0U; i < ppi_regs_num; ++i) { 695 RESTORE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 696 RESTORE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 697 } 698 699 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 700 regs_num = ppi_regs_num << 3; 701 for (i = 0U; i < regs_num; ++i) { 702 gicr_ipriorityr_write(gicr_base, i, 703 rdist_ctx->gicr_ipriorityr[i]); 704 } 705 706 /* 16 interrupt IDs per GICR_ICFGR register */ 707 regs_num = ppi_regs_num << 1; 708 for (i = 0U; i < regs_num; ++i) { 709 RESTORE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 710 } 711 712 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 713 714 /* Restore after group and priorities are set. 715 * 32 interrupt IDs per register 716 */ 717 for (i = 0U; i < ppi_regs_num; ++i) { 718 RESTORE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 719 RESTORE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 720 } 721 722 /* 723 * Wait for all writes to the Distributor to complete before enabling 724 * the SGI and (E)PPIs. 725 */ 726 gicr_wait_for_upstream_pending_write(gicr_base); 727 728 /* 32 interrupt IDs per GICR_ISENABLER register */ 729 for (i = 0U; i < ppi_regs_num; ++i) { 730 RESTORE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 731 } 732 733 /* 734 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 735 * the first write to GICR_CTLR was still in flight (this write only 736 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 737 * bit). 738 */ 739 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 740 gicr_wait_for_pending_write(gicr_base); 741 } 742 743 /***************************************************************************** 744 * Function to save the GIC Distributor register context. This function 745 * must be invoked after CPU interface disable and Redistributor save. 746 *****************************************************************************/ 747 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 748 { 749 assert(gicv3_driver_data != NULL); 750 assert(gicv3_driver_data->gicd_base != 0U); 751 assert(IS_IN_EL3()); 752 assert(dist_ctx != NULL); 753 754 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 755 unsigned int num_ints = gicv3_get_spi_limit(gicd_base); 756 #if GIC_EXT_INTID 757 unsigned int num_eints = gicv3_get_espi_limit(gicd_base); 758 #endif 759 760 /* Wait for pending write to complete */ 761 gicd_wait_for_pending_write(gicd_base); 762 763 /* Save the GICD_CTLR */ 764 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 765 766 /* Save GICD_IGROUPR for INTIDs 32 - 1019 */ 767 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 768 769 /* Save GICD_IGROUPRE for INTIDs 4096 - 5119 */ 770 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 771 772 /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */ 773 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 774 775 /* Save GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 776 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 777 778 /* Save GICD_ISPENDR for INTIDs 32 - 1019 */ 779 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 780 781 /* Save GICD_ISPENDRE for INTIDs 4096 - 5119 */ 782 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 783 784 /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */ 785 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 786 787 /* Save GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 788 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 789 790 /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */ 791 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 792 793 /* Save GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 794 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 795 796 /* Save GICD_ICFGR for INTIDs 32 - 1019 */ 797 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 798 799 /* Save GICD_ICFGRE for INTIDs 4096 - 5119 */ 800 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 801 802 /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */ 803 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 804 805 /* Save GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 806 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 807 808 /* Save GICD_NSACR for INTIDs 32 - 1019 */ 809 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 810 811 /* Save GICD_NSACRE for INTIDs 4096 - 5119 */ 812 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 813 814 /* Save GICD_IROUTER for INTIDs 32 - 1019 */ 815 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 816 817 /* Save GICD_IROUTERE for INTIDs 4096 - 5119 */ 818 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 819 820 /* 821 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 822 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 823 * driver. 824 */ 825 } 826 827 /***************************************************************************** 828 * Function to restore the GIC Distributor register context. We disable G0, G1S 829 * and G1NS interrupt groups before we start restore of the Distributor. This 830 * function must be invoked prior to Redistributor restore and CPU interface 831 * enable. The pending and active interrupts are restored after the interrupts 832 * are fully configured and enabled. 833 *****************************************************************************/ 834 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 835 { 836 assert(gicv3_driver_data != NULL); 837 assert(gicv3_driver_data->gicd_base != 0U); 838 assert(IS_IN_EL3()); 839 assert(dist_ctx != NULL); 840 841 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 842 843 /* 844 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 845 * the ARE_S bit. The Distributor might generate a system error 846 * otherwise. 847 */ 848 gicd_clr_ctlr(gicd_base, 849 CTLR_ENABLE_G0_BIT | 850 CTLR_ENABLE_G1S_BIT | 851 CTLR_ENABLE_G1NS_BIT, 852 RWP_TRUE); 853 854 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 855 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 856 857 unsigned int num_ints = gicv3_get_spi_limit(gicd_base); 858 #if GIC_EXT_INTID 859 unsigned int num_eints = gicv3_get_espi_limit(gicd_base); 860 #endif 861 /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */ 862 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 863 864 /* Restore GICD_IGROUPRE for INTIDs 4096 - 5119 */ 865 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 866 867 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */ 868 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 869 870 /* Restore GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 871 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 872 873 /* Restore GICD_ICFGR for INTIDs 32 - 1019 */ 874 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 875 876 /* Restore GICD_ICFGRE for INTIDs 4096 - 5119 */ 877 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 878 879 /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */ 880 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 881 882 /* Restore GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 883 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 884 885 /* Restore GICD_NSACR for INTIDs 32 - 1019 */ 886 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 887 888 /* Restore GICD_NSACRE for INTIDs 4096 - 5119 */ 889 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 890 891 /* Restore GICD_IROUTER for INTIDs 32 - 1019 */ 892 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 893 894 /* Restore GICD_IROUTERE for INTIDs 4096 - 5119 */ 895 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 896 897 /* 898 * Restore ISENABLER(E), ISPENDR(E) and ISACTIVER(E) after 899 * the interrupts are configured. 900 */ 901 902 /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */ 903 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 904 905 /* Restore GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 906 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 907 908 /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */ 909 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 910 911 /* Restore GICD_ISPENDRE for INTIDs 4096 - 5119 */ 912 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 913 914 /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */ 915 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 916 917 /* Restore GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 918 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 919 920 /* Restore the GICD_CTLR */ 921 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 922 gicd_wait_for_pending_write(gicd_base); 923 } 924 925 /******************************************************************************* 926 * This function gets the priority of the interrupt the processor is currently 927 * servicing. 928 ******************************************************************************/ 929 unsigned int gicv3_get_running_priority(void) 930 { 931 return (unsigned int)read_icc_rpr_el1(); 932 } 933 934 /******************************************************************************* 935 * This function checks if the interrupt identified by id is active (whether the 936 * state is either active, or active and pending). The proc_num is used if the 937 * interrupt is SGI or (E)PPI and programs the corresponding Redistributor 938 * interface. 939 ******************************************************************************/ 940 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) 941 { 942 uintptr_t gicd_base; 943 944 assert(gicv3_driver_data != NULL); 945 assert(gicv3_driver_data->gicd_base != 0U); 946 assert(proc_num < gicv3_driver_data->rdistif_num); 947 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 948 949 if (!is_valid_interrupt(id)) { 950 panic(); 951 } 952 /* Check interrupt ID */ 953 if (IS_SGI_PPI(id)) { 954 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 955 return gicr_get_isactiver( 956 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 957 } 958 959 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 960 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 961 return gicd_get_isactiver(gicd_base, id); 962 } 963 964 /******************************************************************************* 965 * This function enables the interrupt identified by id. The proc_num 966 * is used if the interrupt is SGI or PPI, and programs the corresponding 967 * Redistributor interface. 968 ******************************************************************************/ 969 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) 970 { 971 uintptr_t gicd_base; 972 973 assert(gicv3_driver_data != NULL); 974 assert(gicv3_driver_data->gicd_base != 0U); 975 assert(proc_num < gicv3_driver_data->rdistif_num); 976 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 977 978 /* 979 * Ensure that any shared variable updates depending on out of band 980 * interrupt trigger are observed before enabling interrupt. 981 */ 982 dsbishst(); 983 if (!is_valid_interrupt(id)) { 984 panic(); 985 } 986 /* Check interrupt ID */ 987 if (IS_SGI_PPI(id)) { 988 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 989 gicr_set_isenabler( 990 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 991 } else { 992 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 993 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 994 gicd_set_isenabler(gicd_base, id); 995 } 996 } 997 998 /******************************************************************************* 999 * This function disables the interrupt identified by id. The proc_num 1000 * is used if the interrupt is SGI or PPI, and programs the corresponding 1001 * Redistributor interface. 1002 ******************************************************************************/ 1003 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) 1004 { 1005 uintptr_t gicd_base; 1006 1007 assert(gicv3_driver_data != NULL); 1008 assert(gicv3_driver_data->gicd_base != 0U); 1009 assert(proc_num < gicv3_driver_data->rdistif_num); 1010 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1011 1012 /* 1013 * Disable interrupt, and ensure that any shared variable updates 1014 * depending on out of band interrupt trigger are observed afterwards. 1015 */ 1016 if (!is_valid_interrupt(id)) { 1017 panic(); 1018 } 1019 /* Check interrupt ID */ 1020 if (IS_SGI_PPI(id)) { 1021 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1022 gicr_set_icenabler( 1023 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1024 1025 /* Write to clear enable requires waiting for pending writes */ 1026 gicr_wait_for_pending_write( 1027 gicv3_driver_data->rdistif_base_addrs[proc_num]); 1028 } else { 1029 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1030 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1031 gicd_set_icenabler(gicd_base, id); 1032 1033 /* Write to clear enable requires waiting for pending writes */ 1034 gicd_wait_for_pending_write(gicd_base); 1035 } 1036 1037 dsbishst(); 1038 } 1039 1040 /******************************************************************************* 1041 * This function sets the interrupt priority as supplied for the given interrupt 1042 * id. 1043 ******************************************************************************/ 1044 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 1045 unsigned int priority) 1046 { 1047 uintptr_t gicr_base; 1048 uintptr_t gicd_base; 1049 1050 assert(gicv3_driver_data != NULL); 1051 assert(gicv3_driver_data->gicd_base != 0U); 1052 assert(proc_num < gicv3_driver_data->rdistif_num); 1053 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1054 1055 if (!is_valid_interrupt(id)) { 1056 panic(); 1057 } 1058 /* Check interrupt ID */ 1059 if (IS_SGI_PPI(id)) { 1060 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1061 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1062 gicr_set_ipriorityr(gicr_base, id, priority); 1063 } else { 1064 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1065 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1066 gicd_set_ipriorityr(gicd_base, id, priority); 1067 } 1068 } 1069 1070 /******************************************************************************* 1071 * This function assigns group for the interrupt identified by id. The proc_num 1072 * is used if the interrupt is SGI or (E)PPI, and programs the corresponding 1073 * Redistributor interface. The group can be any of GICV3_INTR_GROUP* 1074 ******************************************************************************/ 1075 void gicv3_set_interrupt_group(unsigned int id, unsigned int proc_num, 1076 unsigned int group) 1077 { 1078 bool igroup = false, grpmod = false; 1079 uintptr_t gicr_base; 1080 uintptr_t gicd_base; 1081 1082 assert(gicv3_driver_data != NULL); 1083 assert(gicv3_driver_data->gicd_base != 0U); 1084 assert(proc_num < gicv3_driver_data->rdistif_num); 1085 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1086 1087 switch (group) { 1088 case INTR_GROUP1S: 1089 igroup = false; 1090 grpmod = true; 1091 break; 1092 case INTR_GROUP0: 1093 igroup = false; 1094 grpmod = false; 1095 break; 1096 case INTR_GROUP1NS: 1097 igroup = true; 1098 grpmod = false; 1099 break; 1100 default: 1101 assert(false); 1102 break; 1103 } 1104 1105 if (!is_valid_interrupt(id)) { 1106 panic(); 1107 } 1108 /* Check interrupt ID */ 1109 if (IS_SGI_PPI(id)) { 1110 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1111 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1112 1113 igroup ? gicr_set_igroupr(gicr_base, id) : 1114 gicr_clr_igroupr(gicr_base, id); 1115 grpmod ? gicr_set_igrpmodr(gicr_base, id) : 1116 gicr_clr_igrpmodr(gicr_base, id); 1117 } else { 1118 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1119 1120 /* Serialize read-modify-write to Distributor registers */ 1121 spin_lock(&gic_lock); 1122 1123 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1124 1125 igroup ? gicd_set_igroupr(gicd_base, id) : 1126 gicd_clr_igroupr(gicd_base, id); 1127 grpmod ? gicd_set_igrpmodr(gicd_base, id) : 1128 gicd_clr_igrpmodr(gicd_base, id); 1129 1130 spin_unlock(&gic_lock); 1131 } 1132 } 1133 1134 /******************************************************************************* 1135 * This function raises the specified SGI of the specified group. 1136 * 1137 * The target parameter must be a valid MPIDR in the system. 1138 ******************************************************************************/ 1139 void gicv3_raise_sgi(unsigned int sgi_num, gicv3_irq_group_t group, 1140 u_register_t target) 1141 { 1142 unsigned int tgt, aff3, aff2, aff1, aff0; 1143 uint64_t sgi_val; 1144 1145 /* Verify interrupt number is in the SGI range */ 1146 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID)); 1147 1148 /* Extract affinity fields from target */ 1149 aff0 = MPIDR_AFFLVL0_VAL(target); 1150 aff1 = MPIDR_AFFLVL1_VAL(target); 1151 aff2 = MPIDR_AFFLVL2_VAL(target); 1152 aff3 = MPIDR_AFFLVL3_VAL(target); 1153 1154 /* 1155 * Make target list from affinity 0, and ensure GICv3 SGI can target 1156 * this PE. 1157 */ 1158 assert(aff0 < GICV3_MAX_SGI_TARGETS); 1159 tgt = BIT_32(aff0); 1160 1161 /* Raise SGI to PE specified by its affinity */ 1162 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF, 1163 tgt); 1164 1165 /* 1166 * Ensure that any shared variable updates depending on out of band 1167 * interrupt trigger are observed before raising SGI. 1168 */ 1169 dsbishst(); 1170 1171 switch (group) { 1172 case GICV3_G0: 1173 write_icc_sgi0r_el1(sgi_val); 1174 break; 1175 case GICV3_G1NS: 1176 write_icc_asgi1r(sgi_val); 1177 break; 1178 case GICV3_G1S: 1179 write_icc_sgi1r(sgi_val); 1180 break; 1181 default: 1182 assert(false); 1183 break; 1184 } 1185 1186 isb(); 1187 } 1188 1189 /******************************************************************************* 1190 * This function sets the interrupt routing for the given (E)SPI interrupt id. 1191 * The interrupt routing is specified in routing mode and mpidr. 1192 * 1193 * The routing mode can be either of: 1194 * - GICV3_IRM_ANY 1195 * - GICV3_IRM_PE 1196 * 1197 * The mpidr is the affinity of the PE to which the interrupt will be routed, 1198 * and is ignored for routing mode GICV3_IRM_ANY. 1199 ******************************************************************************/ 1200 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr) 1201 { 1202 unsigned long long aff; 1203 uint64_t router; 1204 uintptr_t gicd_base; 1205 1206 assert(gicv3_driver_data != NULL); 1207 assert(gicv3_driver_data->gicd_base != 0U); 1208 1209 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE)); 1210 1211 assert(IS_SPI(id)); 1212 1213 aff = gicd_irouter_val_from_mpidr(mpidr, irm); 1214 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1215 gicd_write_irouter(gicd_base, id, aff); 1216 1217 /* 1218 * In implementations that do not require 1 of N distribution of SPIs, 1219 * IRM might be RAZ/WI. Read back and verify IRM bit. 1220 */ 1221 if (irm == GICV3_IRM_ANY) { 1222 router = gicd_read_irouter(gicd_base, id); 1223 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) { 1224 ERROR("GICv3 implementation doesn't support routing ANY\n"); 1225 panic(); 1226 } 1227 } 1228 } 1229 1230 /******************************************************************************* 1231 * This function clears the pending status of an interrupt identified by id. 1232 * The proc_num is used if the interrupt is SGI or (E)PPI, and programs the 1233 * corresponding Redistributor interface. 1234 ******************************************************************************/ 1235 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num) 1236 { 1237 uintptr_t gicd_base; 1238 1239 assert(gicv3_driver_data != NULL); 1240 assert(gicv3_driver_data->gicd_base != 0U); 1241 assert(proc_num < gicv3_driver_data->rdistif_num); 1242 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1243 1244 /* 1245 * Clear pending interrupt, and ensure that any shared variable updates 1246 * depending on out of band interrupt trigger are observed afterwards. 1247 */ 1248 if (!is_valid_interrupt(id)) { 1249 panic(); 1250 } 1251 /* Check interrupt ID */ 1252 if (IS_SGI_PPI(id)) { 1253 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1254 gicr_set_icpendr( 1255 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1256 } else { 1257 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1258 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1259 gicd_set_icpendr(gicd_base, id); 1260 } 1261 1262 dsbishst(); 1263 } 1264 1265 /******************************************************************************* 1266 * This function sets the pending status of an interrupt identified by id. 1267 * The proc_num is used if the interrupt is SGI or PPI and programs the 1268 * corresponding Redistributor interface. 1269 ******************************************************************************/ 1270 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num) 1271 { 1272 uintptr_t gicd_base; 1273 1274 assert(gicv3_driver_data != NULL); 1275 assert(gicv3_driver_data->gicd_base != 0U); 1276 assert(proc_num < gicv3_driver_data->rdistif_num); 1277 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1278 1279 /* 1280 * Ensure that any shared variable updates depending on out of band 1281 * interrupt trigger are observed before setting interrupt pending. 1282 */ 1283 dsbishst(); 1284 1285 if (!is_valid_interrupt(id)) { 1286 panic(); 1287 } 1288 1289 /* Check interrupt ID */ 1290 if (IS_SGI_PPI(id)) { 1291 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1292 gicr_set_ispendr( 1293 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1294 } else { 1295 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1296 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1297 gicd_set_ispendr(gicd_base, id); 1298 } 1299 } 1300 1301 /******************************************************************************* 1302 * This function sets the PMR register with the supplied value. Returns the 1303 * original PMR. 1304 ******************************************************************************/ 1305 unsigned int gicv3_set_pmr(unsigned int mask) 1306 { 1307 unsigned int old_mask; 1308 1309 old_mask = (unsigned int)read_icc_pmr_el1(); 1310 1311 /* 1312 * Order memory updates w.r.t. PMR write, and ensure they're visible 1313 * before potential out of band interrupt trigger because of PMR update. 1314 * PMR system register writes are self-synchronizing, so no ISB required 1315 * thereafter. 1316 */ 1317 dsbishst(); 1318 write_icc_pmr_el1(mask); 1319 1320 return old_mask; 1321 } 1322 1323 /******************************************************************************* 1324 * This function restores the PMR register to old value and also triggers 1325 * gicv3_apply_errata_wa_2384374() that flushes the GIC buffer allowing any 1326 * pending interrupts to processed. Returns the original PMR. 1327 ******************************************************************************/ 1328 unsigned int gicv3_deactivate_priority(unsigned int mask) 1329 { 1330 1331 unsigned int old_mask, proc_num; 1332 uintptr_t gicr_base; 1333 1334 old_mask = gicv3_set_pmr(mask); 1335 1336 proc_num = plat_my_core_pos(); 1337 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1338 assert(gicr_base != 0UL); 1339 1340 /* Add DSB to ensure visibility of System register writes */ 1341 dsb(); 1342 1343 gicv3_apply_errata_wa_2384374(gicr_base); 1344 1345 return old_mask; 1346 } 1347 1348 /******************************************************************************* 1349 * This function delegates the responsibility of discovering the corresponding 1350 * Redistributor frames to each CPU itself. It is a modified version of 1351 * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform 1352 * unlike the previous way in which only the Primary CPU did the discovery of 1353 * all the Redistributor frames for every CPU. It also handles the scenario in 1354 * which the frames of various CPUs are not contiguous in physical memory. 1355 ******************************************************************************/ 1356 int gicv3_rdistif_probe(const uintptr_t gicr_frame) 1357 { 1358 u_register_t mpidr, mpidr_self; 1359 unsigned int proc_num; 1360 uint64_t typer_val; 1361 uintptr_t rdistif_base; 1362 bool gicr_frame_found = false; 1363 1364 assert(gicv3_driver_data->gicr_base == 0U); 1365 1366 if (plat_can_cmo()) { 1367 /* Ensure this function is called with Data Cache enabled */ 1368 #ifndef __aarch64__ 1369 assert((read_sctlr() & SCTLR_C_BIT) != 0U); 1370 #else 1371 assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U); 1372 #endif /* !__aarch64__ */ 1373 } 1374 1375 mpidr_self = read_mpidr_el1() & MPIDR_AFFINITY_MASK; 1376 rdistif_base = gicr_frame; 1377 do { 1378 typer_val = gicr_read_typer(rdistif_base); 1379 mpidr = mpidr_from_gicr_typer(typer_val); 1380 if (gicv3_driver_data->mpidr_to_core_pos != NULL) { 1381 proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr); 1382 } else { 1383 proc_num = (unsigned int)(typer_val >> 1384 TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK; 1385 } 1386 if (mpidr == mpidr_self) { 1387 /* The base address doesn't need to be initialized on 1388 * every warm boot. 1389 */ 1390 if (gicv3_driver_data->rdistif_base_addrs[proc_num] 1391 != 0U) { 1392 return 0; 1393 } 1394 gicv3_driver_data->rdistif_base_addrs[proc_num] = 1395 rdistif_base; 1396 gicr_frame_found = true; 1397 break; 1398 } 1399 rdistif_base += gicv3_redist_size(typer_val); 1400 } while ((typer_val & TYPER_LAST_BIT) == 0U); 1401 1402 if (!gicr_frame_found) { 1403 return -1; 1404 } 1405 1406 /* 1407 * Flush the driver data to ensure coherency. This is 1408 * not required if platform has HW_ASSISTED_COHERENCY 1409 * enabled. 1410 */ 1411 #if !HW_ASSISTED_COHERENCY 1412 /* 1413 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 1414 */ 1415 flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]), 1416 sizeof(*(gicv3_driver_data->rdistif_base_addrs))); 1417 #endif 1418 return 0; /* Found matching GICR frame */ 1419 } 1420 1421 /****************************************************************************** 1422 * This function checks the interrupt ID and returns true for SGIs, (E)PPIs 1423 * and (E)SPIs IDs. Any interrupt ID outside the range is invalid and returns 1424 * false. 1425 *****************************************************************************/ 1426 static bool is_valid_interrupt(unsigned int id) 1427 { 1428 /* Valid interrupts: 1429 * SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 1430 * SPIs: 32-1019, ESPIs: 4096-5119 1431 */ 1432 if ((IS_SGI_PPI(id)) || (IS_SPI(id))) { 1433 return true; 1434 } 1435 1436 return false; 1437 } 1438