1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <debug.h> 35 #include <gic_common.h> 36 #include <gicv3.h> 37 #include "../common/gic_common_private.h" 38 #include "gicv3_private.h" 39 40 static const gicv3_driver_data_t *driver_data; 41 static unsigned int gicv2_compat; 42 43 /* 44 * Redistributor power operations are weakly bound so that they can be 45 * overridden 46 */ 47 #pragma weak gicv3_rdistif_off 48 #pragma weak gicv3_rdistif_on 49 50 /******************************************************************************* 51 * This function initialises the ARM GICv3 driver in EL3 with provided platform 52 * inputs. 53 ******************************************************************************/ 54 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 55 { 56 unsigned int gic_version; 57 58 assert(plat_driver_data); 59 assert(plat_driver_data->gicd_base); 60 assert(plat_driver_data->gicr_base); 61 assert(plat_driver_data->rdistif_num); 62 assert(plat_driver_data->rdistif_base_addrs); 63 64 assert(IS_IN_EL3()); 65 66 /* 67 * The platform should provide a list of at least one type of 68 * interrupts 69 */ 70 assert(plat_driver_data->g0_interrupt_array || 71 plat_driver_data->g1s_interrupt_array); 72 73 /* 74 * If there are no interrupts of a particular type, then the number of 75 * interrupts of that type should be 0 and vice-versa. 76 */ 77 assert(plat_driver_data->g0_interrupt_array ? 78 plat_driver_data->g0_interrupt_num : 79 plat_driver_data->g0_interrupt_num == 0); 80 assert(plat_driver_data->g1s_interrupt_array ? 81 plat_driver_data->g1s_interrupt_num : 82 plat_driver_data->g1s_interrupt_num == 0); 83 84 /* Check for system register support */ 85 #ifdef AARCH32 86 assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)); 87 #else 88 assert(read_id_aa64pfr0_el1() & 89 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)); 90 #endif /* AARCH32 */ 91 92 /* The GIC version should be 3.0 */ 93 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 94 gic_version >>= PIDR2_ARCH_REV_SHIFT; 95 gic_version &= PIDR2_ARCH_REV_MASK; 96 assert(gic_version == ARCH_REV_GICV3); 97 98 /* 99 * Find out whether the GIC supports the GICv2 compatibility mode. The 100 * ARE_S bit resets to 0 if supported 101 */ 102 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 103 gicv2_compat >>= CTLR_ARE_S_SHIFT; 104 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); 105 106 /* 107 * Find the base address of each implemented Redistributor interface. 108 * The number of interfaces should be equal to the number of CPUs in the 109 * system. The memory for saving these addresses has to be allocated by 110 * the platform port 111 */ 112 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 113 plat_driver_data->rdistif_num, 114 plat_driver_data->gicr_base, 115 plat_driver_data->mpidr_to_core_pos); 116 117 driver_data = plat_driver_data; 118 119 /* 120 * The GIC driver data is initialized by the primary CPU with caches 121 * enabled. When the secondary CPU boots up, it initializes the 122 * GICC/GICR interface with the caches disabled. Hence flush the 123 * driver_data to ensure coherency. This is not required if the 124 * platform has HW_ASSISTED_COHERENCY enabled. 125 */ 126 #if !HW_ASSISTED_COHERENCY 127 flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); 128 flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); 129 #endif 130 131 INFO("GICv3 %s legacy support detected." 132 " ARM GICV3 driver initialized in EL3\n", 133 gicv2_compat ? "with" : "without"); 134 } 135 136 /******************************************************************************* 137 * This function initialises the GIC distributor interface based upon the data 138 * provided by the platform while initialising the driver. 139 ******************************************************************************/ 140 void gicv3_distif_init(void) 141 { 142 unsigned int bitmap = 0; 143 144 assert(driver_data); 145 assert(driver_data->gicd_base); 146 assert(driver_data->g1s_interrupt_array || 147 driver_data->g0_interrupt_array); 148 149 assert(IS_IN_EL3()); 150 151 /* 152 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 153 * the ARE_S bit. The Distributor might generate a system error 154 * otherwise. 155 */ 156 gicd_clr_ctlr(driver_data->gicd_base, 157 CTLR_ENABLE_G0_BIT | 158 CTLR_ENABLE_G1S_BIT | 159 CTLR_ENABLE_G1NS_BIT, 160 RWP_TRUE); 161 162 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 163 gicd_set_ctlr(driver_data->gicd_base, 164 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 165 166 /* Set the default attribute of all SPIs */ 167 gicv3_spis_configure_defaults(driver_data->gicd_base); 168 169 /* Configure the G1S SPIs */ 170 if (driver_data->g1s_interrupt_array) { 171 gicv3_secure_spis_configure(driver_data->gicd_base, 172 driver_data->g1s_interrupt_num, 173 driver_data->g1s_interrupt_array, 174 INTR_GROUP1S); 175 bitmap |= CTLR_ENABLE_G1S_BIT; 176 } 177 178 /* Configure the G0 SPIs */ 179 if (driver_data->g0_interrupt_array) { 180 gicv3_secure_spis_configure(driver_data->gicd_base, 181 driver_data->g0_interrupt_num, 182 driver_data->g0_interrupt_array, 183 INTR_GROUP0); 184 bitmap |= CTLR_ENABLE_G0_BIT; 185 } 186 187 /* Enable the secure SPIs now that they have been configured */ 188 gicd_set_ctlr(driver_data->gicd_base, bitmap, RWP_TRUE); 189 } 190 191 /******************************************************************************* 192 * This function initialises the GIC Redistributor interface of the calling CPU 193 * (identified by the 'proc_num' parameter) based upon the data provided by the 194 * platform while initialising the driver. 195 ******************************************************************************/ 196 void gicv3_rdistif_init(unsigned int proc_num) 197 { 198 uintptr_t gicr_base; 199 200 assert(driver_data); 201 assert(proc_num < driver_data->rdistif_num); 202 assert(driver_data->rdistif_base_addrs); 203 assert(driver_data->gicd_base); 204 assert(gicd_read_ctlr(driver_data->gicd_base) & CTLR_ARE_S_BIT); 205 assert(driver_data->g1s_interrupt_array || 206 driver_data->g0_interrupt_array); 207 208 assert(IS_IN_EL3()); 209 210 /* Power on redistributor */ 211 gicv3_rdistif_on(proc_num); 212 213 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 214 215 /* Set the default attribute of all SGIs and PPIs */ 216 gicv3_ppi_sgi_configure_defaults(gicr_base); 217 218 /* Configure the G1S SGIs/PPIs */ 219 if (driver_data->g1s_interrupt_array) { 220 gicv3_secure_ppi_sgi_configure(gicr_base, 221 driver_data->g1s_interrupt_num, 222 driver_data->g1s_interrupt_array, 223 INTR_GROUP1S); 224 } 225 226 /* Configure the G0 SGIs/PPIs */ 227 if (driver_data->g0_interrupt_array) { 228 gicv3_secure_ppi_sgi_configure(gicr_base, 229 driver_data->g0_interrupt_num, 230 driver_data->g0_interrupt_array, 231 INTR_GROUP0); 232 } 233 } 234 235 /******************************************************************************* 236 * Functions to perform power operations on GIC Redistributor 237 ******************************************************************************/ 238 void gicv3_rdistif_off(unsigned int proc_num) 239 { 240 return; 241 } 242 243 void gicv3_rdistif_on(unsigned int proc_num) 244 { 245 return; 246 } 247 248 /******************************************************************************* 249 * This function enables the GIC CPU interface of the calling CPU using only 250 * system register accesses. 251 ******************************************************************************/ 252 void gicv3_cpuif_enable(unsigned int proc_num) 253 { 254 uintptr_t gicr_base; 255 unsigned int scr_el3; 256 unsigned int icc_sre_el3; 257 258 assert(driver_data); 259 assert(proc_num < driver_data->rdistif_num); 260 assert(driver_data->rdistif_base_addrs); 261 assert(IS_IN_EL3()); 262 263 /* Mark the connected core as awake */ 264 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 265 gicv3_rdistif_mark_core_awake(gicr_base); 266 267 /* Disable the legacy interrupt bypass */ 268 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 269 270 /* 271 * Enable system register access for EL3 and allow lower exception 272 * levels to configure the same for themselves. If the legacy mode is 273 * not supported, the SRE bit is RAO/WI 274 */ 275 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 276 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 277 278 scr_el3 = read_scr_el3(); 279 280 /* 281 * Switch to NS state to write Non secure ICC_SRE_EL1 and 282 * ICC_SRE_EL2 registers. 283 */ 284 write_scr_el3(scr_el3 | SCR_NS_BIT); 285 isb(); 286 287 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 288 write_icc_sre_el1(ICC_SRE_SRE_BIT); 289 isb(); 290 291 /* Switch to secure state. */ 292 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 293 isb(); 294 295 /* Program the idle priority in the PMR */ 296 write_icc_pmr_el1(GIC_PRI_MASK); 297 298 /* Enable Group0 interrupts */ 299 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 300 301 /* Enable Group1 Secure interrupts */ 302 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 303 IGRPEN1_EL3_ENABLE_G1S_BIT); 304 305 /* Write the secure ICC_SRE_EL1 register */ 306 write_icc_sre_el1(ICC_SRE_SRE_BIT); 307 isb(); 308 } 309 310 /******************************************************************************* 311 * This function disables the GIC CPU interface of the calling CPU using 312 * only system register accesses. 313 ******************************************************************************/ 314 void gicv3_cpuif_disable(unsigned int proc_num) 315 { 316 uintptr_t gicr_base; 317 318 assert(driver_data); 319 assert(proc_num < driver_data->rdistif_num); 320 assert(driver_data->rdistif_base_addrs); 321 322 assert(IS_IN_EL3()); 323 324 /* Disable legacy interrupt bypass */ 325 write_icc_sre_el3(read_icc_sre_el3() | 326 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 327 328 /* Disable Group0 interrupts */ 329 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 330 ~IGRPEN1_EL1_ENABLE_G0_BIT); 331 332 /* Disable Group1 Secure and Non-Secure interrupts */ 333 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 334 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 335 IGRPEN1_EL3_ENABLE_G1S_BIT)); 336 337 /* Synchronise accesses to group enable registers */ 338 isb(); 339 340 /* Mark the connected core as asleep */ 341 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 342 gicv3_rdistif_mark_core_asleep(gicr_base); 343 } 344 345 /******************************************************************************* 346 * This function returns the id of the highest priority pending interrupt at 347 * the GIC cpu interface. 348 ******************************************************************************/ 349 unsigned int gicv3_get_pending_interrupt_id(void) 350 { 351 unsigned int id; 352 353 assert(IS_IN_EL3()); 354 id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 355 356 /* 357 * If the ID is special identifier corresponding to G1S or G1NS 358 * interrupt, then read the highest pending group 1 interrupt. 359 */ 360 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) 361 return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 362 363 return id; 364 } 365 366 /******************************************************************************* 367 * This function returns the type of the highest priority pending interrupt at 368 * the GIC cpu interface. The return values can be one of the following : 369 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 370 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 371 * 0 - 1019 : The interrupt type is secure Group 0. 372 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 373 * sufficient priority to be signaled 374 ******************************************************************************/ 375 unsigned int gicv3_get_pending_interrupt_type(void) 376 { 377 assert(IS_IN_EL3()); 378 return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 379 } 380 381 /******************************************************************************* 382 * This function returns the type of the interrupt id depending upon the group 383 * this interrupt has been configured under by the interrupt controller i.e. 384 * group0 or group1 Secure / Non Secure. The return value can be one of the 385 * following : 386 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 387 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 388 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 389 * interrupt. 390 ******************************************************************************/ 391 unsigned int gicv3_get_interrupt_type(unsigned int id, 392 unsigned int proc_num) 393 { 394 unsigned int igroup, grpmodr; 395 uintptr_t gicr_base; 396 397 assert(IS_IN_EL3()); 398 assert(driver_data); 399 400 /* Ensure the parameters are valid */ 401 assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID); 402 assert(proc_num < driver_data->rdistif_num); 403 404 /* All LPI interrupts are Group 1 non secure */ 405 if (id >= MIN_LPI_ID) 406 return INTR_GROUP1NS; 407 408 if (id < MIN_SPI_ID) { 409 assert(driver_data->rdistif_base_addrs); 410 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 411 igroup = gicr_get_igroupr0(gicr_base, id); 412 grpmodr = gicr_get_igrpmodr0(gicr_base, id); 413 } else { 414 assert(driver_data->gicd_base); 415 igroup = gicd_get_igroupr(driver_data->gicd_base, id); 416 grpmodr = gicd_get_igrpmodr(driver_data->gicd_base, id); 417 } 418 419 /* 420 * If the IGROUP bit is set, then it is a Group 1 Non secure 421 * interrupt 422 */ 423 if (igroup) 424 return INTR_GROUP1NS; 425 426 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 427 if (grpmodr) 428 return INTR_GROUP1S; 429 430 /* Else it is a Group 0 Secure interrupt */ 431 return INTR_GROUP0; 432 } 433