1 /* 2 * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <common/interrupt_props.h> 14 #include <drivers/arm/gic600_multichip.h> 15 #include <drivers/arm/gicv3.h> 16 #include <lib/spinlock.h> 17 #include <plat/common/platform.h> 18 19 #include "gicv3_private.h" 20 21 const gicv3_driver_data_t *gicv3_driver_data; 22 23 /* 24 * Spinlock to guard registers needing read-modify-write. APIs protected by this 25 * spinlock are used either at boot time (when only a single CPU is active), or 26 * when the system is fully coherent. 27 */ 28 static spinlock_t gic_lock; 29 30 /* 31 * Redistributor power operations are weakly bound so that they can be 32 * overridden 33 */ 34 #pragma weak gicv3_rdistif_off 35 #pragma weak gicv3_rdistif_on 36 37 /* Check interrupt ID for SGI/(E)PPI and (E)SPIs */ 38 static bool is_sgi_ppi(unsigned int id); 39 40 /* 41 * Helper macros to save and restore GICR and GICD registers 42 * corresponding to their numbers to and from the context 43 */ 44 #define RESTORE_GICR_REG(base, ctx, name, i) \ 45 gicr_write_##name((base), (i), (ctx)->gicr_##name[(i)]) 46 47 #define SAVE_GICR_REG(base, ctx, name, i) \ 48 (ctx)->gicr_##name[(i)] = gicr_read_##name((base), (i)) 49 50 /* Helper macros to save and restore GICD registers to and from the context */ 51 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 52 do { \ 53 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 54 int_id += (1U << REG##R_SHIFT)) { \ 55 gicd_write_##reg((base), int_id, \ 56 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 57 REG##R_SHIFT]); \ 58 } \ 59 } while (false) 60 61 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 62 do { \ 63 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 64 int_id += (1U << REG##R_SHIFT)) { \ 65 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 66 REG##R_SHIFT] = gicd_read_##reg((base), int_id); \ 67 } \ 68 } while (false) 69 70 #if GIC_EXT_INTID 71 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 72 do { \ 73 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 74 int_id += (1U << REG##R_SHIFT)) { \ 75 gicd_write_##reg((base), int_id, \ 76 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ 77 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ 78 >> REG##R_SHIFT]); \ 79 } \ 80 } while (false) 81 82 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 83 do { \ 84 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 85 int_id += (1U << REG##R_SHIFT)) { \ 86 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ 87 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ 88 >> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\ 89 } \ 90 } while (false) 91 #else 92 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) 93 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) 94 #endif /* GIC_EXT_INTID */ 95 96 /******************************************************************************* 97 * This function initialises the ARM GICv3 driver in EL3 with provided platform 98 * inputs. 99 ******************************************************************************/ 100 void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 101 { 102 unsigned int gic_version; 103 unsigned int gicv2_compat; 104 105 assert(plat_driver_data != NULL); 106 assert(plat_driver_data->gicd_base != 0U); 107 assert(plat_driver_data->rdistif_num != 0U); 108 assert(plat_driver_data->rdistif_base_addrs != NULL); 109 110 assert(IS_IN_EL3()); 111 112 assert((plat_driver_data->interrupt_props_num != 0U) ? 113 (plat_driver_data->interrupt_props != NULL) : 1); 114 115 /* Check for system register support */ 116 #ifndef __aarch64__ 117 assert((read_id_pfr1() & 118 (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); 119 #else 120 assert((read_id_aa64pfr0_el1() & 121 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U); 122 #endif /* !__aarch64__ */ 123 124 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 125 gic_version >>= PIDR2_ARCH_REV_SHIFT; 126 gic_version &= PIDR2_ARCH_REV_MASK; 127 128 /* Check GIC version */ 129 #if !GIC_ENABLE_V4_EXTN 130 assert(gic_version == ARCH_REV_GICV3); 131 #endif 132 /* 133 * Find out whether the GIC supports the GICv2 compatibility mode. 134 * The ARE_S bit resets to 0 if supported 135 */ 136 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 137 gicv2_compat >>= CTLR_ARE_S_SHIFT; 138 gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK; 139 140 if (plat_driver_data->gicr_base != 0U) { 141 /* 142 * Find the base address of each implemented Redistributor interface. 143 * The number of interfaces should be equal to the number of CPUs in the 144 * system. The memory for saving these addresses has to be allocated by 145 * the platform port 146 */ 147 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 148 plat_driver_data->rdistif_num, 149 plat_driver_data->gicr_base, 150 plat_driver_data->mpidr_to_core_pos); 151 #if !HW_ASSISTED_COHERENCY 152 /* 153 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 154 */ 155 flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs), 156 plat_driver_data->rdistif_num * 157 sizeof(*(plat_driver_data->rdistif_base_addrs))); 158 #endif 159 } 160 gicv3_driver_data = plat_driver_data; 161 162 /* 163 * The GIC driver data is initialized by the primary CPU with caches 164 * enabled. When the secondary CPU boots up, it initializes the 165 * GICC/GICR interface with the caches disabled. Hence flush the 166 * driver data to ensure coherency. This is not required if the 167 * platform has HW_ASSISTED_COHERENCY enabled. 168 */ 169 #if !HW_ASSISTED_COHERENCY 170 flush_dcache_range((uintptr_t)&gicv3_driver_data, 171 sizeof(gicv3_driver_data)); 172 flush_dcache_range((uintptr_t)gicv3_driver_data, 173 sizeof(*gicv3_driver_data)); 174 #endif 175 gicv3_check_erratas_applies(plat_driver_data->gicd_base); 176 177 INFO("GICv%u with%s legacy support detected.\n", gic_version, 178 (gicv2_compat == 0U) ? "" : "out"); 179 INFO("ARM GICv%u driver initialized in EL3\n", gic_version); 180 } 181 182 /******************************************************************************* 183 * This function initialises the GIC distributor interface based upon the data 184 * provided by the platform while initialising the driver. 185 ******************************************************************************/ 186 void __init gicv3_distif_init(void) 187 { 188 unsigned int bitmap; 189 190 assert(gicv3_driver_data != NULL); 191 assert(gicv3_driver_data->gicd_base != 0U); 192 193 assert(IS_IN_EL3()); 194 195 /* 196 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 197 * the ARE_S bit. The Distributor might generate a system error 198 * otherwise. 199 */ 200 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 201 CTLR_ENABLE_G0_BIT | 202 CTLR_ENABLE_G1S_BIT | 203 CTLR_ENABLE_G1NS_BIT, 204 RWP_TRUE); 205 206 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 207 gicd_set_ctlr(gicv3_driver_data->gicd_base, 208 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 209 210 /* Set the default attribute of all (E)SPIs */ 211 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); 212 213 bitmap = gicv3_secure_spis_config_props( 214 gicv3_driver_data->gicd_base, 215 gicv3_driver_data->interrupt_props, 216 gicv3_driver_data->interrupt_props_num); 217 218 /* Enable the secure (E)SPIs now that they have been configured */ 219 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 220 } 221 222 /******************************************************************************* 223 * This function initialises the GIC Redistributor interface of the calling CPU 224 * (identified by the 'proc_num' parameter) based upon the data provided by the 225 * platform while initialising the driver. 226 ******************************************************************************/ 227 void gicv3_rdistif_init(unsigned int proc_num) 228 { 229 uintptr_t gicr_base; 230 unsigned int bitmap; 231 uint32_t ctlr; 232 233 assert(gicv3_driver_data != NULL); 234 assert(proc_num < gicv3_driver_data->rdistif_num); 235 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 236 assert(gicv3_driver_data->gicd_base != 0U); 237 238 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base); 239 assert((ctlr & CTLR_ARE_S_BIT) != 0U); 240 241 assert(IS_IN_EL3()); 242 243 /* Power on redistributor */ 244 gicv3_rdistif_on(proc_num); 245 246 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 247 assert(gicr_base != 0U); 248 249 /* Set the default attribute of all SGIs and (E)PPIs */ 250 gicv3_ppi_sgi_config_defaults(gicr_base); 251 252 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, 253 gicv3_driver_data->interrupt_props, 254 gicv3_driver_data->interrupt_props_num); 255 256 /* Enable interrupt groups as required, if not already */ 257 if ((ctlr & bitmap) != bitmap) { 258 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 259 } 260 } 261 262 /******************************************************************************* 263 * Functions to perform power operations on GIC Redistributor 264 ******************************************************************************/ 265 void gicv3_rdistif_off(unsigned int proc_num) 266 { 267 } 268 269 void gicv3_rdistif_on(unsigned int proc_num) 270 { 271 } 272 273 /******************************************************************************* 274 * This function enables the GIC CPU interface of the calling CPU using only 275 * system register accesses. 276 ******************************************************************************/ 277 void gicv3_cpuif_enable(unsigned int proc_num) 278 { 279 uintptr_t gicr_base; 280 u_register_t scr_el3; 281 unsigned int icc_sre_el3; 282 283 assert(gicv3_driver_data != NULL); 284 assert(proc_num < gicv3_driver_data->rdistif_num); 285 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 286 assert(IS_IN_EL3()); 287 288 /* Mark the connected core as awake */ 289 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 290 gicv3_rdistif_mark_core_awake(gicr_base); 291 292 /* Disable the legacy interrupt bypass */ 293 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 294 295 /* 296 * Enable system register access for EL3 and allow lower exception 297 * levels to configure the same for themselves. If the legacy mode is 298 * not supported, the SRE bit is RAO/WI 299 */ 300 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 301 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 302 303 scr_el3 = read_scr_el3(); 304 305 /* 306 * Switch to NS state to write Non secure ICC_SRE_EL1 and 307 * ICC_SRE_EL2 registers. 308 */ 309 write_scr_el3(scr_el3 | SCR_NS_BIT); 310 isb(); 311 312 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 313 write_icc_sre_el1(ICC_SRE_SRE_BIT); 314 isb(); 315 316 /* Switch to secure state. */ 317 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 318 isb(); 319 320 /* Write the secure ICC_SRE_EL1 register */ 321 write_icc_sre_el1(ICC_SRE_SRE_BIT); 322 isb(); 323 324 /* Program the idle priority in the PMR */ 325 write_icc_pmr_el1(GIC_PRI_MASK); 326 327 /* Enable Group0 interrupts */ 328 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 329 330 /* Enable Group1 Secure interrupts */ 331 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 332 IGRPEN1_EL3_ENABLE_G1S_BIT); 333 isb(); 334 /* Add DSB to ensure visibility of System register writes */ 335 dsb(); 336 } 337 338 /******************************************************************************* 339 * This function disables the GIC CPU interface of the calling CPU using 340 * only system register accesses. 341 ******************************************************************************/ 342 void gicv3_cpuif_disable(unsigned int proc_num) 343 { 344 uintptr_t gicr_base; 345 346 assert(gicv3_driver_data != NULL); 347 assert(proc_num < gicv3_driver_data->rdistif_num); 348 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 349 350 assert(IS_IN_EL3()); 351 352 /* Disable legacy interrupt bypass */ 353 write_icc_sre_el3(read_icc_sre_el3() | 354 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 355 356 /* Disable Group0 interrupts */ 357 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 358 ~IGRPEN1_EL1_ENABLE_G0_BIT); 359 360 /* Disable Group1 Secure and Non-Secure interrupts */ 361 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 362 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 363 IGRPEN1_EL3_ENABLE_G1S_BIT)); 364 365 /* Synchronise accesses to group enable registers */ 366 isb(); 367 /* Add DSB to ensure visibility of System register writes */ 368 dsb(); 369 370 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 371 assert(gicr_base != 0UL); 372 373 /* 374 * dsb() already issued previously after clearing the CPU group 375 * enabled, apply below workaround to toggle the "DPG*" 376 * bits of GICR_CTLR register for unblocking event. 377 */ 378 gicv3_apply_errata_wa_2384374(gicr_base); 379 380 /* Mark the connected core as asleep */ 381 gicv3_rdistif_mark_core_asleep(gicr_base); 382 } 383 384 /******************************************************************************* 385 * This function returns the id of the highest priority pending interrupt at 386 * the GIC cpu interface. 387 ******************************************************************************/ 388 unsigned int gicv3_get_pending_interrupt_id(void) 389 { 390 unsigned int id; 391 392 assert(IS_IN_EL3()); 393 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 394 395 /* 396 * If the ID is special identifier corresponding to G1S or G1NS 397 * interrupt, then read the highest pending group 1 interrupt. 398 */ 399 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) { 400 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 401 } 402 403 return id; 404 } 405 406 /******************************************************************************* 407 * This function returns the type of the highest priority pending interrupt at 408 * the GIC cpu interface. The return values can be one of the following : 409 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 410 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 411 * 0 - 1019 : The interrupt type is secure Group 0. 412 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 413 * sufficient priority to be signaled 414 ******************************************************************************/ 415 unsigned int gicv3_get_pending_interrupt_type(void) 416 { 417 assert(IS_IN_EL3()); 418 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 419 } 420 421 /******************************************************************************* 422 * This function returns the type of the interrupt id depending upon the group 423 * this interrupt has been configured under by the interrupt controller i.e. 424 * group0 or group1 Secure / Non Secure. The return value can be one of the 425 * following : 426 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 427 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 428 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 429 * interrupt. 430 ******************************************************************************/ 431 unsigned int gicv3_get_interrupt_type(unsigned int id, unsigned int proc_num) 432 { 433 unsigned int igroup, grpmodr; 434 uintptr_t gicr_base; 435 uintptr_t gicd_base; 436 437 assert(IS_IN_EL3()); 438 assert(gicv3_driver_data != NULL); 439 440 /* Ensure the parameters are valid */ 441 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID)); 442 assert(proc_num < gicv3_driver_data->rdistif_num); 443 444 /* All LPI interrupts are Group 1 non secure */ 445 if (id >= MIN_LPI_ID) { 446 return INTR_GROUP1NS; 447 } 448 449 /* Check interrupt ID */ 450 if (is_sgi_ppi(id)) { 451 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 452 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 453 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 454 igroup = gicr_get_igroupr(gicr_base, id); 455 grpmodr = gicr_get_igrpmodr(gicr_base, id); 456 } else { 457 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 458 assert(gicv3_driver_data->gicd_base != 0U); 459 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 460 igroup = gicd_get_igroupr(gicd_base, id); 461 grpmodr = gicd_get_igrpmodr(gicd_base, id); 462 } 463 464 /* 465 * If the IGROUP bit is set, then it is a Group 1 Non secure 466 * interrupt 467 */ 468 if (igroup != 0U) { 469 return INTR_GROUP1NS; 470 } 471 472 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 473 if (grpmodr != 0U) { 474 return INTR_GROUP1S; 475 } 476 477 /* Else it is a Group 0 Secure interrupt */ 478 return INTR_GROUP0; 479 } 480 481 /***************************************************************************** 482 * Function to save and disable the GIC ITS register context. The power 483 * management of GIC ITS is implementation-defined and this function doesn't 484 * save any memory structures required to support ITS. As the sequence to save 485 * this state is implementation defined, it should be executed in platform 486 * specific code. Calling this function alone and then powering down the GIC and 487 * ITS without implementing the aforementioned platform specific code will 488 * corrupt the ITS state. 489 * 490 * This function must be invoked after the GIC CPU interface is disabled. 491 *****************************************************************************/ 492 void gicv3_its_save_disable(uintptr_t gits_base, 493 gicv3_its_ctx_t * const its_ctx) 494 { 495 unsigned int i; 496 497 assert(gicv3_driver_data != NULL); 498 assert(IS_IN_EL3()); 499 assert(its_ctx != NULL); 500 assert(gits_base != 0U); 501 502 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 503 504 /* Disable the ITS */ 505 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 506 507 /* Wait for quiescent state */ 508 gits_wait_for_quiescent_bit(gits_base); 509 510 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 511 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 512 513 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 514 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 515 } 516 } 517 518 /***************************************************************************** 519 * Function to restore the GIC ITS register context. The power 520 * management of GIC ITS is implementation defined and this function doesn't 521 * restore any memory structures required to support ITS. The assumption is 522 * that these structures are in memory and are retained during system suspend. 523 * 524 * This must be invoked before the GIC CPU interface is enabled. 525 *****************************************************************************/ 526 void gicv3_its_restore(uintptr_t gits_base, 527 const gicv3_its_ctx_t * const its_ctx) 528 { 529 unsigned int i; 530 531 assert(gicv3_driver_data != NULL); 532 assert(IS_IN_EL3()); 533 assert(its_ctx != NULL); 534 assert(gits_base != 0U); 535 536 /* Assert that the GITS is disabled and quiescent */ 537 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 538 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U); 539 540 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 541 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 542 543 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 544 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 545 } 546 547 /* Restore the ITS CTLR but leave the ITS disabled */ 548 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 549 } 550 551 /***************************************************************************** 552 * Function to save the GIC Redistributor register context. This function 553 * must be invoked after CPU interface disable and prior to Distributor save. 554 *****************************************************************************/ 555 void gicv3_rdistif_save(unsigned int proc_num, 556 gicv3_redist_ctx_t * const rdist_ctx) 557 { 558 uintptr_t gicr_base; 559 unsigned int i, ppi_regs_num, regs_num; 560 561 assert(gicv3_driver_data != NULL); 562 assert(proc_num < gicv3_driver_data->rdistif_num); 563 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 564 assert(IS_IN_EL3()); 565 assert(rdist_ctx != NULL); 566 567 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 568 569 #if GIC_EXT_INTID 570 /* Calculate number of PPI registers */ 571 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 572 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 573 /* All other values except PPInum [0-2] are reserved */ 574 if (ppi_regs_num > 3U) { 575 ppi_regs_num = 1U; 576 } 577 #else 578 ppi_regs_num = 1U; 579 #endif 580 /* 581 * Wait for any write to GICR_CTLR to complete before trying to save any 582 * state. 583 */ 584 gicr_wait_for_pending_write(gicr_base); 585 586 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 587 588 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 589 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 590 591 /* 32 interrupt IDs per register */ 592 for (i = 0U; i < ppi_regs_num; ++i) { 593 SAVE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 594 SAVE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 595 SAVE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 596 SAVE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 597 SAVE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 598 } 599 600 /* 16 interrupt IDs per GICR_ICFGR register */ 601 regs_num = ppi_regs_num << 1; 602 for (i = 0U; i < regs_num; ++i) { 603 SAVE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 604 } 605 606 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 607 608 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 609 regs_num = ppi_regs_num << 3; 610 for (i = 0U; i < regs_num; ++i) { 611 rdist_ctx->gicr_ipriorityr[i] = 612 gicr_ipriorityr_read(gicr_base, i); 613 } 614 615 /* 616 * Call the pre-save hook that implements the IMP DEF sequence that may 617 * be required on some GIC implementations. As this may need to access 618 * the Redistributor registers, we pass it proc_num. 619 */ 620 gicv3_distif_pre_save(proc_num); 621 } 622 623 /***************************************************************************** 624 * Function to restore the GIC Redistributor register context. We disable 625 * LPI and per-cpu interrupts before we start restore of the Redistributor. 626 * This function must be invoked after Distributor restore but prior to 627 * CPU interface enable. The pending and active interrupts are restored 628 * after the interrupts are fully configured and enabled. 629 *****************************************************************************/ 630 void gicv3_rdistif_init_restore(unsigned int proc_num, 631 const gicv3_redist_ctx_t * const rdist_ctx) 632 { 633 uintptr_t gicr_base; 634 unsigned int i, ppi_regs_num, regs_num; 635 636 assert(gicv3_driver_data != NULL); 637 assert(proc_num < gicv3_driver_data->rdistif_num); 638 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 639 assert(IS_IN_EL3()); 640 assert(rdist_ctx != NULL); 641 642 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 643 644 #if GIC_EXT_INTID 645 /* Calculate number of PPI registers */ 646 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 647 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 648 /* All other values except PPInum [0-2] are reserved */ 649 if (ppi_regs_num > 3U) { 650 ppi_regs_num = 1U; 651 } 652 #else 653 ppi_regs_num = 1U; 654 #endif 655 /* Power on redistributor */ 656 gicv3_rdistif_on(proc_num); 657 658 /* 659 * Call the post-restore hook that implements the IMP DEF sequence that 660 * may be required on some GIC implementations. As this may need to 661 * access the Redistributor registers, we pass it proc_num. 662 */ 663 gicv3_distif_post_restore(proc_num); 664 665 /* 666 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 667 * This is a more scalable approach as it avoids clearing the enable 668 * bits in the GICD_CTLR. 669 */ 670 for (i = 0U; i < ppi_regs_num; ++i) { 671 gicr_write_icenabler(gicr_base, i, ~0U); 672 } 673 674 /* Wait for pending writes to GICR_ICENABLER */ 675 gicr_wait_for_pending_write(gicr_base); 676 677 /* 678 * Disable the LPIs to avoid unpredictable behavior when writing to 679 * GICR_PROPBASER and GICR_PENDBASER. 680 */ 681 gicr_write_ctlr(gicr_base, 682 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 683 684 /* Restore registers' content */ 685 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 686 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 687 688 /* 32 interrupt IDs per register */ 689 for (i = 0U; i < ppi_regs_num; ++i) { 690 RESTORE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 691 RESTORE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 692 } 693 694 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 695 regs_num = ppi_regs_num << 3; 696 for (i = 0U; i < regs_num; ++i) { 697 gicr_ipriorityr_write(gicr_base, i, 698 rdist_ctx->gicr_ipriorityr[i]); 699 } 700 701 /* 16 interrupt IDs per GICR_ICFGR register */ 702 regs_num = ppi_regs_num << 1; 703 for (i = 0U; i < regs_num; ++i) { 704 RESTORE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 705 } 706 707 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 708 709 /* Restore after group and priorities are set. 710 * 32 interrupt IDs per register 711 */ 712 for (i = 0U; i < ppi_regs_num; ++i) { 713 RESTORE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 714 RESTORE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 715 } 716 717 /* 718 * Wait for all writes to the Distributor to complete before enabling 719 * the SGI and (E)PPIs. 720 */ 721 gicr_wait_for_upstream_pending_write(gicr_base); 722 723 /* 32 interrupt IDs per GICR_ISENABLER register */ 724 for (i = 0U; i < ppi_regs_num; ++i) { 725 RESTORE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 726 } 727 728 /* 729 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 730 * the first write to GICR_CTLR was still in flight (this write only 731 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 732 * bit). 733 */ 734 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 735 gicr_wait_for_pending_write(gicr_base); 736 } 737 738 /***************************************************************************** 739 * Function to save the GIC Distributor register context. This function 740 * must be invoked after CPU interface disable and Redistributor save. 741 *****************************************************************************/ 742 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 743 { 744 assert(gicv3_driver_data != NULL); 745 assert(gicv3_driver_data->gicd_base != 0U); 746 assert(IS_IN_EL3()); 747 assert(dist_ctx != NULL); 748 749 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 750 unsigned int num_ints = gicv3_get_spi_limit(gicd_base); 751 #if GIC_EXT_INTID 752 unsigned int num_eints = gicv3_get_espi_limit(gicd_base); 753 #endif 754 755 /* Wait for pending write to complete */ 756 gicd_wait_for_pending_write(gicd_base); 757 758 /* Save the GICD_CTLR */ 759 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 760 761 /* Save GICD_IGROUPR for INTIDs 32 - 1019 */ 762 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 763 764 /* Save GICD_IGROUPRE for INTIDs 4096 - 5119 */ 765 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 766 767 /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */ 768 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 769 770 /* Save GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 771 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 772 773 /* Save GICD_ISPENDR for INTIDs 32 - 1019 */ 774 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 775 776 /* Save GICD_ISPENDRE for INTIDs 4096 - 5119 */ 777 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 778 779 /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */ 780 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 781 782 /* Save GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 783 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 784 785 /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */ 786 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 787 788 /* Save GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 789 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 790 791 /* Save GICD_ICFGR for INTIDs 32 - 1019 */ 792 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 793 794 /* Save GICD_ICFGRE for INTIDs 4096 - 5119 */ 795 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 796 797 /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */ 798 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 799 800 /* Save GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 801 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 802 803 /* Save GICD_NSACR for INTIDs 32 - 1019 */ 804 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 805 806 /* Save GICD_NSACRE for INTIDs 4096 - 5119 */ 807 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 808 809 /* Save GICD_IROUTER for INTIDs 32 - 1019 */ 810 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 811 812 /* Save GICD_IROUTERE for INTIDs 4096 - 5119 */ 813 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 814 815 /* 816 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 817 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 818 * driver. 819 */ 820 } 821 822 /***************************************************************************** 823 * Function to restore the GIC Distributor register context. We disable G0, G1S 824 * and G1NS interrupt groups before we start restore of the Distributor. This 825 * function must be invoked prior to Redistributor restore and CPU interface 826 * enable. The pending and active interrupts are restored after the interrupts 827 * are fully configured and enabled. 828 *****************************************************************************/ 829 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 830 { 831 assert(gicv3_driver_data != NULL); 832 assert(gicv3_driver_data->gicd_base != 0U); 833 assert(IS_IN_EL3()); 834 assert(dist_ctx != NULL); 835 836 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 837 838 /* 839 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 840 * the ARE_S bit. The Distributor might generate a system error 841 * otherwise. 842 */ 843 gicd_clr_ctlr(gicd_base, 844 CTLR_ENABLE_G0_BIT | 845 CTLR_ENABLE_G1S_BIT | 846 CTLR_ENABLE_G1NS_BIT, 847 RWP_TRUE); 848 849 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 850 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 851 852 unsigned int num_ints = gicv3_get_spi_limit(gicd_base); 853 #if GIC_EXT_INTID 854 unsigned int num_eints = gicv3_get_espi_limit(gicd_base); 855 #endif 856 /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */ 857 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 858 859 /* Restore GICD_IGROUPRE for INTIDs 4096 - 5119 */ 860 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 861 862 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */ 863 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 864 865 /* Restore GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 866 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 867 868 /* Restore GICD_ICFGR for INTIDs 32 - 1019 */ 869 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 870 871 /* Restore GICD_ICFGRE for INTIDs 4096 - 5119 */ 872 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 873 874 /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */ 875 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 876 877 /* Restore GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 878 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 879 880 /* Restore GICD_NSACR for INTIDs 32 - 1019 */ 881 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 882 883 /* Restore GICD_NSACRE for INTIDs 4096 - 5119 */ 884 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 885 886 /* Restore GICD_IROUTER for INTIDs 32 - 1019 */ 887 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 888 889 /* Restore GICD_IROUTERE for INTIDs 4096 - 5119 */ 890 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 891 892 /* 893 * Restore ISENABLER(E), ISPENDR(E) and ISACTIVER(E) after 894 * the interrupts are configured. 895 */ 896 897 /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */ 898 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 899 900 /* Restore GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 901 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 902 903 /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */ 904 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 905 906 /* Restore GICD_ISPENDRE for INTIDs 4096 - 5119 */ 907 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 908 909 /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */ 910 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 911 912 /* Restore GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 913 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 914 915 /* Restore the GICD_CTLR */ 916 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 917 gicd_wait_for_pending_write(gicd_base); 918 } 919 920 /******************************************************************************* 921 * This function gets the priority of the interrupt the processor is currently 922 * servicing. 923 ******************************************************************************/ 924 unsigned int gicv3_get_running_priority(void) 925 { 926 return (unsigned int)read_icc_rpr_el1(); 927 } 928 929 /******************************************************************************* 930 * This function checks if the interrupt identified by id is active (whether the 931 * state is either active, or active and pending). The proc_num is used if the 932 * interrupt is SGI or (E)PPI and programs the corresponding Redistributor 933 * interface. 934 ******************************************************************************/ 935 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) 936 { 937 uintptr_t gicd_base; 938 939 assert(gicv3_driver_data != NULL); 940 assert(gicv3_driver_data->gicd_base != 0U); 941 assert(proc_num < gicv3_driver_data->rdistif_num); 942 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 943 944 /* Check interrupt ID */ 945 if (is_sgi_ppi(id)) { 946 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 947 return gicr_get_isactiver( 948 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 949 } 950 951 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 952 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 953 return gicd_get_isactiver(gicd_base, id); 954 } 955 956 /******************************************************************************* 957 * This function enables the interrupt identified by id. The proc_num 958 * is used if the interrupt is SGI or PPI, and programs the corresponding 959 * Redistributor interface. 960 ******************************************************************************/ 961 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) 962 { 963 uintptr_t gicd_base; 964 965 assert(gicv3_driver_data != NULL); 966 assert(gicv3_driver_data->gicd_base != 0U); 967 assert(proc_num < gicv3_driver_data->rdistif_num); 968 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 969 970 /* 971 * Ensure that any shared variable updates depending on out of band 972 * interrupt trigger are observed before enabling interrupt. 973 */ 974 dsbishst(); 975 976 /* Check interrupt ID */ 977 if (is_sgi_ppi(id)) { 978 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 979 gicr_set_isenabler( 980 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 981 } else { 982 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 983 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 984 gicd_set_isenabler(gicd_base, id); 985 } 986 } 987 988 /******************************************************************************* 989 * This function disables the interrupt identified by id. The proc_num 990 * is used if the interrupt is SGI or PPI, and programs the corresponding 991 * Redistributor interface. 992 ******************************************************************************/ 993 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) 994 { 995 uintptr_t gicd_base; 996 997 assert(gicv3_driver_data != NULL); 998 assert(gicv3_driver_data->gicd_base != 0U); 999 assert(proc_num < gicv3_driver_data->rdistif_num); 1000 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1001 1002 /* 1003 * Disable interrupt, and ensure that any shared variable updates 1004 * depending on out of band interrupt trigger are observed afterwards. 1005 */ 1006 1007 /* Check interrupt ID */ 1008 if (is_sgi_ppi(id)) { 1009 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1010 gicr_set_icenabler( 1011 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1012 1013 /* Write to clear enable requires waiting for pending writes */ 1014 gicr_wait_for_pending_write( 1015 gicv3_driver_data->rdistif_base_addrs[proc_num]); 1016 } else { 1017 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1018 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1019 gicd_set_icenabler(gicd_base, id); 1020 1021 /* Write to clear enable requires waiting for pending writes */ 1022 gicd_wait_for_pending_write(gicd_base); 1023 } 1024 1025 dsbishst(); 1026 } 1027 1028 /******************************************************************************* 1029 * This function sets the interrupt priority as supplied for the given interrupt 1030 * id. 1031 ******************************************************************************/ 1032 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 1033 unsigned int priority) 1034 { 1035 uintptr_t gicr_base; 1036 uintptr_t gicd_base; 1037 1038 assert(gicv3_driver_data != NULL); 1039 assert(gicv3_driver_data->gicd_base != 0U); 1040 assert(proc_num < gicv3_driver_data->rdistif_num); 1041 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1042 1043 /* Check interrupt ID */ 1044 if (is_sgi_ppi(id)) { 1045 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1046 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1047 gicr_set_ipriorityr(gicr_base, id, priority); 1048 } else { 1049 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1050 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1051 gicd_set_ipriorityr(gicd_base, id, priority); 1052 } 1053 } 1054 1055 /******************************************************************************* 1056 * This function assigns group for the interrupt identified by id. The proc_num 1057 * is used if the interrupt is SGI or (E)PPI, and programs the corresponding 1058 * Redistributor interface. The group can be any of GICV3_INTR_GROUP* 1059 ******************************************************************************/ 1060 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 1061 unsigned int type) 1062 { 1063 bool igroup = false, grpmod = false; 1064 uintptr_t gicr_base; 1065 uintptr_t gicd_base; 1066 1067 assert(gicv3_driver_data != NULL); 1068 assert(gicv3_driver_data->gicd_base != 0U); 1069 assert(proc_num < gicv3_driver_data->rdistif_num); 1070 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1071 1072 switch (type) { 1073 case INTR_GROUP1S: 1074 igroup = false; 1075 grpmod = true; 1076 break; 1077 case INTR_GROUP0: 1078 igroup = false; 1079 grpmod = false; 1080 break; 1081 case INTR_GROUP1NS: 1082 igroup = true; 1083 grpmod = false; 1084 break; 1085 default: 1086 assert(false); 1087 break; 1088 } 1089 1090 /* Check interrupt ID */ 1091 if (is_sgi_ppi(id)) { 1092 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1093 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1094 1095 igroup ? gicr_set_igroupr(gicr_base, id) : 1096 gicr_clr_igroupr(gicr_base, id); 1097 grpmod ? gicr_set_igrpmodr(gicr_base, id) : 1098 gicr_clr_igrpmodr(gicr_base, id); 1099 } else { 1100 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1101 1102 /* Serialize read-modify-write to Distributor registers */ 1103 spin_lock(&gic_lock); 1104 1105 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1106 1107 igroup ? gicd_set_igroupr(gicd_base, id) : 1108 gicd_clr_igroupr(gicd_base, id); 1109 grpmod ? gicd_set_igrpmodr(gicd_base, id) : 1110 gicd_clr_igrpmodr(gicd_base, id); 1111 1112 spin_unlock(&gic_lock); 1113 } 1114 } 1115 1116 /******************************************************************************* 1117 * This function raises the specified SGI of the specified group. 1118 * 1119 * The target parameter must be a valid MPIDR in the system. 1120 ******************************************************************************/ 1121 void gicv3_raise_sgi(unsigned int sgi_num, gicv3_irq_group_t group, 1122 u_register_t target) 1123 { 1124 unsigned int tgt, aff3, aff2, aff1, aff0; 1125 uint64_t sgi_val; 1126 1127 /* Verify interrupt number is in the SGI range */ 1128 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID)); 1129 1130 /* Extract affinity fields from target */ 1131 aff0 = MPIDR_AFFLVL0_VAL(target); 1132 aff1 = MPIDR_AFFLVL1_VAL(target); 1133 aff2 = MPIDR_AFFLVL2_VAL(target); 1134 aff3 = MPIDR_AFFLVL3_VAL(target); 1135 1136 /* 1137 * Make target list from affinity 0, and ensure GICv3 SGI can target 1138 * this PE. 1139 */ 1140 assert(aff0 < GICV3_MAX_SGI_TARGETS); 1141 tgt = BIT_32(aff0); 1142 1143 /* Raise SGI to PE specified by its affinity */ 1144 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF, 1145 tgt); 1146 1147 /* 1148 * Ensure that any shared variable updates depending on out of band 1149 * interrupt trigger are observed before raising SGI. 1150 */ 1151 dsbishst(); 1152 1153 switch (group) { 1154 case GICV3_G0: 1155 write_icc_sgi0r_el1(sgi_val); 1156 break; 1157 case GICV3_G1NS: 1158 write_icc_asgi1r(sgi_val); 1159 break; 1160 case GICV3_G1S: 1161 write_icc_sgi1r(sgi_val); 1162 break; 1163 default: 1164 assert(false); 1165 break; 1166 } 1167 1168 isb(); 1169 } 1170 1171 /******************************************************************************* 1172 * This function sets the interrupt routing for the given (E)SPI interrupt id. 1173 * The interrupt routing is specified in routing mode and mpidr. 1174 * 1175 * The routing mode can be either of: 1176 * - GICV3_IRM_ANY 1177 * - GICV3_IRM_PE 1178 * 1179 * The mpidr is the affinity of the PE to which the interrupt will be routed, 1180 * and is ignored for routing mode GICV3_IRM_ANY. 1181 ******************************************************************************/ 1182 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr) 1183 { 1184 unsigned long long aff; 1185 uint64_t router; 1186 uintptr_t gicd_base; 1187 1188 assert(gicv3_driver_data != NULL); 1189 assert(gicv3_driver_data->gicd_base != 0U); 1190 1191 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE)); 1192 1193 assert(IS_SPI(id)); 1194 1195 aff = gicd_irouter_val_from_mpidr(mpidr, irm); 1196 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1197 gicd_write_irouter(gicd_base, id, aff); 1198 1199 /* 1200 * In implementations that do not require 1 of N distribution of SPIs, 1201 * IRM might be RAZ/WI. Read back and verify IRM bit. 1202 */ 1203 if (irm == GICV3_IRM_ANY) { 1204 router = gicd_read_irouter(gicd_base, id); 1205 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) { 1206 ERROR("GICv3 implementation doesn't support routing ANY\n"); 1207 panic(); 1208 } 1209 } 1210 } 1211 1212 /******************************************************************************* 1213 * This function clears the pending status of an interrupt identified by id. 1214 * The proc_num is used if the interrupt is SGI or (E)PPI, and programs the 1215 * corresponding Redistributor interface. 1216 ******************************************************************************/ 1217 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num) 1218 { 1219 uintptr_t gicd_base; 1220 1221 assert(gicv3_driver_data != NULL); 1222 assert(gicv3_driver_data->gicd_base != 0U); 1223 assert(proc_num < gicv3_driver_data->rdistif_num); 1224 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1225 1226 /* 1227 * Clear pending interrupt, and ensure that any shared variable updates 1228 * depending on out of band interrupt trigger are observed afterwards. 1229 */ 1230 1231 /* Check interrupt ID */ 1232 if (is_sgi_ppi(id)) { 1233 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1234 gicr_set_icpendr( 1235 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1236 } else { 1237 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1238 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1239 gicd_set_icpendr(gicd_base, id); 1240 } 1241 1242 dsbishst(); 1243 } 1244 1245 /******************************************************************************* 1246 * This function sets the pending status of an interrupt identified by id. 1247 * The proc_num is used if the interrupt is SGI or PPI and programs the 1248 * corresponding Redistributor interface. 1249 ******************************************************************************/ 1250 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num) 1251 { 1252 uintptr_t gicd_base; 1253 1254 assert(gicv3_driver_data != NULL); 1255 assert(gicv3_driver_data->gicd_base != 0U); 1256 assert(proc_num < gicv3_driver_data->rdistif_num); 1257 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1258 1259 /* 1260 * Ensure that any shared variable updates depending on out of band 1261 * interrupt trigger are observed before setting interrupt pending. 1262 */ 1263 dsbishst(); 1264 1265 /* Check interrupt ID */ 1266 if (is_sgi_ppi(id)) { 1267 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1268 gicr_set_ispendr( 1269 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1270 } else { 1271 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1272 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1273 gicd_set_ispendr(gicd_base, id); 1274 } 1275 } 1276 1277 /******************************************************************************* 1278 * This function sets the PMR register with the supplied value. Returns the 1279 * original PMR. 1280 ******************************************************************************/ 1281 unsigned int gicv3_set_pmr(unsigned int mask) 1282 { 1283 unsigned int old_mask; 1284 1285 old_mask = (unsigned int)read_icc_pmr_el1(); 1286 1287 /* 1288 * Order memory updates w.r.t. PMR write, and ensure they're visible 1289 * before potential out of band interrupt trigger because of PMR update. 1290 * PMR system register writes are self-synchronizing, so no ISB required 1291 * thereafter. 1292 */ 1293 dsbishst(); 1294 write_icc_pmr_el1(mask); 1295 1296 return old_mask; 1297 } 1298 1299 /******************************************************************************* 1300 * This function delegates the responsibility of discovering the corresponding 1301 * Redistributor frames to each CPU itself. It is a modified version of 1302 * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform 1303 * unlike the previous way in which only the Primary CPU did the discovery of 1304 * all the Redistributor frames for every CPU. It also handles the scenario in 1305 * which the frames of various CPUs are not contiguous in physical memory. 1306 ******************************************************************************/ 1307 int gicv3_rdistif_probe(const uintptr_t gicr_frame) 1308 { 1309 u_register_t mpidr, mpidr_self; 1310 unsigned int proc_num; 1311 uint64_t typer_val; 1312 uintptr_t rdistif_base; 1313 bool gicr_frame_found = false; 1314 1315 assert(gicv3_driver_data->gicr_base == 0U); 1316 1317 if (plat_can_cmo()) { 1318 /* Ensure this function is called with Data Cache enabled */ 1319 #ifndef __aarch64__ 1320 assert((read_sctlr() & SCTLR_C_BIT) != 0U); 1321 #else 1322 assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U); 1323 #endif /* !__aarch64__ */ 1324 } 1325 1326 mpidr_self = read_mpidr_el1() & MPIDR_AFFINITY_MASK; 1327 rdistif_base = gicr_frame; 1328 do { 1329 typer_val = gicr_read_typer(rdistif_base); 1330 mpidr = mpidr_from_gicr_typer(typer_val); 1331 if (gicv3_driver_data->mpidr_to_core_pos != NULL) { 1332 proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr); 1333 } else { 1334 proc_num = (unsigned int)(typer_val >> 1335 TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK; 1336 } 1337 if (mpidr == mpidr_self) { 1338 /* The base address doesn't need to be initialized on 1339 * every warm boot. 1340 */ 1341 if (gicv3_driver_data->rdistif_base_addrs[proc_num] 1342 != 0U) { 1343 return 0; 1344 } 1345 gicv3_driver_data->rdistif_base_addrs[proc_num] = 1346 rdistif_base; 1347 gicr_frame_found = true; 1348 break; 1349 } 1350 rdistif_base += gicv3_redist_size(typer_val); 1351 } while ((typer_val & TYPER_LAST_BIT) == 0U); 1352 1353 if (!gicr_frame_found) { 1354 return -1; 1355 } 1356 1357 /* 1358 * Flush the driver data to ensure coherency. This is 1359 * not required if platform has HW_ASSISTED_COHERENCY 1360 * enabled. 1361 */ 1362 #if !HW_ASSISTED_COHERENCY 1363 /* 1364 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 1365 */ 1366 flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]), 1367 sizeof(*(gicv3_driver_data->rdistif_base_addrs))); 1368 #endif 1369 return 0; /* Found matching GICR frame */ 1370 } 1371 1372 /****************************************************************************** 1373 * This function checks the interrupt ID and returns true for SGIs and (E)PPIs 1374 * and false for (E)SPIs IDs. 1375 *****************************************************************************/ 1376 static bool is_sgi_ppi(unsigned int id) 1377 { 1378 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 1379 if (IS_SGI_PPI(id)) { 1380 return true; 1381 } 1382 1383 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 1384 if (IS_SPI(id)) { 1385 return false; 1386 } 1387 1388 assert(false); 1389 panic(); 1390 } 1391