1 /* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <common/interrupt_props.h> 14 #include <drivers/arm/gic600_multichip.h> 15 #include <drivers/arm/gicv3.h> 16 #include <lib/spinlock.h> 17 #include <plat/common/platform.h> 18 19 #include "gicv3_private.h" 20 21 const gicv3_driver_data_t *gicv3_driver_data; 22 23 /* 24 * Spinlock to guard registers needing read-modify-write. APIs protected by this 25 * spinlock are used either at boot time (when only a single CPU is active), or 26 * when the system is fully coherent. 27 */ 28 static spinlock_t gic_lock; 29 30 /* 31 * Redistributor power operations are weakly bound so that they can be 32 * overridden 33 */ 34 #pragma weak gicv3_rdistif_off 35 #pragma weak gicv3_rdistif_on 36 37 /* Check interrupt ID for SGI/(E)PPI and (E)SPIs */ 38 static bool is_sgi_ppi(unsigned int id); 39 40 /* 41 * Helper macros to save and restore GICR and GICD registers 42 * corresponding to their numbers to and from the context 43 */ 44 #define RESTORE_GICR_REG(base, ctx, name, i) \ 45 gicr_write_##name((base), (i), (ctx)->gicr_##name[(i)]) 46 47 #define SAVE_GICR_REG(base, ctx, name, i) \ 48 (ctx)->gicr_##name[(i)] = gicr_read_##name((base), (i)) 49 50 /* Helper macros to save and restore GICD registers to and from the context */ 51 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 52 do { \ 53 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 54 int_id += (1U << REG##R_SHIFT)) { \ 55 gicd_write_##reg((base), int_id, \ 56 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 57 REG##R_SHIFT]); \ 58 } \ 59 } while (false) 60 61 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 62 do { \ 63 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 64 int_id += (1U << REG##R_SHIFT)) { \ 65 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 66 REG##R_SHIFT] = gicd_read_##reg((base), int_id); \ 67 } \ 68 } while (false) 69 70 #if GIC_EXT_INTID 71 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 72 do { \ 73 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 74 int_id += (1U << REG##R_SHIFT)) { \ 75 gicd_write_##reg((base), int_id, \ 76 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ 77 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ 78 >> REG##R_SHIFT]); \ 79 } \ 80 } while (false) 81 82 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 83 do { \ 84 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 85 int_id += (1U << REG##R_SHIFT)) { \ 86 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ 87 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ 88 >> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\ 89 } \ 90 } while (false) 91 #else 92 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) 93 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) 94 #endif /* GIC_EXT_INTID */ 95 96 /******************************************************************************* 97 * This function initialises the ARM GICv3 driver in EL3 with provided platform 98 * inputs. 99 ******************************************************************************/ 100 void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 101 { 102 unsigned int gic_version; 103 unsigned int gicv2_compat; 104 105 assert(plat_driver_data != NULL); 106 assert(plat_driver_data->gicd_base != 0U); 107 assert(plat_driver_data->rdistif_num != 0U); 108 assert(plat_driver_data->rdistif_base_addrs != NULL); 109 110 assert(IS_IN_EL3()); 111 112 assert((plat_driver_data->interrupt_props_num != 0U) ? 113 (plat_driver_data->interrupt_props != NULL) : 1); 114 115 /* Check for system register support */ 116 #ifndef __aarch64__ 117 assert((read_id_pfr1() & 118 (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); 119 #else 120 assert((read_id_aa64pfr0_el1() & 121 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U); 122 #endif /* !__aarch64__ */ 123 124 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 125 gic_version >>= PIDR2_ARCH_REV_SHIFT; 126 gic_version &= PIDR2_ARCH_REV_MASK; 127 128 /* Check GIC version */ 129 #if !GIC_ENABLE_V4_EXTN 130 assert(gic_version == ARCH_REV_GICV3); 131 #endif 132 /* 133 * Find out whether the GIC supports the GICv2 compatibility mode. 134 * The ARE_S bit resets to 0 if supported 135 */ 136 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 137 gicv2_compat >>= CTLR_ARE_S_SHIFT; 138 gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK; 139 140 if (plat_driver_data->gicr_base != 0U) { 141 /* 142 * Find the base address of each implemented Redistributor interface. 143 * The number of interfaces should be equal to the number of CPUs in the 144 * system. The memory for saving these addresses has to be allocated by 145 * the platform port 146 */ 147 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 148 plat_driver_data->rdistif_num, 149 plat_driver_data->gicr_base, 150 plat_driver_data->mpidr_to_core_pos); 151 #if !HW_ASSISTED_COHERENCY 152 /* 153 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 154 */ 155 flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs), 156 plat_driver_data->rdistif_num * 157 sizeof(*(plat_driver_data->rdistif_base_addrs))); 158 #endif 159 } 160 gicv3_driver_data = plat_driver_data; 161 162 /* 163 * The GIC driver data is initialized by the primary CPU with caches 164 * enabled. When the secondary CPU boots up, it initializes the 165 * GICC/GICR interface with the caches disabled. Hence flush the 166 * driver data to ensure coherency. This is not required if the 167 * platform has HW_ASSISTED_COHERENCY enabled. 168 */ 169 #if !HW_ASSISTED_COHERENCY 170 flush_dcache_range((uintptr_t)&gicv3_driver_data, 171 sizeof(gicv3_driver_data)); 172 flush_dcache_range((uintptr_t)gicv3_driver_data, 173 sizeof(*gicv3_driver_data)); 174 #endif 175 gicv3_check_erratas_applies(plat_driver_data->gicd_base); 176 177 INFO("GICv%u with%s legacy support detected.\n", gic_version, 178 (gicv2_compat == 0U) ? "" : "out"); 179 INFO("ARM GICv%u driver initialized in EL3\n", gic_version); 180 } 181 182 /******************************************************************************* 183 * This function initialises the GIC distributor interface based upon the data 184 * provided by the platform while initialising the driver. 185 ******************************************************************************/ 186 void __init gicv3_distif_init(void) 187 { 188 unsigned int bitmap; 189 190 assert(gicv3_driver_data != NULL); 191 assert(gicv3_driver_data->gicd_base != 0U); 192 193 assert(IS_IN_EL3()); 194 195 /* 196 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 197 * the ARE_S bit. The Distributor might generate a system error 198 * otherwise. 199 */ 200 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 201 CTLR_ENABLE_G0_BIT | 202 CTLR_ENABLE_G1S_BIT | 203 CTLR_ENABLE_G1NS_BIT, 204 RWP_TRUE); 205 206 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 207 gicd_set_ctlr(gicv3_driver_data->gicd_base, 208 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 209 210 /* Set the default attribute of all (E)SPIs */ 211 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); 212 213 bitmap = gicv3_secure_spis_config_props( 214 gicv3_driver_data->gicd_base, 215 gicv3_driver_data->interrupt_props, 216 gicv3_driver_data->interrupt_props_num); 217 218 /* Enable the secure (E)SPIs now that they have been configured */ 219 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 220 } 221 222 /******************************************************************************* 223 * This function initialises the GIC Redistributor interface of the calling CPU 224 * (identified by the 'proc_num' parameter) based upon the data provided by the 225 * platform while initialising the driver. 226 ******************************************************************************/ 227 void gicv3_rdistif_init(unsigned int proc_num) 228 { 229 uintptr_t gicr_base; 230 unsigned int bitmap; 231 uint32_t ctlr; 232 233 assert(gicv3_driver_data != NULL); 234 assert(proc_num < gicv3_driver_data->rdistif_num); 235 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 236 assert(gicv3_driver_data->gicd_base != 0U); 237 238 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base); 239 assert((ctlr & CTLR_ARE_S_BIT) != 0U); 240 241 assert(IS_IN_EL3()); 242 243 /* Power on redistributor */ 244 gicv3_rdistif_on(proc_num); 245 246 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 247 assert(gicr_base != 0U); 248 249 /* Set the default attribute of all SGIs and (E)PPIs */ 250 gicv3_ppi_sgi_config_defaults(gicr_base); 251 252 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, 253 gicv3_driver_data->interrupt_props, 254 gicv3_driver_data->interrupt_props_num); 255 256 /* Enable interrupt groups as required, if not already */ 257 if ((ctlr & bitmap) != bitmap) { 258 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 259 } 260 } 261 262 /******************************************************************************* 263 * Functions to perform power operations on GIC Redistributor 264 ******************************************************************************/ 265 void gicv3_rdistif_off(unsigned int proc_num) 266 { 267 } 268 269 void gicv3_rdistif_on(unsigned int proc_num) 270 { 271 } 272 273 /******************************************************************************* 274 * This function enables the GIC CPU interface of the calling CPU using only 275 * system register accesses. 276 ******************************************************************************/ 277 void gicv3_cpuif_enable(unsigned int proc_num) 278 { 279 uintptr_t gicr_base; 280 u_register_t scr_el3; 281 unsigned int icc_sre_el3; 282 283 assert(gicv3_driver_data != NULL); 284 assert(proc_num < gicv3_driver_data->rdistif_num); 285 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 286 assert(IS_IN_EL3()); 287 288 /* Mark the connected core as awake */ 289 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 290 gicv3_rdistif_mark_core_awake(gicr_base); 291 292 /* Disable the legacy interrupt bypass */ 293 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 294 295 /* 296 * Enable system register access for EL3 and allow lower exception 297 * levels to configure the same for themselves. If the legacy mode is 298 * not supported, the SRE bit is RAO/WI 299 */ 300 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 301 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 302 303 scr_el3 = read_scr_el3(); 304 305 /* 306 * Switch to NS state to write Non secure ICC_SRE_EL1 and 307 * ICC_SRE_EL2 registers. 308 */ 309 write_scr_el3(scr_el3 | SCR_NS_BIT); 310 isb(); 311 312 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 313 write_icc_sre_el1(ICC_SRE_SRE_BIT); 314 isb(); 315 316 /* Switch to secure state. */ 317 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 318 isb(); 319 320 /* Write the secure ICC_SRE_EL1 register */ 321 write_icc_sre_el1(ICC_SRE_SRE_BIT); 322 isb(); 323 324 /* Program the idle priority in the PMR */ 325 write_icc_pmr_el1(GIC_PRI_MASK); 326 327 /* Enable Group0 interrupts */ 328 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 329 330 /* Enable Group1 Secure interrupts */ 331 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 332 IGRPEN1_EL3_ENABLE_G1S_BIT); 333 /* and restore the original */ 334 write_scr_el3(scr_el3); 335 isb(); 336 /* Add DSB to ensure visibility of System register writes */ 337 dsb(); 338 } 339 340 /******************************************************************************* 341 * This function disables the GIC CPU interface of the calling CPU using 342 * only system register accesses. 343 ******************************************************************************/ 344 void gicv3_cpuif_disable(unsigned int proc_num) 345 { 346 uintptr_t gicr_base; 347 348 assert(gicv3_driver_data != NULL); 349 assert(proc_num < gicv3_driver_data->rdistif_num); 350 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 351 352 assert(IS_IN_EL3()); 353 354 /* Disable legacy interrupt bypass */ 355 write_icc_sre_el3(read_icc_sre_el3() | 356 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 357 358 /* Disable Group0 interrupts */ 359 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 360 ~IGRPEN1_EL1_ENABLE_G0_BIT); 361 362 /* Disable Group1 Secure and Non-Secure interrupts */ 363 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 364 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 365 IGRPEN1_EL3_ENABLE_G1S_BIT)); 366 367 /* Synchronise accesses to group enable registers */ 368 isb(); 369 /* Add DSB to ensure visibility of System register writes */ 370 dsb(); 371 372 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 373 assert(gicr_base != 0UL); 374 375 /* 376 * dsb() already issued previously after clearing the CPU group 377 * enabled, apply below workaround to toggle the "DPG*" 378 * bits of GICR_CTLR register for unblocking event. 379 */ 380 gicv3_apply_errata_wa_2384374(gicr_base); 381 382 /* Mark the connected core as asleep */ 383 gicv3_rdistif_mark_core_asleep(gicr_base); 384 } 385 386 /******************************************************************************* 387 * This function returns the id of the highest priority pending interrupt at 388 * the GIC cpu interface. 389 ******************************************************************************/ 390 unsigned int gicv3_get_pending_interrupt_id(void) 391 { 392 unsigned int id; 393 394 assert(IS_IN_EL3()); 395 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 396 397 /* 398 * If the ID is special identifier corresponding to G1S or G1NS 399 * interrupt, then read the highest pending group 1 interrupt. 400 */ 401 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) { 402 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 403 } 404 405 return id; 406 } 407 408 /******************************************************************************* 409 * This function returns the type of the highest priority pending interrupt at 410 * the GIC cpu interface. The return values can be one of the following : 411 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 412 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 413 * 0 - 1019 : The interrupt type is secure Group 0. 414 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 415 * sufficient priority to be signaled 416 ******************************************************************************/ 417 unsigned int gicv3_get_pending_interrupt_type(void) 418 { 419 assert(IS_IN_EL3()); 420 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 421 } 422 423 /******************************************************************************* 424 * This function returns the group that has been configured under by the 425 * interrupt controller for the given interrupt id i.e. either group0 or group1 426 * Secure / Non Secure. The return value can be one of the following : 427 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 428 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 429 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 430 * interrupt. 431 ******************************************************************************/ 432 unsigned int gicv3_get_interrupt_group(unsigned int id, unsigned int proc_num) 433 { 434 unsigned int igroup, grpmodr; 435 uintptr_t gicr_base; 436 uintptr_t gicd_base; 437 438 assert(IS_IN_EL3()); 439 assert(gicv3_driver_data != NULL); 440 441 /* Ensure the parameters are valid */ 442 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID)); 443 assert(proc_num < gicv3_driver_data->rdistif_num); 444 445 /* All LPI interrupts are Group 1 non secure */ 446 if (id >= MIN_LPI_ID) { 447 return INTR_GROUP1NS; 448 } 449 450 /* Check interrupt ID */ 451 if (is_sgi_ppi(id)) { 452 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 453 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 454 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 455 igroup = gicr_get_igroupr(gicr_base, id); 456 grpmodr = gicr_get_igrpmodr(gicr_base, id); 457 } else { 458 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 459 assert(gicv3_driver_data->gicd_base != 0U); 460 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 461 igroup = gicd_get_igroupr(gicd_base, id); 462 grpmodr = gicd_get_igrpmodr(gicd_base, id); 463 } 464 465 /* 466 * If the IGROUP bit is set, then it is a Group 1 Non secure 467 * interrupt 468 */ 469 if (igroup != 0U) { 470 return INTR_GROUP1NS; 471 } 472 473 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 474 if (grpmodr != 0U) { 475 return INTR_GROUP1S; 476 } 477 478 /* Else it is a Group 0 Secure interrupt */ 479 return INTR_GROUP0; 480 } 481 482 /***************************************************************************** 483 * Function to save and disable the GIC ITS register context. The power 484 * management of GIC ITS is implementation-defined and this function doesn't 485 * save any memory structures required to support ITS. As the sequence to save 486 * this state is implementation defined, it should be executed in platform 487 * specific code. Calling this function alone and then powering down the GIC and 488 * ITS without implementing the aforementioned platform specific code will 489 * corrupt the ITS state. 490 * 491 * This function must be invoked after the GIC CPU interface is disabled. 492 *****************************************************************************/ 493 void gicv3_its_save_disable(uintptr_t gits_base, 494 gicv3_its_ctx_t * const its_ctx) 495 { 496 unsigned int i; 497 498 assert(gicv3_driver_data != NULL); 499 assert(IS_IN_EL3()); 500 assert(its_ctx != NULL); 501 assert(gits_base != 0U); 502 503 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 504 505 /* Disable the ITS */ 506 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 507 508 /* Wait for quiescent state */ 509 gits_wait_for_quiescent_bit(gits_base); 510 511 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 512 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 513 514 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 515 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 516 } 517 } 518 519 /***************************************************************************** 520 * Function to restore the GIC ITS register context. The power 521 * management of GIC ITS is implementation defined and this function doesn't 522 * restore any memory structures required to support ITS. The assumption is 523 * that these structures are in memory and are retained during system suspend. 524 * 525 * This must be invoked before the GIC CPU interface is enabled. 526 *****************************************************************************/ 527 void gicv3_its_restore(uintptr_t gits_base, 528 const gicv3_its_ctx_t * const its_ctx) 529 { 530 unsigned int i; 531 532 assert(gicv3_driver_data != NULL); 533 assert(IS_IN_EL3()); 534 assert(its_ctx != NULL); 535 assert(gits_base != 0U); 536 537 /* Assert that the GITS is disabled and quiescent */ 538 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 539 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U); 540 541 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 542 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 543 544 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 545 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 546 } 547 548 /* Restore the ITS CTLR but leave the ITS disabled */ 549 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 550 } 551 552 /***************************************************************************** 553 * Function to save the GIC Redistributor register context. This function 554 * must be invoked after CPU interface disable and prior to Distributor save. 555 *****************************************************************************/ 556 void gicv3_rdistif_save(unsigned int proc_num, 557 gicv3_redist_ctx_t * const rdist_ctx) 558 { 559 uintptr_t gicr_base; 560 unsigned int i, ppi_regs_num, regs_num; 561 562 assert(gicv3_driver_data != NULL); 563 assert(proc_num < gicv3_driver_data->rdistif_num); 564 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 565 assert(IS_IN_EL3()); 566 assert(rdist_ctx != NULL); 567 568 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 569 570 #if GIC_EXT_INTID 571 /* Calculate number of PPI registers */ 572 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 573 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 574 /* All other values except PPInum [0-2] are reserved */ 575 if (ppi_regs_num > 3U) { 576 ppi_regs_num = 1U; 577 } 578 #else 579 ppi_regs_num = 1U; 580 #endif 581 /* 582 * Wait for any write to GICR_CTLR to complete before trying to save any 583 * state. 584 */ 585 gicr_wait_for_pending_write(gicr_base); 586 587 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 588 589 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 590 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 591 592 /* 32 interrupt IDs per register */ 593 for (i = 0U; i < ppi_regs_num; ++i) { 594 SAVE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 595 SAVE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 596 SAVE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 597 SAVE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 598 SAVE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 599 } 600 601 /* 16 interrupt IDs per GICR_ICFGR register */ 602 regs_num = ppi_regs_num << 1; 603 for (i = 0U; i < regs_num; ++i) { 604 SAVE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 605 } 606 607 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 608 609 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 610 regs_num = ppi_regs_num << 3; 611 for (i = 0U; i < regs_num; ++i) { 612 rdist_ctx->gicr_ipriorityr[i] = 613 gicr_ipriorityr_read(gicr_base, i); 614 } 615 616 /* 617 * Call the pre-save hook that implements the IMP DEF sequence that may 618 * be required on some GIC implementations. As this may need to access 619 * the Redistributor registers, we pass it proc_num. 620 */ 621 gicv3_distif_pre_save(proc_num); 622 } 623 624 /***************************************************************************** 625 * Function to restore the GIC Redistributor register context. We disable 626 * LPI and per-cpu interrupts before we start restore of the Redistributor. 627 * This function must be invoked after Distributor restore but prior to 628 * CPU interface enable. The pending and active interrupts are restored 629 * after the interrupts are fully configured and enabled. 630 *****************************************************************************/ 631 void gicv3_rdistif_init_restore(unsigned int proc_num, 632 const gicv3_redist_ctx_t * const rdist_ctx) 633 { 634 uintptr_t gicr_base; 635 unsigned int i, ppi_regs_num, regs_num; 636 637 assert(gicv3_driver_data != NULL); 638 assert(proc_num < gicv3_driver_data->rdistif_num); 639 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 640 assert(IS_IN_EL3()); 641 assert(rdist_ctx != NULL); 642 643 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 644 645 #if GIC_EXT_INTID 646 /* Calculate number of PPI registers */ 647 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 648 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 649 /* All other values except PPInum [0-2] are reserved */ 650 if (ppi_regs_num > 3U) { 651 ppi_regs_num = 1U; 652 } 653 #else 654 ppi_regs_num = 1U; 655 #endif 656 /* Power on redistributor */ 657 gicv3_rdistif_on(proc_num); 658 659 /* 660 * Call the post-restore hook that implements the IMP DEF sequence that 661 * may be required on some GIC implementations. As this may need to 662 * access the Redistributor registers, we pass it proc_num. 663 */ 664 gicv3_distif_post_restore(proc_num); 665 666 /* 667 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 668 * This is a more scalable approach as it avoids clearing the enable 669 * bits in the GICD_CTLR. 670 */ 671 for (i = 0U; i < ppi_regs_num; ++i) { 672 gicr_write_icenabler(gicr_base, i, ~0U); 673 } 674 675 /* Wait for pending writes to GICR_ICENABLER */ 676 gicr_wait_for_pending_write(gicr_base); 677 678 /* 679 * Disable the LPIs to avoid unpredictable behavior when writing to 680 * GICR_PROPBASER and GICR_PENDBASER. 681 */ 682 gicr_write_ctlr(gicr_base, 683 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 684 685 /* Restore registers' content */ 686 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 687 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 688 689 /* 32 interrupt IDs per register */ 690 for (i = 0U; i < ppi_regs_num; ++i) { 691 RESTORE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 692 RESTORE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 693 } 694 695 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 696 regs_num = ppi_regs_num << 3; 697 for (i = 0U; i < regs_num; ++i) { 698 gicr_ipriorityr_write(gicr_base, i, 699 rdist_ctx->gicr_ipriorityr[i]); 700 } 701 702 /* 16 interrupt IDs per GICR_ICFGR register */ 703 regs_num = ppi_regs_num << 1; 704 for (i = 0U; i < regs_num; ++i) { 705 RESTORE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 706 } 707 708 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 709 710 /* Restore after group and priorities are set. 711 * 32 interrupt IDs per register 712 */ 713 for (i = 0U; i < ppi_regs_num; ++i) { 714 RESTORE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 715 RESTORE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 716 } 717 718 /* 719 * Wait for all writes to the Distributor to complete before enabling 720 * the SGI and (E)PPIs. 721 */ 722 gicr_wait_for_upstream_pending_write(gicr_base); 723 724 /* 32 interrupt IDs per GICR_ISENABLER register */ 725 for (i = 0U; i < ppi_regs_num; ++i) { 726 RESTORE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 727 } 728 729 /* 730 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 731 * the first write to GICR_CTLR was still in flight (this write only 732 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 733 * bit). 734 */ 735 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 736 gicr_wait_for_pending_write(gicr_base); 737 } 738 739 /***************************************************************************** 740 * Function to save the GIC Distributor register context. This function 741 * must be invoked after CPU interface disable and Redistributor save. 742 *****************************************************************************/ 743 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 744 { 745 assert(gicv3_driver_data != NULL); 746 assert(gicv3_driver_data->gicd_base != 0U); 747 assert(IS_IN_EL3()); 748 assert(dist_ctx != NULL); 749 750 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 751 unsigned int num_ints = gicv3_get_spi_limit(gicd_base); 752 #if GIC_EXT_INTID 753 unsigned int num_eints = gicv3_get_espi_limit(gicd_base); 754 #endif 755 756 /* Wait for pending write to complete */ 757 gicd_wait_for_pending_write(gicd_base); 758 759 /* Save the GICD_CTLR */ 760 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 761 762 /* Save GICD_IGROUPR for INTIDs 32 - 1019 */ 763 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 764 765 /* Save GICD_IGROUPRE for INTIDs 4096 - 5119 */ 766 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 767 768 /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */ 769 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 770 771 /* Save GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 772 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 773 774 /* Save GICD_ISPENDR for INTIDs 32 - 1019 */ 775 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 776 777 /* Save GICD_ISPENDRE for INTIDs 4096 - 5119 */ 778 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 779 780 /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */ 781 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 782 783 /* Save GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 784 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 785 786 /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */ 787 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 788 789 /* Save GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 790 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 791 792 /* Save GICD_ICFGR for INTIDs 32 - 1019 */ 793 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 794 795 /* Save GICD_ICFGRE for INTIDs 4096 - 5119 */ 796 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 797 798 /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */ 799 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 800 801 /* Save GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 802 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 803 804 /* Save GICD_NSACR for INTIDs 32 - 1019 */ 805 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 806 807 /* Save GICD_NSACRE for INTIDs 4096 - 5119 */ 808 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 809 810 /* Save GICD_IROUTER for INTIDs 32 - 1019 */ 811 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 812 813 /* Save GICD_IROUTERE for INTIDs 4096 - 5119 */ 814 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 815 816 /* 817 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 818 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 819 * driver. 820 */ 821 } 822 823 /***************************************************************************** 824 * Function to restore the GIC Distributor register context. We disable G0, G1S 825 * and G1NS interrupt groups before we start restore of the Distributor. This 826 * function must be invoked prior to Redistributor restore and CPU interface 827 * enable. The pending and active interrupts are restored after the interrupts 828 * are fully configured and enabled. 829 *****************************************************************************/ 830 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 831 { 832 assert(gicv3_driver_data != NULL); 833 assert(gicv3_driver_data->gicd_base != 0U); 834 assert(IS_IN_EL3()); 835 assert(dist_ctx != NULL); 836 837 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 838 839 /* 840 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 841 * the ARE_S bit. The Distributor might generate a system error 842 * otherwise. 843 */ 844 gicd_clr_ctlr(gicd_base, 845 CTLR_ENABLE_G0_BIT | 846 CTLR_ENABLE_G1S_BIT | 847 CTLR_ENABLE_G1NS_BIT, 848 RWP_TRUE); 849 850 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 851 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 852 853 unsigned int num_ints = gicv3_get_spi_limit(gicd_base); 854 #if GIC_EXT_INTID 855 unsigned int num_eints = gicv3_get_espi_limit(gicd_base); 856 #endif 857 /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */ 858 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 859 860 /* Restore GICD_IGROUPRE for INTIDs 4096 - 5119 */ 861 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 862 863 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */ 864 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 865 866 /* Restore GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 867 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 868 869 /* Restore GICD_ICFGR for INTIDs 32 - 1019 */ 870 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 871 872 /* Restore GICD_ICFGRE for INTIDs 4096 - 5119 */ 873 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 874 875 /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */ 876 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 877 878 /* Restore GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 879 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 880 881 /* Restore GICD_NSACR for INTIDs 32 - 1019 */ 882 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 883 884 /* Restore GICD_NSACRE for INTIDs 4096 - 5119 */ 885 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 886 887 /* Restore GICD_IROUTER for INTIDs 32 - 1019 */ 888 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 889 890 /* Restore GICD_IROUTERE for INTIDs 4096 - 5119 */ 891 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 892 893 /* 894 * Restore ISENABLER(E), ISPENDR(E) and ISACTIVER(E) after 895 * the interrupts are configured. 896 */ 897 898 /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */ 899 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 900 901 /* Restore GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 902 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 903 904 /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */ 905 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 906 907 /* Restore GICD_ISPENDRE for INTIDs 4096 - 5119 */ 908 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 909 910 /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */ 911 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 912 913 /* Restore GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 914 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 915 916 /* Restore the GICD_CTLR */ 917 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 918 gicd_wait_for_pending_write(gicd_base); 919 } 920 921 /******************************************************************************* 922 * This function gets the priority of the interrupt the processor is currently 923 * servicing. 924 ******************************************************************************/ 925 unsigned int gicv3_get_running_priority(void) 926 { 927 return (unsigned int)read_icc_rpr_el1(); 928 } 929 930 /******************************************************************************* 931 * This function checks if the interrupt identified by id is active (whether the 932 * state is either active, or active and pending). The proc_num is used if the 933 * interrupt is SGI or (E)PPI and programs the corresponding Redistributor 934 * interface. 935 ******************************************************************************/ 936 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) 937 { 938 uintptr_t gicd_base; 939 940 assert(gicv3_driver_data != NULL); 941 assert(gicv3_driver_data->gicd_base != 0U); 942 assert(proc_num < gicv3_driver_data->rdistif_num); 943 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 944 945 /* Check interrupt ID */ 946 if (is_sgi_ppi(id)) { 947 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 948 return gicr_get_isactiver( 949 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 950 } 951 952 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 953 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 954 return gicd_get_isactiver(gicd_base, id); 955 } 956 957 /******************************************************************************* 958 * This function enables the interrupt identified by id. The proc_num 959 * is used if the interrupt is SGI or PPI, and programs the corresponding 960 * Redistributor interface. 961 ******************************************************************************/ 962 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) 963 { 964 uintptr_t gicd_base; 965 966 assert(gicv3_driver_data != NULL); 967 assert(gicv3_driver_data->gicd_base != 0U); 968 assert(proc_num < gicv3_driver_data->rdistif_num); 969 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 970 971 /* 972 * Ensure that any shared variable updates depending on out of band 973 * interrupt trigger are observed before enabling interrupt. 974 */ 975 dsbishst(); 976 977 /* Check interrupt ID */ 978 if (is_sgi_ppi(id)) { 979 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 980 gicr_set_isenabler( 981 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 982 } else { 983 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 984 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 985 gicd_set_isenabler(gicd_base, id); 986 } 987 } 988 989 /******************************************************************************* 990 * This function disables the interrupt identified by id. The proc_num 991 * is used if the interrupt is SGI or PPI, and programs the corresponding 992 * Redistributor interface. 993 ******************************************************************************/ 994 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) 995 { 996 uintptr_t gicd_base; 997 998 assert(gicv3_driver_data != NULL); 999 assert(gicv3_driver_data->gicd_base != 0U); 1000 assert(proc_num < gicv3_driver_data->rdistif_num); 1001 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1002 1003 /* 1004 * Disable interrupt, and ensure that any shared variable updates 1005 * depending on out of band interrupt trigger are observed afterwards. 1006 */ 1007 1008 /* Check interrupt ID */ 1009 if (is_sgi_ppi(id)) { 1010 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1011 gicr_set_icenabler( 1012 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1013 1014 /* Write to clear enable requires waiting for pending writes */ 1015 gicr_wait_for_pending_write( 1016 gicv3_driver_data->rdistif_base_addrs[proc_num]); 1017 } else { 1018 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1019 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1020 gicd_set_icenabler(gicd_base, id); 1021 1022 /* Write to clear enable requires waiting for pending writes */ 1023 gicd_wait_for_pending_write(gicd_base); 1024 } 1025 1026 dsbishst(); 1027 } 1028 1029 /******************************************************************************* 1030 * This function sets the interrupt priority as supplied for the given interrupt 1031 * id. 1032 ******************************************************************************/ 1033 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 1034 unsigned int priority) 1035 { 1036 uintptr_t gicr_base; 1037 uintptr_t gicd_base; 1038 1039 assert(gicv3_driver_data != NULL); 1040 assert(gicv3_driver_data->gicd_base != 0U); 1041 assert(proc_num < gicv3_driver_data->rdistif_num); 1042 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1043 1044 /* Check interrupt ID */ 1045 if (is_sgi_ppi(id)) { 1046 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1047 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1048 gicr_set_ipriorityr(gicr_base, id, priority); 1049 } else { 1050 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1051 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1052 gicd_set_ipriorityr(gicd_base, id, priority); 1053 } 1054 } 1055 1056 /******************************************************************************* 1057 * This function assigns group for the interrupt identified by id. The proc_num 1058 * is used if the interrupt is SGI or (E)PPI, and programs the corresponding 1059 * Redistributor interface. The group can be any of GICV3_INTR_GROUP* 1060 ******************************************************************************/ 1061 void gicv3_set_interrupt_group(unsigned int id, unsigned int proc_num, 1062 unsigned int group) 1063 { 1064 bool igroup = false, grpmod = false; 1065 uintptr_t gicr_base; 1066 uintptr_t gicd_base; 1067 1068 assert(gicv3_driver_data != NULL); 1069 assert(gicv3_driver_data->gicd_base != 0U); 1070 assert(proc_num < gicv3_driver_data->rdistif_num); 1071 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1072 1073 switch (group) { 1074 case INTR_GROUP1S: 1075 igroup = false; 1076 grpmod = true; 1077 break; 1078 case INTR_GROUP0: 1079 igroup = false; 1080 grpmod = false; 1081 break; 1082 case INTR_GROUP1NS: 1083 igroup = true; 1084 grpmod = false; 1085 break; 1086 default: 1087 assert(false); 1088 break; 1089 } 1090 1091 /* Check interrupt ID */ 1092 if (is_sgi_ppi(id)) { 1093 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1094 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1095 1096 igroup ? gicr_set_igroupr(gicr_base, id) : 1097 gicr_clr_igroupr(gicr_base, id); 1098 grpmod ? gicr_set_igrpmodr(gicr_base, id) : 1099 gicr_clr_igrpmodr(gicr_base, id); 1100 } else { 1101 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1102 1103 /* Serialize read-modify-write to Distributor registers */ 1104 spin_lock(&gic_lock); 1105 1106 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1107 1108 igroup ? gicd_set_igroupr(gicd_base, id) : 1109 gicd_clr_igroupr(gicd_base, id); 1110 grpmod ? gicd_set_igrpmodr(gicd_base, id) : 1111 gicd_clr_igrpmodr(gicd_base, id); 1112 1113 spin_unlock(&gic_lock); 1114 } 1115 } 1116 1117 /******************************************************************************* 1118 * This function raises the specified SGI of the specified group. 1119 * 1120 * The target parameter must be a valid MPIDR in the system. 1121 ******************************************************************************/ 1122 void gicv3_raise_sgi(unsigned int sgi_num, gicv3_irq_group_t group, 1123 u_register_t target) 1124 { 1125 unsigned int tgt, aff3, aff2, aff1, aff0; 1126 uint64_t sgi_val; 1127 1128 /* Verify interrupt number is in the SGI range */ 1129 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID)); 1130 1131 /* Extract affinity fields from target */ 1132 aff0 = MPIDR_AFFLVL0_VAL(target); 1133 aff1 = MPIDR_AFFLVL1_VAL(target); 1134 aff2 = MPIDR_AFFLVL2_VAL(target); 1135 aff3 = MPIDR_AFFLVL3_VAL(target); 1136 1137 /* 1138 * Make target list from affinity 0, and ensure GICv3 SGI can target 1139 * this PE. 1140 */ 1141 assert(aff0 < GICV3_MAX_SGI_TARGETS); 1142 tgt = BIT_32(aff0); 1143 1144 /* Raise SGI to PE specified by its affinity */ 1145 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF, 1146 tgt); 1147 1148 /* 1149 * Ensure that any shared variable updates depending on out of band 1150 * interrupt trigger are observed before raising SGI. 1151 */ 1152 dsbishst(); 1153 1154 switch (group) { 1155 case GICV3_G0: 1156 write_icc_sgi0r_el1(sgi_val); 1157 break; 1158 case GICV3_G1NS: 1159 write_icc_asgi1r(sgi_val); 1160 break; 1161 case GICV3_G1S: 1162 write_icc_sgi1r(sgi_val); 1163 break; 1164 default: 1165 assert(false); 1166 break; 1167 } 1168 1169 isb(); 1170 } 1171 1172 /******************************************************************************* 1173 * This function sets the interrupt routing for the given (E)SPI interrupt id. 1174 * The interrupt routing is specified in routing mode and mpidr. 1175 * 1176 * The routing mode can be either of: 1177 * - GICV3_IRM_ANY 1178 * - GICV3_IRM_PE 1179 * 1180 * The mpidr is the affinity of the PE to which the interrupt will be routed, 1181 * and is ignored for routing mode GICV3_IRM_ANY. 1182 ******************************************************************************/ 1183 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr) 1184 { 1185 unsigned long long aff; 1186 uint64_t router; 1187 uintptr_t gicd_base; 1188 1189 assert(gicv3_driver_data != NULL); 1190 assert(gicv3_driver_data->gicd_base != 0U); 1191 1192 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE)); 1193 1194 assert(IS_SPI(id)); 1195 1196 aff = gicd_irouter_val_from_mpidr(mpidr, irm); 1197 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1198 gicd_write_irouter(gicd_base, id, aff); 1199 1200 /* 1201 * In implementations that do not require 1 of N distribution of SPIs, 1202 * IRM might be RAZ/WI. Read back and verify IRM bit. 1203 */ 1204 if (irm == GICV3_IRM_ANY) { 1205 router = gicd_read_irouter(gicd_base, id); 1206 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) { 1207 ERROR("GICv3 implementation doesn't support routing ANY\n"); 1208 panic(); 1209 } 1210 } 1211 } 1212 1213 /******************************************************************************* 1214 * This function clears the pending status of an interrupt identified by id. 1215 * The proc_num is used if the interrupt is SGI or (E)PPI, and programs the 1216 * corresponding Redistributor interface. 1217 ******************************************************************************/ 1218 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num) 1219 { 1220 uintptr_t gicd_base; 1221 1222 assert(gicv3_driver_data != NULL); 1223 assert(gicv3_driver_data->gicd_base != 0U); 1224 assert(proc_num < gicv3_driver_data->rdistif_num); 1225 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1226 1227 /* 1228 * Clear pending interrupt, and ensure that any shared variable updates 1229 * depending on out of band interrupt trigger are observed afterwards. 1230 */ 1231 1232 /* Check interrupt ID */ 1233 if (is_sgi_ppi(id)) { 1234 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1235 gicr_set_icpendr( 1236 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1237 } else { 1238 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1239 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1240 gicd_set_icpendr(gicd_base, id); 1241 } 1242 1243 dsbishst(); 1244 } 1245 1246 /******************************************************************************* 1247 * This function sets the pending status of an interrupt identified by id. 1248 * The proc_num is used if the interrupt is SGI or PPI and programs the 1249 * corresponding Redistributor interface. 1250 ******************************************************************************/ 1251 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num) 1252 { 1253 uintptr_t gicd_base; 1254 1255 assert(gicv3_driver_data != NULL); 1256 assert(gicv3_driver_data->gicd_base != 0U); 1257 assert(proc_num < gicv3_driver_data->rdistif_num); 1258 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1259 1260 /* 1261 * Ensure that any shared variable updates depending on out of band 1262 * interrupt trigger are observed before setting interrupt pending. 1263 */ 1264 dsbishst(); 1265 1266 /* Check interrupt ID */ 1267 if (is_sgi_ppi(id)) { 1268 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1269 gicr_set_ispendr( 1270 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1271 } else { 1272 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1273 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1274 gicd_set_ispendr(gicd_base, id); 1275 } 1276 } 1277 1278 /******************************************************************************* 1279 * This function sets the PMR register with the supplied value. Returns the 1280 * original PMR. 1281 ******************************************************************************/ 1282 unsigned int gicv3_set_pmr(unsigned int mask) 1283 { 1284 unsigned int old_mask; 1285 1286 old_mask = (unsigned int)read_icc_pmr_el1(); 1287 1288 /* 1289 * Order memory updates w.r.t. PMR write, and ensure they're visible 1290 * before potential out of band interrupt trigger because of PMR update. 1291 * PMR system register writes are self-synchronizing, so no ISB required 1292 * thereafter. 1293 */ 1294 dsbishst(); 1295 write_icc_pmr_el1(mask); 1296 1297 return old_mask; 1298 } 1299 1300 /******************************************************************************* 1301 * This function delegates the responsibility of discovering the corresponding 1302 * Redistributor frames to each CPU itself. It is a modified version of 1303 * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform 1304 * unlike the previous way in which only the Primary CPU did the discovery of 1305 * all the Redistributor frames for every CPU. It also handles the scenario in 1306 * which the frames of various CPUs are not contiguous in physical memory. 1307 ******************************************************************************/ 1308 int gicv3_rdistif_probe(const uintptr_t gicr_frame) 1309 { 1310 u_register_t mpidr, mpidr_self; 1311 unsigned int proc_num; 1312 uint64_t typer_val; 1313 uintptr_t rdistif_base; 1314 bool gicr_frame_found = false; 1315 1316 assert(gicv3_driver_data->gicr_base == 0U); 1317 1318 if (plat_can_cmo()) { 1319 /* Ensure this function is called with Data Cache enabled */ 1320 #ifndef __aarch64__ 1321 assert((read_sctlr() & SCTLR_C_BIT) != 0U); 1322 #else 1323 assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U); 1324 #endif /* !__aarch64__ */ 1325 } 1326 1327 mpidr_self = read_mpidr_el1() & MPIDR_AFFINITY_MASK; 1328 rdistif_base = gicr_frame; 1329 do { 1330 typer_val = gicr_read_typer(rdistif_base); 1331 mpidr = mpidr_from_gicr_typer(typer_val); 1332 if (gicv3_driver_data->mpidr_to_core_pos != NULL) { 1333 proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr); 1334 } else { 1335 proc_num = (unsigned int)(typer_val >> 1336 TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK; 1337 } 1338 if (mpidr == mpidr_self) { 1339 /* The base address doesn't need to be initialized on 1340 * every warm boot. 1341 */ 1342 if (gicv3_driver_data->rdistif_base_addrs[proc_num] 1343 != 0U) { 1344 return 0; 1345 } 1346 gicv3_driver_data->rdistif_base_addrs[proc_num] = 1347 rdistif_base; 1348 gicr_frame_found = true; 1349 break; 1350 } 1351 rdistif_base += gicv3_redist_size(typer_val); 1352 } while ((typer_val & TYPER_LAST_BIT) == 0U); 1353 1354 if (!gicr_frame_found) { 1355 return -1; 1356 } 1357 1358 /* 1359 * Flush the driver data to ensure coherency. This is 1360 * not required if platform has HW_ASSISTED_COHERENCY 1361 * enabled. 1362 */ 1363 #if !HW_ASSISTED_COHERENCY 1364 /* 1365 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 1366 */ 1367 flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]), 1368 sizeof(*(gicv3_driver_data->rdistif_base_addrs))); 1369 #endif 1370 return 0; /* Found matching GICR frame */ 1371 } 1372 1373 /****************************************************************************** 1374 * This function checks the interrupt ID and returns true for SGIs and (E)PPIs 1375 * and false for (E)SPIs IDs. 1376 *****************************************************************************/ 1377 static bool is_sgi_ppi(unsigned int id) 1378 { 1379 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 1380 if (IS_SGI_PPI(id)) { 1381 return true; 1382 } 1383 1384 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 1385 if (IS_SPI(id)) { 1386 return false; 1387 } 1388 1389 assert(false); 1390 panic(); 1391 } 1392