1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <debug.h> 35 #include <gic_common.h> 36 #include <gicv3.h> 37 #include "../common/gic_common_private.h" 38 #include "gicv3_private.h" 39 40 static const gicv3_driver_data_t *driver_data; 41 static unsigned int gicv2_compat; 42 43 /* 44 * Redistributor power operations are weakly bound so that they can be 45 * overridden 46 */ 47 #pragma weak gicv3_rdistif_off 48 #pragma weak gicv3_rdistif_on 49 50 /******************************************************************************* 51 * This function initialises the ARM GICv3 driver in EL3 with provided platform 52 * inputs. 53 ******************************************************************************/ 54 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 55 { 56 unsigned int gic_version; 57 58 assert(plat_driver_data); 59 assert(plat_driver_data->gicd_base); 60 assert(plat_driver_data->gicr_base); 61 assert(plat_driver_data->rdistif_num); 62 assert(plat_driver_data->rdistif_base_addrs); 63 64 assert(IS_IN_EL3()); 65 66 /* 67 * The platform should provide a list of at least one type of 68 * interrupts 69 */ 70 assert(plat_driver_data->g0_interrupt_array || 71 plat_driver_data->g1s_interrupt_array); 72 73 /* 74 * If there are no interrupts of a particular type, then the number of 75 * interrupts of that type should be 0 and vice-versa. 76 */ 77 assert(plat_driver_data->g0_interrupt_array ? 78 plat_driver_data->g0_interrupt_num : 79 plat_driver_data->g0_interrupt_num == 0); 80 assert(plat_driver_data->g1s_interrupt_array ? 81 plat_driver_data->g1s_interrupt_num : 82 plat_driver_data->g1s_interrupt_num == 0); 83 84 /* Check for system register support */ 85 #ifdef AARCH32 86 assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)); 87 #else 88 assert(read_id_aa64pfr0_el1() & 89 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)); 90 #endif /* AARCH32 */ 91 92 /* The GIC version should be 3.0 */ 93 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 94 gic_version >>= PIDR2_ARCH_REV_SHIFT; 95 gic_version &= PIDR2_ARCH_REV_MASK; 96 assert(gic_version == ARCH_REV_GICV3); 97 98 /* 99 * Find out whether the GIC supports the GICv2 compatibility mode. The 100 * ARE_S bit resets to 0 if supported 101 */ 102 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 103 gicv2_compat >>= CTLR_ARE_S_SHIFT; 104 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); 105 106 /* 107 * Find the base address of each implemented Redistributor interface. 108 * The number of interfaces should be equal to the number of CPUs in the 109 * system. The memory for saving these addresses has to be allocated by 110 * the platform port 111 */ 112 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 113 plat_driver_data->rdistif_num, 114 plat_driver_data->gicr_base, 115 plat_driver_data->mpidr_to_core_pos); 116 117 driver_data = plat_driver_data; 118 119 INFO("GICv3 %s legacy support detected." 120 " ARM GICV3 driver initialized in EL3\n", 121 gicv2_compat ? "with" : "without"); 122 } 123 124 /******************************************************************************* 125 * This function initialises the GIC distributor interface based upon the data 126 * provided by the platform while initialising the driver. 127 ******************************************************************************/ 128 void gicv3_distif_init(void) 129 { 130 unsigned int bitmap = 0; 131 132 assert(driver_data); 133 assert(driver_data->gicd_base); 134 assert(driver_data->g1s_interrupt_array || 135 driver_data->g0_interrupt_array); 136 137 assert(IS_IN_EL3()); 138 139 /* 140 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 141 * the ARE_S bit. The Distributor might generate a system error 142 * otherwise. 143 */ 144 gicd_clr_ctlr(driver_data->gicd_base, 145 CTLR_ENABLE_G0_BIT | 146 CTLR_ENABLE_G1S_BIT | 147 CTLR_ENABLE_G1NS_BIT, 148 RWP_TRUE); 149 150 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 151 gicd_set_ctlr(driver_data->gicd_base, 152 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 153 154 /* Set the default attribute of all SPIs */ 155 gicv3_spis_configure_defaults(driver_data->gicd_base); 156 157 /* Configure the G1S SPIs */ 158 if (driver_data->g1s_interrupt_array) { 159 gicv3_secure_spis_configure(driver_data->gicd_base, 160 driver_data->g1s_interrupt_num, 161 driver_data->g1s_interrupt_array, 162 INTR_GROUP1S); 163 bitmap |= CTLR_ENABLE_G1S_BIT; 164 } 165 166 /* Configure the G0 SPIs */ 167 if (driver_data->g0_interrupt_array) { 168 gicv3_secure_spis_configure(driver_data->gicd_base, 169 driver_data->g0_interrupt_num, 170 driver_data->g0_interrupt_array, 171 INTR_GROUP0); 172 bitmap |= CTLR_ENABLE_G0_BIT; 173 } 174 175 /* Enable the secure SPIs now that they have been configured */ 176 gicd_set_ctlr(driver_data->gicd_base, bitmap, RWP_TRUE); 177 } 178 179 /******************************************************************************* 180 * This function initialises the GIC Redistributor interface of the calling CPU 181 * (identified by the 'proc_num' parameter) based upon the data provided by the 182 * platform while initialising the driver. 183 ******************************************************************************/ 184 void gicv3_rdistif_init(unsigned int proc_num) 185 { 186 uintptr_t gicr_base; 187 188 assert(driver_data); 189 assert(proc_num < driver_data->rdistif_num); 190 assert(driver_data->rdistif_base_addrs); 191 assert(driver_data->gicd_base); 192 assert(gicd_read_ctlr(driver_data->gicd_base) & CTLR_ARE_S_BIT); 193 assert(driver_data->g1s_interrupt_array || 194 driver_data->g0_interrupt_array); 195 196 assert(IS_IN_EL3()); 197 198 /* Power on redistributor */ 199 gicv3_rdistif_on(proc_num); 200 201 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 202 203 /* Set the default attribute of all SGIs and PPIs */ 204 gicv3_ppi_sgi_configure_defaults(gicr_base); 205 206 /* Configure the G1S SGIs/PPIs */ 207 if (driver_data->g1s_interrupt_array) { 208 gicv3_secure_ppi_sgi_configure(gicr_base, 209 driver_data->g1s_interrupt_num, 210 driver_data->g1s_interrupt_array, 211 INTR_GROUP1S); 212 } 213 214 /* Configure the G0 SGIs/PPIs */ 215 if (driver_data->g0_interrupt_array) { 216 gicv3_secure_ppi_sgi_configure(gicr_base, 217 driver_data->g0_interrupt_num, 218 driver_data->g0_interrupt_array, 219 INTR_GROUP0); 220 } 221 } 222 223 /******************************************************************************* 224 * Functions to perform power operations on GIC Redistributor 225 ******************************************************************************/ 226 void gicv3_rdistif_off(unsigned int proc_num) 227 { 228 return; 229 } 230 231 void gicv3_rdistif_on(unsigned int proc_num) 232 { 233 return; 234 } 235 236 /******************************************************************************* 237 * This function enables the GIC CPU interface of the calling CPU using only 238 * system register accesses. 239 ******************************************************************************/ 240 void gicv3_cpuif_enable(unsigned int proc_num) 241 { 242 uintptr_t gicr_base; 243 unsigned int scr_el3; 244 unsigned int icc_sre_el3; 245 246 assert(driver_data); 247 assert(proc_num < driver_data->rdistif_num); 248 assert(driver_data->rdistif_base_addrs); 249 assert(IS_IN_EL3()); 250 251 /* Mark the connected core as awake */ 252 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 253 gicv3_rdistif_mark_core_awake(gicr_base); 254 255 /* Disable the legacy interrupt bypass */ 256 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 257 258 /* 259 * Enable system register access for EL3 and allow lower exception 260 * levels to configure the same for themselves. If the legacy mode is 261 * not supported, the SRE bit is RAO/WI 262 */ 263 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 264 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 265 266 scr_el3 = read_scr_el3(); 267 268 /* 269 * Switch to NS state to write Non secure ICC_SRE_EL1 and 270 * ICC_SRE_EL2 registers. 271 */ 272 write_scr_el3(scr_el3 | SCR_NS_BIT); 273 isb(); 274 275 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 276 write_icc_sre_el1(ICC_SRE_SRE_BIT); 277 isb(); 278 279 /* Switch to secure state. */ 280 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 281 isb(); 282 283 /* Program the idle priority in the PMR */ 284 write_icc_pmr_el1(GIC_PRI_MASK); 285 286 /* Enable Group0 interrupts */ 287 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 288 289 /* Enable Group1 Secure interrupts */ 290 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 291 IGRPEN1_EL3_ENABLE_G1S_BIT); 292 293 /* Write the secure ICC_SRE_EL1 register */ 294 write_icc_sre_el1(ICC_SRE_SRE_BIT); 295 isb(); 296 } 297 298 /******************************************************************************* 299 * This function disables the GIC CPU interface of the calling CPU using 300 * only system register accesses. 301 ******************************************************************************/ 302 void gicv3_cpuif_disable(unsigned int proc_num) 303 { 304 uintptr_t gicr_base; 305 306 assert(driver_data); 307 assert(proc_num < driver_data->rdistif_num); 308 assert(driver_data->rdistif_base_addrs); 309 310 assert(IS_IN_EL3()); 311 312 /* Disable legacy interrupt bypass */ 313 write_icc_sre_el3(read_icc_sre_el3() | 314 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 315 316 /* Disable Group0 interrupts */ 317 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 318 ~IGRPEN1_EL1_ENABLE_G0_BIT); 319 320 /* Disable Group1 Secure and Non-Secure interrupts */ 321 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 322 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 323 IGRPEN1_EL3_ENABLE_G1S_BIT)); 324 325 /* Synchronise accesses to group enable registers */ 326 isb(); 327 328 /* Mark the connected core as asleep */ 329 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 330 gicv3_rdistif_mark_core_asleep(gicr_base); 331 } 332 333 /******************************************************************************* 334 * This function returns the id of the highest priority pending interrupt at 335 * the GIC cpu interface. 336 ******************************************************************************/ 337 unsigned int gicv3_get_pending_interrupt_id(void) 338 { 339 unsigned int id; 340 341 assert(IS_IN_EL3()); 342 id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 343 344 /* 345 * If the ID is special identifier corresponding to G1S or G1NS 346 * interrupt, then read the highest pending group 1 interrupt. 347 */ 348 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) 349 return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 350 351 return id; 352 } 353 354 /******************************************************************************* 355 * This function returns the type of the highest priority pending interrupt at 356 * the GIC cpu interface. The return values can be one of the following : 357 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 358 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 359 * 0 - 1019 : The interrupt type is secure Group 0. 360 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 361 * sufficient priority to be signaled 362 ******************************************************************************/ 363 unsigned int gicv3_get_pending_interrupt_type(void) 364 { 365 assert(IS_IN_EL3()); 366 return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 367 } 368 369 /******************************************************************************* 370 * This function returns the type of the interrupt id depending upon the group 371 * this interrupt has been configured under by the interrupt controller i.e. 372 * group0 or group1 Secure / Non Secure. The return value can be one of the 373 * following : 374 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 375 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 376 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 377 * interrupt. 378 ******************************************************************************/ 379 unsigned int gicv3_get_interrupt_type(unsigned int id, 380 unsigned int proc_num) 381 { 382 unsigned int igroup, grpmodr; 383 uintptr_t gicr_base; 384 385 assert(IS_IN_EL3()); 386 assert(driver_data); 387 388 /* Ensure the parameters are valid */ 389 assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID); 390 assert(proc_num < driver_data->rdistif_num); 391 392 /* All LPI interrupts are Group 1 non secure */ 393 if (id >= MIN_LPI_ID) 394 return INTR_GROUP1NS; 395 396 if (id < MIN_SPI_ID) { 397 assert(driver_data->rdistif_base_addrs); 398 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 399 igroup = gicr_get_igroupr0(gicr_base, id); 400 grpmodr = gicr_get_igrpmodr0(gicr_base, id); 401 } else { 402 assert(driver_data->gicd_base); 403 igroup = gicd_get_igroupr(driver_data->gicd_base, id); 404 grpmodr = gicd_get_igrpmodr(driver_data->gicd_base, id); 405 } 406 407 /* 408 * If the IGROUP bit is set, then it is a Group 1 Non secure 409 * interrupt 410 */ 411 if (igroup) 412 return INTR_GROUP1NS; 413 414 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 415 if (grpmodr) 416 return INTR_GROUP1S; 417 418 /* Else it is a Group 0 Secure interrupt */ 419 return INTR_GROUP0; 420 } 421