1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gicv3.h> 12 #include <interrupt_props.h> 13 #include <spinlock.h> 14 #include "gicv3_private.h" 15 16 const gicv3_driver_data_t *gicv3_driver_data; 17 static unsigned int gicv2_compat; 18 19 /* 20 * Spinlock to guard registers needing read-modify-write. APIs protected by this 21 * spinlock are used either at boot time (when only a single CPU is active), or 22 * when the system is fully coherent. 23 */ 24 static spinlock_t gic_lock; 25 26 /* 27 * Redistributor power operations are weakly bound so that they can be 28 * overridden 29 */ 30 #pragma weak gicv3_rdistif_off 31 #pragma weak gicv3_rdistif_on 32 33 34 /* Helper macros to save and restore GICD registers to and from the context */ 35 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 36 do { \ 37 for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \ 38 int_id += (1 << REG##_SHIFT)) { \ 39 gicd_write_##reg(base, int_id, \ 40 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT]); \ 41 } \ 42 } while (0) 43 44 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 45 do { \ 46 for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \ 47 int_id += (1 << REG##_SHIFT)) { \ 48 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT] =\ 49 gicd_read_##reg(base, int_id); \ 50 } \ 51 } while (0) 52 53 54 /******************************************************************************* 55 * This function initialises the ARM GICv3 driver in EL3 with provided platform 56 * inputs. 57 ******************************************************************************/ 58 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 59 { 60 unsigned int gic_version; 61 62 assert(plat_driver_data); 63 assert(plat_driver_data->gicd_base); 64 assert(plat_driver_data->gicr_base); 65 assert(plat_driver_data->rdistif_num); 66 assert(plat_driver_data->rdistif_base_addrs); 67 68 assert(IS_IN_EL3()); 69 70 #if !ERROR_DEPRECATED 71 if (plat_driver_data->interrupt_props == NULL) { 72 /* Interrupt properties array size must be 0 */ 73 assert(plat_driver_data->interrupt_props_num == 0); 74 75 /* 76 * Suppress deprecated declaration warnings in compatibility 77 * function 78 */ 79 #pragma GCC diagnostic push 80 #pragma GCC diagnostic ignored "-Wdeprecated-declarations" 81 82 /* 83 * The platform should provide a list of at least one type of 84 * interrupt. 85 */ 86 assert(plat_driver_data->g0_interrupt_array || 87 plat_driver_data->g1s_interrupt_array); 88 89 /* 90 * If there are no interrupts of a particular type, then the 91 * number of interrupts of that type should be 0 and vice-versa. 92 */ 93 assert(plat_driver_data->g0_interrupt_array ? 94 plat_driver_data->g0_interrupt_num : 95 plat_driver_data->g0_interrupt_num == 0); 96 assert(plat_driver_data->g1s_interrupt_array ? 97 plat_driver_data->g1s_interrupt_num : 98 plat_driver_data->g1s_interrupt_num == 0); 99 #pragma GCC diagnostic pop 100 101 WARN("Using deprecated integer interrupt arrays in " 102 "gicv3_driver_data_t\n"); 103 WARN("Please migrate to using interrupt_prop_t arrays\n"); 104 } 105 #else 106 assert(plat_driver_data->interrupt_props_num > 0 ? 107 plat_driver_data->interrupt_props != NULL : 1); 108 #endif 109 110 /* Check for system register support */ 111 #ifdef AARCH32 112 assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)); 113 #else 114 assert(read_id_aa64pfr0_el1() & 115 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)); 116 #endif /* AARCH32 */ 117 118 /* The GIC version should be 3.0 */ 119 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 120 gic_version >>= PIDR2_ARCH_REV_SHIFT; 121 gic_version &= PIDR2_ARCH_REV_MASK; 122 assert(gic_version == ARCH_REV_GICV3); 123 124 /* 125 * Find out whether the GIC supports the GICv2 compatibility mode. The 126 * ARE_S bit resets to 0 if supported 127 */ 128 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 129 gicv2_compat >>= CTLR_ARE_S_SHIFT; 130 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); 131 132 /* 133 * Find the base address of each implemented Redistributor interface. 134 * The number of interfaces should be equal to the number of CPUs in the 135 * system. The memory for saving these addresses has to be allocated by 136 * the platform port 137 */ 138 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 139 plat_driver_data->rdistif_num, 140 plat_driver_data->gicr_base, 141 plat_driver_data->mpidr_to_core_pos); 142 143 gicv3_driver_data = plat_driver_data; 144 145 /* 146 * The GIC driver data is initialized by the primary CPU with caches 147 * enabled. When the secondary CPU boots up, it initializes the 148 * GICC/GICR interface with the caches disabled. Hence flush the 149 * driver data to ensure coherency. This is not required if the 150 * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY 151 * enabled. 152 */ 153 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 154 flush_dcache_range((uintptr_t) &gicv3_driver_data, 155 sizeof(gicv3_driver_data)); 156 flush_dcache_range((uintptr_t) gicv3_driver_data, 157 sizeof(*gicv3_driver_data)); 158 #endif 159 160 INFO("GICv3 %s legacy support detected." 161 " ARM GICV3 driver initialized in EL3\n", 162 gicv2_compat ? "with" : "without"); 163 } 164 165 /******************************************************************************* 166 * This function initialises the GIC distributor interface based upon the data 167 * provided by the platform while initialising the driver. 168 ******************************************************************************/ 169 void gicv3_distif_init(void) 170 { 171 unsigned int bitmap = 0; 172 173 assert(gicv3_driver_data); 174 assert(gicv3_driver_data->gicd_base); 175 176 assert(IS_IN_EL3()); 177 178 /* 179 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 180 * the ARE_S bit. The Distributor might generate a system error 181 * otherwise. 182 */ 183 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 184 CTLR_ENABLE_G0_BIT | 185 CTLR_ENABLE_G1S_BIT | 186 CTLR_ENABLE_G1NS_BIT, 187 RWP_TRUE); 188 189 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 190 gicd_set_ctlr(gicv3_driver_data->gicd_base, 191 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 192 193 /* Set the default attribute of all SPIs */ 194 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); 195 196 #if !ERROR_DEPRECATED 197 if (gicv3_driver_data->interrupt_props != NULL) { 198 #endif 199 bitmap = gicv3_secure_spis_config_props( 200 gicv3_driver_data->gicd_base, 201 gicv3_driver_data->interrupt_props, 202 gicv3_driver_data->interrupt_props_num); 203 #if !ERROR_DEPRECATED 204 } else { 205 /* 206 * Suppress deprecated declaration warnings in compatibility 207 * function 208 */ 209 #pragma GCC diagnostic push 210 #pragma GCC diagnostic ignored "-Wdeprecated-declarations" 211 212 assert(gicv3_driver_data->g1s_interrupt_array || 213 gicv3_driver_data->g0_interrupt_array); 214 215 /* Configure the G1S SPIs */ 216 if (gicv3_driver_data->g1s_interrupt_array) { 217 gicv3_secure_spis_config(gicv3_driver_data->gicd_base, 218 gicv3_driver_data->g1s_interrupt_num, 219 gicv3_driver_data->g1s_interrupt_array, 220 INTR_GROUP1S); 221 bitmap |= CTLR_ENABLE_G1S_BIT; 222 } 223 224 /* Configure the G0 SPIs */ 225 if (gicv3_driver_data->g0_interrupt_array) { 226 gicv3_secure_spis_config(gicv3_driver_data->gicd_base, 227 gicv3_driver_data->g0_interrupt_num, 228 gicv3_driver_data->g0_interrupt_array, 229 INTR_GROUP0); 230 bitmap |= CTLR_ENABLE_G0_BIT; 231 } 232 #pragma GCC diagnostic pop 233 } 234 #endif 235 236 /* Enable the secure SPIs now that they have been configured */ 237 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 238 } 239 240 /******************************************************************************* 241 * This function initialises the GIC Redistributor interface of the calling CPU 242 * (identified by the 'proc_num' parameter) based upon the data provided by the 243 * platform while initialising the driver. 244 ******************************************************************************/ 245 void gicv3_rdistif_init(unsigned int proc_num) 246 { 247 uintptr_t gicr_base; 248 unsigned int bitmap = 0; 249 uint32_t ctlr; 250 251 assert(gicv3_driver_data); 252 assert(proc_num < gicv3_driver_data->rdistif_num); 253 assert(gicv3_driver_data->rdistif_base_addrs); 254 assert(gicv3_driver_data->gicd_base); 255 256 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base); 257 assert(ctlr & CTLR_ARE_S_BIT); 258 259 assert(IS_IN_EL3()); 260 261 /* Power on redistributor */ 262 gicv3_rdistif_on(proc_num); 263 264 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 265 266 /* Set the default attribute of all SGIs and PPIs */ 267 gicv3_ppi_sgi_config_defaults(gicr_base); 268 269 #if !ERROR_DEPRECATED 270 if (gicv3_driver_data->interrupt_props != NULL) { 271 #endif 272 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, 273 gicv3_driver_data->interrupt_props, 274 gicv3_driver_data->interrupt_props_num); 275 #if !ERROR_DEPRECATED 276 } else { 277 /* 278 * Suppress deprecated declaration warnings in compatibility 279 * function 280 */ 281 #pragma GCC diagnostic push 282 #pragma GCC diagnostic ignored "-Wdeprecated-declarations" 283 284 assert(gicv3_driver_data->g1s_interrupt_array || 285 gicv3_driver_data->g0_interrupt_array); 286 287 /* Configure the G1S SGIs/PPIs */ 288 if (gicv3_driver_data->g1s_interrupt_array) { 289 gicv3_secure_ppi_sgi_config(gicr_base, 290 gicv3_driver_data->g1s_interrupt_num, 291 gicv3_driver_data->g1s_interrupt_array, 292 INTR_GROUP1S); 293 bitmap |= CTLR_ENABLE_G1S_BIT; 294 } 295 296 /* Configure the G0 SGIs/PPIs */ 297 if (gicv3_driver_data->g0_interrupt_array) { 298 gicv3_secure_ppi_sgi_config(gicr_base, 299 gicv3_driver_data->g0_interrupt_num, 300 gicv3_driver_data->g0_interrupt_array, 301 INTR_GROUP0); 302 bitmap |= CTLR_ENABLE_G0_BIT; 303 } 304 #pragma GCC diagnostic pop 305 } 306 #endif 307 308 /* Enable interrupt groups as required, if not already */ 309 if ((ctlr & bitmap) != bitmap) 310 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 311 } 312 313 /******************************************************************************* 314 * Functions to perform power operations on GIC Redistributor 315 ******************************************************************************/ 316 void gicv3_rdistif_off(unsigned int proc_num) 317 { 318 return; 319 } 320 321 void gicv3_rdistif_on(unsigned int proc_num) 322 { 323 return; 324 } 325 326 /******************************************************************************* 327 * This function enables the GIC CPU interface of the calling CPU using only 328 * system register accesses. 329 ******************************************************************************/ 330 void gicv3_cpuif_enable(unsigned int proc_num) 331 { 332 uintptr_t gicr_base; 333 unsigned int scr_el3; 334 unsigned int icc_sre_el3; 335 336 assert(gicv3_driver_data); 337 assert(proc_num < gicv3_driver_data->rdistif_num); 338 assert(gicv3_driver_data->rdistif_base_addrs); 339 assert(IS_IN_EL3()); 340 341 /* Mark the connected core as awake */ 342 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 343 gicv3_rdistif_mark_core_awake(gicr_base); 344 345 /* Disable the legacy interrupt bypass */ 346 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 347 348 /* 349 * Enable system register access for EL3 and allow lower exception 350 * levels to configure the same for themselves. If the legacy mode is 351 * not supported, the SRE bit is RAO/WI 352 */ 353 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 354 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 355 356 scr_el3 = read_scr_el3(); 357 358 /* 359 * Switch to NS state to write Non secure ICC_SRE_EL1 and 360 * ICC_SRE_EL2 registers. 361 */ 362 write_scr_el3(scr_el3 | SCR_NS_BIT); 363 isb(); 364 365 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 366 write_icc_sre_el1(ICC_SRE_SRE_BIT); 367 isb(); 368 369 /* Switch to secure state. */ 370 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 371 isb(); 372 373 /* Program the idle priority in the PMR */ 374 write_icc_pmr_el1(GIC_PRI_MASK); 375 376 /* Enable Group0 interrupts */ 377 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 378 379 /* Enable Group1 Secure interrupts */ 380 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 381 IGRPEN1_EL3_ENABLE_G1S_BIT); 382 383 /* Write the secure ICC_SRE_EL1 register */ 384 write_icc_sre_el1(ICC_SRE_SRE_BIT); 385 isb(); 386 } 387 388 /******************************************************************************* 389 * This function disables the GIC CPU interface of the calling CPU using 390 * only system register accesses. 391 ******************************************************************************/ 392 void gicv3_cpuif_disable(unsigned int proc_num) 393 { 394 uintptr_t gicr_base; 395 396 assert(gicv3_driver_data); 397 assert(proc_num < gicv3_driver_data->rdistif_num); 398 assert(gicv3_driver_data->rdistif_base_addrs); 399 400 assert(IS_IN_EL3()); 401 402 /* Disable legacy interrupt bypass */ 403 write_icc_sre_el3(read_icc_sre_el3() | 404 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 405 406 /* Disable Group0 interrupts */ 407 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 408 ~IGRPEN1_EL1_ENABLE_G0_BIT); 409 410 /* Disable Group1 Secure and Non-Secure interrupts */ 411 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 412 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 413 IGRPEN1_EL3_ENABLE_G1S_BIT)); 414 415 /* Synchronise accesses to group enable registers */ 416 isb(); 417 418 /* Mark the connected core as asleep */ 419 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 420 gicv3_rdistif_mark_core_asleep(gicr_base); 421 } 422 423 /******************************************************************************* 424 * This function returns the id of the highest priority pending interrupt at 425 * the GIC cpu interface. 426 ******************************************************************************/ 427 unsigned int gicv3_get_pending_interrupt_id(void) 428 { 429 unsigned int id; 430 431 assert(IS_IN_EL3()); 432 id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 433 434 /* 435 * If the ID is special identifier corresponding to G1S or G1NS 436 * interrupt, then read the highest pending group 1 interrupt. 437 */ 438 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) 439 return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 440 441 return id; 442 } 443 444 /******************************************************************************* 445 * This function returns the type of the highest priority pending interrupt at 446 * the GIC cpu interface. The return values can be one of the following : 447 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 448 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 449 * 0 - 1019 : The interrupt type is secure Group 0. 450 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 451 * sufficient priority to be signaled 452 ******************************************************************************/ 453 unsigned int gicv3_get_pending_interrupt_type(void) 454 { 455 assert(IS_IN_EL3()); 456 return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 457 } 458 459 /******************************************************************************* 460 * This function returns the type of the interrupt id depending upon the group 461 * this interrupt has been configured under by the interrupt controller i.e. 462 * group0 or group1 Secure / Non Secure. The return value can be one of the 463 * following : 464 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 465 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 466 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 467 * interrupt. 468 ******************************************************************************/ 469 unsigned int gicv3_get_interrupt_type(unsigned int id, 470 unsigned int proc_num) 471 { 472 unsigned int igroup, grpmodr; 473 uintptr_t gicr_base; 474 475 assert(IS_IN_EL3()); 476 assert(gicv3_driver_data); 477 478 /* Ensure the parameters are valid */ 479 assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID); 480 assert(proc_num < gicv3_driver_data->rdistif_num); 481 482 /* All LPI interrupts are Group 1 non secure */ 483 if (id >= MIN_LPI_ID) 484 return INTR_GROUP1NS; 485 486 if (id < MIN_SPI_ID) { 487 assert(gicv3_driver_data->rdistif_base_addrs); 488 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 489 igroup = gicr_get_igroupr0(gicr_base, id); 490 grpmodr = gicr_get_igrpmodr0(gicr_base, id); 491 } else { 492 assert(gicv3_driver_data->gicd_base); 493 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id); 494 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id); 495 } 496 497 /* 498 * If the IGROUP bit is set, then it is a Group 1 Non secure 499 * interrupt 500 */ 501 if (igroup) 502 return INTR_GROUP1NS; 503 504 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 505 if (grpmodr) 506 return INTR_GROUP1S; 507 508 /* Else it is a Group 0 Secure interrupt */ 509 return INTR_GROUP0; 510 } 511 512 /***************************************************************************** 513 * Function to save and disable the GIC ITS register context. The power 514 * management of GIC ITS is implementation-defined and this function doesn't 515 * save any memory structures required to support ITS. As the sequence to save 516 * this state is implementation defined, it should be executed in platform 517 * specific code. Calling this function alone and then powering down the GIC and 518 * ITS without implementing the aforementioned platform specific code will 519 * corrupt the ITS state. 520 * 521 * This function must be invoked after the GIC CPU interface is disabled. 522 *****************************************************************************/ 523 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx) 524 { 525 int i; 526 527 assert(gicv3_driver_data); 528 assert(IS_IN_EL3()); 529 assert(its_ctx); 530 assert(gits_base); 531 532 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 533 534 /* Disable the ITS */ 535 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & 536 (~GITS_CTLR_ENABLED_BIT)); 537 538 /* Wait for quiescent state */ 539 gits_wait_for_quiescent_bit(gits_base); 540 541 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 542 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 543 544 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++) 545 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 546 } 547 548 /***************************************************************************** 549 * Function to restore the GIC ITS register context. The power 550 * management of GIC ITS is implementation defined and this function doesn't 551 * restore any memory structures required to support ITS. The assumption is 552 * that these structures are in memory and are retained during system suspend. 553 * 554 * This must be invoked before the GIC CPU interface is enabled. 555 *****************************************************************************/ 556 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx) 557 { 558 int i; 559 560 assert(gicv3_driver_data); 561 assert(IS_IN_EL3()); 562 assert(its_ctx); 563 assert(gits_base); 564 565 /* Assert that the GITS is disabled and quiescent */ 566 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0); 567 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0); 568 569 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 570 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 571 572 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++) 573 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 574 575 /* Restore the ITS CTLR but leave the ITS disabled */ 576 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & 577 (~GITS_CTLR_ENABLED_BIT)); 578 } 579 580 /***************************************************************************** 581 * Function to save the GIC Redistributor register context. This function 582 * must be invoked after CPU interface disable and prior to Distributor save. 583 *****************************************************************************/ 584 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx) 585 { 586 uintptr_t gicr_base; 587 unsigned int int_id; 588 589 assert(gicv3_driver_data); 590 assert(proc_num < gicv3_driver_data->rdistif_num); 591 assert(gicv3_driver_data->rdistif_base_addrs); 592 assert(IS_IN_EL3()); 593 assert(rdist_ctx); 594 595 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 596 597 /* 598 * Wait for any write to GICR_CTLR to complete before trying to save any 599 * state. 600 */ 601 gicr_wait_for_pending_write(gicr_base); 602 603 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 604 605 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 606 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 607 608 rdist_ctx->gicr_igroupr0 = gicr_read_igroupr0(gicr_base); 609 rdist_ctx->gicr_isenabler0 = gicr_read_isenabler0(gicr_base); 610 rdist_ctx->gicr_ispendr0 = gicr_read_ispendr0(gicr_base); 611 rdist_ctx->gicr_isactiver0 = gicr_read_isactiver0(gicr_base); 612 rdist_ctx->gicr_icfgr0 = gicr_read_icfgr0(gicr_base); 613 rdist_ctx->gicr_icfgr1 = gicr_read_icfgr1(gicr_base); 614 rdist_ctx->gicr_igrpmodr0 = gicr_read_igrpmodr0(gicr_base); 615 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 616 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 617 int_id += (1 << IPRIORITYR_SHIFT)) { 618 rdist_ctx->gicr_ipriorityr[(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT] = 619 gicr_read_ipriorityr(gicr_base, int_id); 620 } 621 622 623 /* 624 * Call the pre-save hook that implements the IMP DEF sequence that may 625 * be required on some GIC implementations. As this may need to access 626 * the Redistributor registers, we pass it proc_num. 627 */ 628 gicv3_distif_pre_save(proc_num); 629 } 630 631 /***************************************************************************** 632 * Function to restore the GIC Redistributor register context. We disable 633 * LPI and per-cpu interrupts before we start restore of the Redistributor. 634 * This function must be invoked after Distributor restore but prior to 635 * CPU interface enable. The pending and active interrupts are restored 636 * after the interrupts are fully configured and enabled. 637 *****************************************************************************/ 638 void gicv3_rdistif_init_restore(unsigned int proc_num, 639 const gicv3_redist_ctx_t * const rdist_ctx) 640 { 641 uintptr_t gicr_base; 642 unsigned int int_id; 643 644 assert(gicv3_driver_data); 645 assert(proc_num < gicv3_driver_data->rdistif_num); 646 assert(gicv3_driver_data->rdistif_base_addrs); 647 assert(IS_IN_EL3()); 648 assert(rdist_ctx); 649 650 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 651 652 /* Power on redistributor */ 653 gicv3_rdistif_on(proc_num); 654 655 /* 656 * Call the post-restore hook that implements the IMP DEF sequence that 657 * may be required on some GIC implementations. As this may need to 658 * access the Redistributor registers, we pass it proc_num. 659 */ 660 gicv3_distif_post_restore(proc_num); 661 662 /* 663 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a 664 * more scalable approach as it avoids clearing the enable bits in the 665 * GICD_CTLR 666 */ 667 gicr_write_icenabler0(gicr_base, ~0); 668 /* Wait for pending writes to GICR_ICENABLER */ 669 gicr_wait_for_pending_write(gicr_base); 670 671 /* 672 * Disable the LPIs to avoid unpredictable behavior when writing to 673 * GICR_PROPBASER and GICR_PENDBASER. 674 */ 675 gicr_write_ctlr(gicr_base, 676 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 677 678 /* Restore registers' content */ 679 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 680 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 681 682 gicr_write_igroupr0(gicr_base, rdist_ctx->gicr_igroupr0); 683 684 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 685 int_id += (1 << IPRIORITYR_SHIFT)) { 686 gicr_write_ipriorityr(gicr_base, int_id, 687 rdist_ctx->gicr_ipriorityr[ 688 (int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT]); 689 } 690 691 gicr_write_icfgr0(gicr_base, rdist_ctx->gicr_icfgr0); 692 gicr_write_icfgr1(gicr_base, rdist_ctx->gicr_icfgr1); 693 gicr_write_igrpmodr0(gicr_base, rdist_ctx->gicr_igrpmodr0); 694 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 695 696 /* Restore after group and priorities are set */ 697 gicr_write_ispendr0(gicr_base, rdist_ctx->gicr_ispendr0); 698 gicr_write_isactiver0(gicr_base, rdist_ctx->gicr_isactiver0); 699 700 /* 701 * Wait for all writes to the Distributor to complete before enabling 702 * the SGI and PPIs. 703 */ 704 gicr_wait_for_upstream_pending_write(gicr_base); 705 gicr_write_isenabler0(gicr_base, rdist_ctx->gicr_isenabler0); 706 707 /* 708 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 709 * the first write to GICR_CTLR was still in flight (this write only 710 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 711 * bit). 712 */ 713 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 714 gicr_wait_for_pending_write(gicr_base); 715 } 716 717 /***************************************************************************** 718 * Function to save the GIC Distributor register context. This function 719 * must be invoked after CPU interface disable and Redistributor save. 720 *****************************************************************************/ 721 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 722 { 723 unsigned int num_ints; 724 725 assert(gicv3_driver_data); 726 assert(gicv3_driver_data->gicd_base); 727 assert(IS_IN_EL3()); 728 assert(dist_ctx); 729 730 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 731 732 num_ints = gicd_read_typer(gicd_base); 733 num_ints &= TYPER_IT_LINES_NO_MASK; 734 num_ints = (num_ints + 1) << 5; 735 736 assert(num_ints <= MAX_SPI_ID + 1); 737 738 /* Wait for pending write to complete */ 739 gicd_wait_for_pending_write(gicd_base); 740 741 /* Save the GICD_CTLR */ 742 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 743 744 /* Save GICD_IGROUPR for INTIDs 32 - 1020 */ 745 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 746 747 /* Save GICD_ISENABLER for INT_IDs 32 - 1020 */ 748 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 749 750 /* Save GICD_ISPENDR for INTIDs 32 - 1020 */ 751 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 752 753 /* Save GICD_ISACTIVER for INTIDs 32 - 1020 */ 754 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 755 756 /* Save GICD_IPRIORITYR for INTIDs 32 - 1020 */ 757 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 758 759 /* Save GICD_ICFGR for INTIDs 32 - 1020 */ 760 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 761 762 /* Save GICD_IGRPMODR for INTIDs 32 - 1020 */ 763 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 764 765 /* Save GICD_NSACR for INTIDs 32 - 1020 */ 766 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 767 768 /* Save GICD_IROUTER for INTIDs 32 - 1024 */ 769 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 770 771 /* 772 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 773 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 774 * driver. 775 */ 776 } 777 778 /***************************************************************************** 779 * Function to restore the GIC Distributor register context. We disable G0, G1S 780 * and G1NS interrupt groups before we start restore of the Distributor. This 781 * function must be invoked prior to Redistributor restore and CPU interface 782 * enable. The pending and active interrupts are restored after the interrupts 783 * are fully configured and enabled. 784 *****************************************************************************/ 785 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 786 { 787 unsigned int num_ints = 0; 788 789 assert(gicv3_driver_data); 790 assert(gicv3_driver_data->gicd_base); 791 assert(IS_IN_EL3()); 792 assert(dist_ctx); 793 794 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 795 796 /* 797 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 798 * the ARE_S bit. The Distributor might generate a system error 799 * otherwise. 800 */ 801 gicd_clr_ctlr(gicd_base, 802 CTLR_ENABLE_G0_BIT | 803 CTLR_ENABLE_G1S_BIT | 804 CTLR_ENABLE_G1NS_BIT, 805 RWP_TRUE); 806 807 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 808 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 809 810 num_ints = gicd_read_typer(gicd_base); 811 num_ints &= TYPER_IT_LINES_NO_MASK; 812 num_ints = (num_ints + 1) << 5; 813 814 assert(num_ints <= MAX_SPI_ID + 1); 815 816 /* Restore GICD_IGROUPR for INTIDs 32 - 1020 */ 817 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 818 819 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1020 */ 820 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 821 822 /* Restore GICD_ICFGR for INTIDs 32 - 1020 */ 823 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 824 825 /* Restore GICD_IGRPMODR for INTIDs 32 - 1020 */ 826 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 827 828 /* Restore GICD_NSACR for INTIDs 32 - 1020 */ 829 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 830 831 /* Restore GICD_IROUTER for INTIDs 32 - 1020 */ 832 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 833 834 /* 835 * Restore ISENABLER, ISPENDR and ISACTIVER after the interrupts are 836 * configured. 837 */ 838 839 /* Restore GICD_ISENABLER for INT_IDs 32 - 1020 */ 840 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 841 842 /* Restore GICD_ISPENDR for INTIDs 32 - 1020 */ 843 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 844 845 /* Restore GICD_ISACTIVER for INTIDs 32 - 1020 */ 846 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 847 848 /* Restore the GICD_CTLR */ 849 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 850 gicd_wait_for_pending_write(gicd_base); 851 852 } 853 854 /******************************************************************************* 855 * This function gets the priority of the interrupt the processor is currently 856 * servicing. 857 ******************************************************************************/ 858 unsigned int gicv3_get_running_priority(void) 859 { 860 return read_icc_rpr_el1(); 861 } 862 863 /******************************************************************************* 864 * This function checks if the interrupt identified by id is active (whether the 865 * state is either active, or active and pending). The proc_num is used if the 866 * interrupt is SGI or PPI and programs the corresponding Redistributor 867 * interface. 868 ******************************************************************************/ 869 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) 870 { 871 unsigned int value; 872 873 assert(gicv3_driver_data); 874 assert(gicv3_driver_data->gicd_base); 875 assert(proc_num < gicv3_driver_data->rdistif_num); 876 assert(gicv3_driver_data->rdistif_base_addrs); 877 assert(id <= MAX_SPI_ID); 878 879 if (id < MIN_SPI_ID) { 880 /* For SGIs and PPIs */ 881 value = gicr_get_isactiver0( 882 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 883 } else { 884 value = gicd_get_isactiver(gicv3_driver_data->gicd_base, id); 885 } 886 887 return value; 888 } 889 890 /******************************************************************************* 891 * This function enables the interrupt identified by id. The proc_num 892 * is used if the interrupt is SGI or PPI, and programs the corresponding 893 * Redistributor interface. 894 ******************************************************************************/ 895 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) 896 { 897 assert(gicv3_driver_data); 898 assert(gicv3_driver_data->gicd_base); 899 assert(proc_num < gicv3_driver_data->rdistif_num); 900 assert(gicv3_driver_data->rdistif_base_addrs); 901 assert(id <= MAX_SPI_ID); 902 903 /* 904 * Ensure that any shared variable updates depending on out of band 905 * interrupt trigger are observed before enabling interrupt. 906 */ 907 dsbishst(); 908 if (id < MIN_SPI_ID) { 909 /* For SGIs and PPIs */ 910 gicr_set_isenabler0( 911 gicv3_driver_data->rdistif_base_addrs[proc_num], 912 id); 913 } else { 914 gicd_set_isenabler(gicv3_driver_data->gicd_base, id); 915 } 916 } 917 918 /******************************************************************************* 919 * This function disables the interrupt identified by id. The proc_num 920 * is used if the interrupt is SGI or PPI, and programs the corresponding 921 * Redistributor interface. 922 ******************************************************************************/ 923 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) 924 { 925 assert(gicv3_driver_data); 926 assert(gicv3_driver_data->gicd_base); 927 assert(proc_num < gicv3_driver_data->rdistif_num); 928 assert(gicv3_driver_data->rdistif_base_addrs); 929 assert(id <= MAX_SPI_ID); 930 931 /* 932 * Disable interrupt, and ensure that any shared variable updates 933 * depending on out of band interrupt trigger are observed afterwards. 934 */ 935 if (id < MIN_SPI_ID) { 936 /* For SGIs and PPIs */ 937 gicr_set_icenabler0( 938 gicv3_driver_data->rdistif_base_addrs[proc_num], 939 id); 940 941 /* Write to clear enable requires waiting for pending writes */ 942 gicr_wait_for_pending_write( 943 gicv3_driver_data->rdistif_base_addrs[proc_num]); 944 } else { 945 gicd_set_icenabler(gicv3_driver_data->gicd_base, id); 946 947 /* Write to clear enable requires waiting for pending writes */ 948 gicd_wait_for_pending_write(gicv3_driver_data->gicd_base); 949 } 950 951 dsbishst(); 952 } 953 954 /******************************************************************************* 955 * This function sets the interrupt priority as supplied for the given interrupt 956 * id. 957 ******************************************************************************/ 958 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 959 unsigned int priority) 960 { 961 uintptr_t gicr_base; 962 963 assert(gicv3_driver_data); 964 assert(gicv3_driver_data->gicd_base); 965 assert(proc_num < gicv3_driver_data->rdistif_num); 966 assert(gicv3_driver_data->rdistif_base_addrs); 967 assert(id <= MAX_SPI_ID); 968 969 if (id < MIN_SPI_ID) { 970 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 971 gicr_set_ipriorityr(gicr_base, id, priority); 972 } else { 973 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority); 974 } 975 } 976 977 /******************************************************************************* 978 * This function assigns group for the interrupt identified by id. The proc_num 979 * is used if the interrupt is SGI or PPI, and programs the corresponding 980 * Redistributor interface. The group can be any of GICV3_INTR_GROUP* 981 ******************************************************************************/ 982 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 983 unsigned int type) 984 { 985 unsigned int igroup = 0, grpmod = 0; 986 uintptr_t gicr_base; 987 988 assert(gicv3_driver_data); 989 assert(gicv3_driver_data->gicd_base); 990 assert(proc_num < gicv3_driver_data->rdistif_num); 991 assert(gicv3_driver_data->rdistif_base_addrs); 992 993 switch (type) { 994 case INTR_GROUP1S: 995 igroup = 0; 996 grpmod = 1; 997 break; 998 case INTR_GROUP0: 999 igroup = 0; 1000 grpmod = 0; 1001 break; 1002 case INTR_GROUP1NS: 1003 igroup = 1; 1004 grpmod = 0; 1005 break; 1006 default: 1007 assert(0); 1008 break; 1009 } 1010 1011 if (id < MIN_SPI_ID) { 1012 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1013 if (igroup) 1014 gicr_set_igroupr0(gicr_base, id); 1015 else 1016 gicr_clr_igroupr0(gicr_base, id); 1017 1018 if (grpmod) 1019 gicr_set_igrpmodr0(gicr_base, id); 1020 else 1021 gicr_clr_igrpmodr0(gicr_base, id); 1022 } else { 1023 /* Serialize read-modify-write to Distributor registers */ 1024 spin_lock(&gic_lock); 1025 if (igroup) 1026 gicd_set_igroupr(gicv3_driver_data->gicd_base, id); 1027 else 1028 gicd_clr_igroupr(gicv3_driver_data->gicd_base, id); 1029 1030 if (grpmod) 1031 gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id); 1032 else 1033 gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id); 1034 spin_unlock(&gic_lock); 1035 } 1036 } 1037 1038 /******************************************************************************* 1039 * This function raises the specified Secure Group 0 SGI. 1040 * 1041 * The target parameter must be a valid MPIDR in the system. 1042 ******************************************************************************/ 1043 void gicv3_raise_secure_g0_sgi(int sgi_num, u_register_t target) 1044 { 1045 unsigned int tgt, aff3, aff2, aff1, aff0; 1046 uint64_t sgi_val; 1047 1048 /* Verify interrupt number is in the SGI range */ 1049 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID)); 1050 1051 /* Extract affinity fields from target */ 1052 aff0 = MPIDR_AFFLVL0_VAL(target); 1053 aff1 = MPIDR_AFFLVL1_VAL(target); 1054 aff2 = MPIDR_AFFLVL2_VAL(target); 1055 aff3 = MPIDR_AFFLVL3_VAL(target); 1056 1057 /* 1058 * Make target list from affinity 0, and ensure GICv3 SGI can target 1059 * this PE. 1060 */ 1061 assert(aff0 < GICV3_MAX_SGI_TARGETS); 1062 tgt = BIT(aff0); 1063 1064 /* Raise SGI to PE specified by its affinity */ 1065 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF, 1066 tgt); 1067 1068 /* 1069 * Ensure that any shared variable updates depending on out of band 1070 * interrupt trigger are observed before raising SGI. 1071 */ 1072 dsbishst(); 1073 write_icc_sgi0r_el1(sgi_val); 1074 isb(); 1075 } 1076 1077 /******************************************************************************* 1078 * This function sets the interrupt routing for the given SPI interrupt id. 1079 * The interrupt routing is specified in routing mode and mpidr. 1080 * 1081 * The routing mode can be either of: 1082 * - GICV3_IRM_ANY 1083 * - GICV3_IRM_PE 1084 * 1085 * The mpidr is the affinity of the PE to which the interrupt will be routed, 1086 * and is ignored for routing mode GICV3_IRM_ANY. 1087 ******************************************************************************/ 1088 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr) 1089 { 1090 unsigned long long aff; 1091 uint64_t router; 1092 1093 assert(gicv3_driver_data); 1094 assert(gicv3_driver_data->gicd_base); 1095 1096 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE)); 1097 assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID); 1098 1099 aff = gicd_irouter_val_from_mpidr(mpidr, irm); 1100 gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff); 1101 1102 /* 1103 * In implementations that do not require 1 of N distribution of SPIs, 1104 * IRM might be RAZ/WI. Read back and verify IRM bit. 1105 */ 1106 if (irm == GICV3_IRM_ANY) { 1107 router = gicd_read_irouter(gicv3_driver_data->gicd_base, id); 1108 if (!((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK)) { 1109 ERROR("GICv3 implementation doesn't support routing ANY\n"); 1110 panic(); 1111 } 1112 } 1113 } 1114 1115 /******************************************************************************* 1116 * This function clears the pending status of an interrupt identified by id. 1117 * The proc_num is used if the interrupt is SGI or PPI, and programs the 1118 * corresponding Redistributor interface. 1119 ******************************************************************************/ 1120 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num) 1121 { 1122 assert(gicv3_driver_data); 1123 assert(gicv3_driver_data->gicd_base); 1124 assert(proc_num < gicv3_driver_data->rdistif_num); 1125 assert(gicv3_driver_data->rdistif_base_addrs); 1126 1127 /* 1128 * Clear pending interrupt, and ensure that any shared variable updates 1129 * depending on out of band interrupt trigger are observed afterwards. 1130 */ 1131 if (id < MIN_SPI_ID) { 1132 /* For SGIs and PPIs */ 1133 gicr_set_icpendr0(gicv3_driver_data->rdistif_base_addrs[proc_num], 1134 id); 1135 } else { 1136 gicd_set_icpendr(gicv3_driver_data->gicd_base, id); 1137 } 1138 dsbishst(); 1139 } 1140 1141 /******************************************************************************* 1142 * This function sets the pending status of an interrupt identified by id. 1143 * The proc_num is used if the interrupt is SGI or PPI and programs the 1144 * corresponding Redistributor interface. 1145 ******************************************************************************/ 1146 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num) 1147 { 1148 assert(gicv3_driver_data); 1149 assert(gicv3_driver_data->gicd_base); 1150 assert(proc_num < gicv3_driver_data->rdistif_num); 1151 assert(gicv3_driver_data->rdistif_base_addrs); 1152 1153 /* 1154 * Ensure that any shared variable updates depending on out of band 1155 * interrupt trigger are observed before setting interrupt pending. 1156 */ 1157 dsbishst(); 1158 if (id < MIN_SPI_ID) { 1159 /* For SGIs and PPIs */ 1160 gicr_set_ispendr0(gicv3_driver_data->rdistif_base_addrs[proc_num], 1161 id); 1162 } else { 1163 gicd_set_ispendr(gicv3_driver_data->gicd_base, id); 1164 } 1165 } 1166 1167 /******************************************************************************* 1168 * This function sets the PMR register with the supplied value. Returns the 1169 * original PMR. 1170 ******************************************************************************/ 1171 unsigned int gicv3_set_pmr(unsigned int mask) 1172 { 1173 unsigned int old_mask; 1174 1175 old_mask = read_icc_pmr_el1(); 1176 1177 /* 1178 * Order memory updates w.r.t. PMR write, and ensure they're visible 1179 * before potential out of band interrupt trigger because of PMR update. 1180 * PMR system register writes are self-synchronizing, so no ISB required 1181 * thereafter. 1182 */ 1183 dsbishst(); 1184 write_icc_pmr_el1(mask); 1185 1186 return old_mask; 1187 } 1188