1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/interrupt_props.h> 13 #include <drivers/arm/gicv3.h> 14 #include <lib/spinlock.h> 15 16 #include "gicv3_private.h" 17 18 const gicv3_driver_data_t *gicv3_driver_data; 19 20 /* 21 * Spinlock to guard registers needing read-modify-write. APIs protected by this 22 * spinlock are used either at boot time (when only a single CPU is active), or 23 * when the system is fully coherent. 24 */ 25 static spinlock_t gic_lock; 26 27 /* 28 * Redistributor power operations are weakly bound so that they can be 29 * overridden 30 */ 31 #pragma weak gicv3_rdistif_off 32 #pragma weak gicv3_rdistif_on 33 34 /* Check interrupt ID for SGI/(E)PPI and (E)SPIs */ 35 static bool is_sgi_ppi(unsigned int id); 36 37 /* 38 * Helper macros to save and restore GICR and GICD registers 39 * corresponding to their numbers to and from the context 40 */ 41 #define RESTORE_GICR_REG(base, ctx, name, i) \ 42 gicr_write_##name((base), (i), (ctx)->gicr_##name[(i)]) 43 44 #define SAVE_GICR_REG(base, ctx, name, i) \ 45 (ctx)->gicr_##name[(i)] = gicr_read_##name((base), (i)) 46 47 /* Helper macros to save and restore GICD registers to and from the context */ 48 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 49 do { \ 50 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 51 int_id += (1U << REG##R_SHIFT)) { \ 52 gicd_write_##reg((base), int_id, \ 53 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 54 REG##R_SHIFT]); \ 55 } \ 56 } while (false) 57 58 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 59 do { \ 60 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 61 int_id += (1U << REG##R_SHIFT)) { \ 62 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 63 REG##R_SHIFT] = gicd_read_##reg((base), int_id); \ 64 } \ 65 } while (false) 66 67 #if GIC_EXT_INTID 68 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 69 do { \ 70 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 71 int_id += (1U << REG##R_SHIFT)) { \ 72 gicd_write_##reg((base), int_id, \ 73 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ 74 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ 75 >> REG##R_SHIFT]); \ 76 } \ 77 } while (false) 78 79 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 80 do { \ 81 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 82 int_id += (1U << REG##R_SHIFT)) { \ 83 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ 84 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ 85 >> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\ 86 } \ 87 } while (false) 88 #else 89 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) 90 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) 91 #endif /* GIC_EXT_INTID */ 92 93 /******************************************************************************* 94 * This function initialises the ARM GICv3 driver in EL3 with provided platform 95 * inputs. 96 ******************************************************************************/ 97 void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 98 { 99 unsigned int gic_version; 100 unsigned int gicv2_compat; 101 102 assert(plat_driver_data != NULL); 103 assert(plat_driver_data->gicd_base != 0U); 104 assert(plat_driver_data->rdistif_num != 0U); 105 assert(plat_driver_data->rdistif_base_addrs != NULL); 106 107 assert(IS_IN_EL3()); 108 109 assert((plat_driver_data->interrupt_props_num != 0U) ? 110 (plat_driver_data->interrupt_props != NULL) : 1); 111 112 /* Check for system register support */ 113 #ifndef __aarch64__ 114 assert((read_id_pfr1() & 115 (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); 116 #else 117 assert((read_id_aa64pfr0_el1() & 118 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U); 119 #endif /* !__aarch64__ */ 120 121 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 122 gic_version >>= PIDR2_ARCH_REV_SHIFT; 123 gic_version &= PIDR2_ARCH_REV_MASK; 124 125 /* Check GIC version */ 126 #if GIC_ENABLE_V4_EXTN 127 assert(gic_version == ARCH_REV_GICV4); 128 129 /* GICv4 supports Direct Virtual LPI injection */ 130 assert((gicd_read_typer(plat_driver_data->gicd_base) 131 & TYPER_DVIS) != 0); 132 #else 133 assert(gic_version == ARCH_REV_GICV3); 134 #endif 135 /* 136 * Find out whether the GIC supports the GICv2 compatibility mode. 137 * The ARE_S bit resets to 0 if supported 138 */ 139 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 140 gicv2_compat >>= CTLR_ARE_S_SHIFT; 141 gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK; 142 143 if (plat_driver_data->gicr_base != 0U) { 144 /* 145 * Find the base address of each implemented Redistributor interface. 146 * The number of interfaces should be equal to the number of CPUs in the 147 * system. The memory for saving these addresses has to be allocated by 148 * the platform port 149 */ 150 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 151 plat_driver_data->rdistif_num, 152 plat_driver_data->gicr_base, 153 plat_driver_data->mpidr_to_core_pos); 154 #if !HW_ASSISTED_COHERENCY 155 /* 156 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 157 */ 158 flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs), 159 plat_driver_data->rdistif_num * 160 sizeof(*(plat_driver_data->rdistif_base_addrs))); 161 #endif 162 } 163 gicv3_driver_data = plat_driver_data; 164 165 /* 166 * The GIC driver data is initialized by the primary CPU with caches 167 * enabled. When the secondary CPU boots up, it initializes the 168 * GICC/GICR interface with the caches disabled. Hence flush the 169 * driver data to ensure coherency. This is not required if the 170 * platform has HW_ASSISTED_COHERENCY enabled. 171 */ 172 #if !HW_ASSISTED_COHERENCY 173 flush_dcache_range((uintptr_t)&gicv3_driver_data, 174 sizeof(gicv3_driver_data)); 175 flush_dcache_range((uintptr_t)gicv3_driver_data, 176 sizeof(*gicv3_driver_data)); 177 #endif 178 INFO("GICv%u with%s legacy support detected.\n", gic_version, 179 (gicv2_compat == 0U) ? "" : "out"); 180 INFO("ARM GICv%u driver initialized in EL3\n", gic_version); 181 } 182 183 /******************************************************************************* 184 * This function initialises the GIC distributor interface based upon the data 185 * provided by the platform while initialising the driver. 186 ******************************************************************************/ 187 void __init gicv3_distif_init(void) 188 { 189 unsigned int bitmap; 190 191 assert(gicv3_driver_data != NULL); 192 assert(gicv3_driver_data->gicd_base != 0U); 193 194 assert(IS_IN_EL3()); 195 196 /* 197 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 198 * the ARE_S bit. The Distributor might generate a system error 199 * otherwise. 200 */ 201 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 202 CTLR_ENABLE_G0_BIT | 203 CTLR_ENABLE_G1S_BIT | 204 CTLR_ENABLE_G1NS_BIT, 205 RWP_TRUE); 206 207 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 208 gicd_set_ctlr(gicv3_driver_data->gicd_base, 209 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 210 211 /* Set the default attribute of all (E)SPIs */ 212 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); 213 214 bitmap = gicv3_secure_spis_config_props( 215 gicv3_driver_data->gicd_base, 216 gicv3_driver_data->interrupt_props, 217 gicv3_driver_data->interrupt_props_num); 218 219 /* Enable the secure (E)SPIs now that they have been configured */ 220 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 221 } 222 223 /******************************************************************************* 224 * This function initialises the GIC Redistributor interface of the calling CPU 225 * (identified by the 'proc_num' parameter) based upon the data provided by the 226 * platform while initialising the driver. 227 ******************************************************************************/ 228 void gicv3_rdistif_init(unsigned int proc_num) 229 { 230 uintptr_t gicr_base; 231 unsigned int bitmap; 232 uint32_t ctlr; 233 234 assert(gicv3_driver_data != NULL); 235 assert(proc_num < gicv3_driver_data->rdistif_num); 236 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 237 assert(gicv3_driver_data->gicd_base != 0U); 238 239 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base); 240 assert((ctlr & CTLR_ARE_S_BIT) != 0U); 241 242 assert(IS_IN_EL3()); 243 244 /* Power on redistributor */ 245 gicv3_rdistif_on(proc_num); 246 247 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 248 assert(gicr_base != 0U); 249 250 /* Set the default attribute of all SGIs and (E)PPIs */ 251 gicv3_ppi_sgi_config_defaults(gicr_base); 252 253 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, 254 gicv3_driver_data->interrupt_props, 255 gicv3_driver_data->interrupt_props_num); 256 257 /* Enable interrupt groups as required, if not already */ 258 if ((ctlr & bitmap) != bitmap) { 259 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 260 } 261 } 262 263 /******************************************************************************* 264 * Functions to perform power operations on GIC Redistributor 265 ******************************************************************************/ 266 void gicv3_rdistif_off(unsigned int proc_num) 267 { 268 } 269 270 void gicv3_rdistif_on(unsigned int proc_num) 271 { 272 } 273 274 /******************************************************************************* 275 * This function enables the GIC CPU interface of the calling CPU using only 276 * system register accesses. 277 ******************************************************************************/ 278 void gicv3_cpuif_enable(unsigned int proc_num) 279 { 280 uintptr_t gicr_base; 281 u_register_t scr_el3; 282 unsigned int icc_sre_el3; 283 284 assert(gicv3_driver_data != NULL); 285 assert(proc_num < gicv3_driver_data->rdistif_num); 286 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 287 assert(IS_IN_EL3()); 288 289 /* Mark the connected core as awake */ 290 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 291 gicv3_rdistif_mark_core_awake(gicr_base); 292 293 /* Disable the legacy interrupt bypass */ 294 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 295 296 /* 297 * Enable system register access for EL3 and allow lower exception 298 * levels to configure the same for themselves. If the legacy mode is 299 * not supported, the SRE bit is RAO/WI 300 */ 301 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 302 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 303 304 scr_el3 = read_scr_el3(); 305 306 /* 307 * Switch to NS state to write Non secure ICC_SRE_EL1 and 308 * ICC_SRE_EL2 registers. 309 */ 310 write_scr_el3(scr_el3 | SCR_NS_BIT); 311 isb(); 312 313 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 314 write_icc_sre_el1(ICC_SRE_SRE_BIT); 315 isb(); 316 317 /* Switch to secure state. */ 318 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 319 isb(); 320 321 /* Write the secure ICC_SRE_EL1 register */ 322 write_icc_sre_el1(ICC_SRE_SRE_BIT); 323 isb(); 324 325 /* Program the idle priority in the PMR */ 326 write_icc_pmr_el1(GIC_PRI_MASK); 327 328 /* Enable Group0 interrupts */ 329 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 330 331 /* Enable Group1 Secure interrupts */ 332 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 333 IGRPEN1_EL3_ENABLE_G1S_BIT); 334 isb(); 335 } 336 337 /******************************************************************************* 338 * This function disables the GIC CPU interface of the calling CPU using 339 * only system register accesses. 340 ******************************************************************************/ 341 void gicv3_cpuif_disable(unsigned int proc_num) 342 { 343 uintptr_t gicr_base; 344 345 assert(gicv3_driver_data != NULL); 346 assert(proc_num < gicv3_driver_data->rdistif_num); 347 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 348 349 assert(IS_IN_EL3()); 350 351 /* Disable legacy interrupt bypass */ 352 write_icc_sre_el3(read_icc_sre_el3() | 353 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 354 355 /* Disable Group0 interrupts */ 356 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 357 ~IGRPEN1_EL1_ENABLE_G0_BIT); 358 359 /* Disable Group1 Secure and Non-Secure interrupts */ 360 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 361 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 362 IGRPEN1_EL3_ENABLE_G1S_BIT)); 363 364 /* Synchronise accesses to group enable registers */ 365 isb(); 366 367 /* Mark the connected core as asleep */ 368 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 369 assert(gicr_base != 0U); 370 gicv3_rdistif_mark_core_asleep(gicr_base); 371 } 372 373 /******************************************************************************* 374 * This function returns the id of the highest priority pending interrupt at 375 * the GIC cpu interface. 376 ******************************************************************************/ 377 unsigned int gicv3_get_pending_interrupt_id(void) 378 { 379 unsigned int id; 380 381 assert(IS_IN_EL3()); 382 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 383 384 /* 385 * If the ID is special identifier corresponding to G1S or G1NS 386 * interrupt, then read the highest pending group 1 interrupt. 387 */ 388 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) { 389 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 390 } 391 392 return id; 393 } 394 395 /******************************************************************************* 396 * This function returns the type of the highest priority pending interrupt at 397 * the GIC cpu interface. The return values can be one of the following : 398 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 399 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 400 * 0 - 1019 : The interrupt type is secure Group 0. 401 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 402 * sufficient priority to be signaled 403 ******************************************************************************/ 404 unsigned int gicv3_get_pending_interrupt_type(void) 405 { 406 assert(IS_IN_EL3()); 407 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 408 } 409 410 /******************************************************************************* 411 * This function returns the type of the interrupt id depending upon the group 412 * this interrupt has been configured under by the interrupt controller i.e. 413 * group0 or group1 Secure / Non Secure. The return value can be one of the 414 * following : 415 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 416 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 417 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 418 * interrupt. 419 ******************************************************************************/ 420 unsigned int gicv3_get_interrupt_type(unsigned int id, unsigned int proc_num) 421 { 422 unsigned int igroup, grpmodr; 423 uintptr_t gicr_base; 424 425 assert(IS_IN_EL3()); 426 assert(gicv3_driver_data != NULL); 427 428 /* Ensure the parameters are valid */ 429 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID)); 430 assert(proc_num < gicv3_driver_data->rdistif_num); 431 432 /* All LPI interrupts are Group 1 non secure */ 433 if (id >= MIN_LPI_ID) { 434 return INTR_GROUP1NS; 435 } 436 437 /* Check interrupt ID */ 438 if (is_sgi_ppi(id)) { 439 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 440 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 441 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 442 igroup = gicr_get_igroupr(gicr_base, id); 443 grpmodr = gicr_get_igrpmodr(gicr_base, id); 444 } else { 445 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 446 assert(gicv3_driver_data->gicd_base != 0U); 447 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id); 448 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id); 449 } 450 451 /* 452 * If the IGROUP bit is set, then it is a Group 1 Non secure 453 * interrupt 454 */ 455 if (igroup != 0U) { 456 return INTR_GROUP1NS; 457 } 458 459 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 460 if (grpmodr != 0U) { 461 return INTR_GROUP1S; 462 } 463 464 /* Else it is a Group 0 Secure interrupt */ 465 return INTR_GROUP0; 466 } 467 468 /***************************************************************************** 469 * Function to save and disable the GIC ITS register context. The power 470 * management of GIC ITS is implementation-defined and this function doesn't 471 * save any memory structures required to support ITS. As the sequence to save 472 * this state is implementation defined, it should be executed in platform 473 * specific code. Calling this function alone and then powering down the GIC and 474 * ITS without implementing the aforementioned platform specific code will 475 * corrupt the ITS state. 476 * 477 * This function must be invoked after the GIC CPU interface is disabled. 478 *****************************************************************************/ 479 void gicv3_its_save_disable(uintptr_t gits_base, 480 gicv3_its_ctx_t * const its_ctx) 481 { 482 unsigned int i; 483 484 assert(gicv3_driver_data != NULL); 485 assert(IS_IN_EL3()); 486 assert(its_ctx != NULL); 487 assert(gits_base != 0U); 488 489 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 490 491 /* Disable the ITS */ 492 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 493 494 /* Wait for quiescent state */ 495 gits_wait_for_quiescent_bit(gits_base); 496 497 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 498 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 499 500 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 501 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 502 } 503 } 504 505 /***************************************************************************** 506 * Function to restore the GIC ITS register context. The power 507 * management of GIC ITS is implementation defined and this function doesn't 508 * restore any memory structures required to support ITS. The assumption is 509 * that these structures are in memory and are retained during system suspend. 510 * 511 * This must be invoked before the GIC CPU interface is enabled. 512 *****************************************************************************/ 513 void gicv3_its_restore(uintptr_t gits_base, 514 const gicv3_its_ctx_t * const its_ctx) 515 { 516 unsigned int i; 517 518 assert(gicv3_driver_data != NULL); 519 assert(IS_IN_EL3()); 520 assert(its_ctx != NULL); 521 assert(gits_base != 0U); 522 523 /* Assert that the GITS is disabled and quiescent */ 524 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 525 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U); 526 527 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 528 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 529 530 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 531 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 532 } 533 534 /* Restore the ITS CTLR but leave the ITS disabled */ 535 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 536 } 537 538 /***************************************************************************** 539 * Function to save the GIC Redistributor register context. This function 540 * must be invoked after CPU interface disable and prior to Distributor save. 541 *****************************************************************************/ 542 void gicv3_rdistif_save(unsigned int proc_num, 543 gicv3_redist_ctx_t * const rdist_ctx) 544 { 545 uintptr_t gicr_base; 546 unsigned int i, ppi_regs_num, regs_num; 547 548 assert(gicv3_driver_data != NULL); 549 assert(proc_num < gicv3_driver_data->rdistif_num); 550 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 551 assert(IS_IN_EL3()); 552 assert(rdist_ctx != NULL); 553 554 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 555 556 #if GIC_EXT_INTID 557 /* Calculate number of PPI registers */ 558 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 559 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 560 /* All other values except PPInum [0-2] are reserved */ 561 if (ppi_regs_num > 3U) { 562 ppi_regs_num = 1U; 563 } 564 #else 565 ppi_regs_num = 1U; 566 #endif 567 /* 568 * Wait for any write to GICR_CTLR to complete before trying to save any 569 * state. 570 */ 571 gicr_wait_for_pending_write(gicr_base); 572 573 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 574 575 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 576 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 577 578 /* 32 interrupt IDs per register */ 579 for (i = 0U; i < ppi_regs_num; ++i) { 580 SAVE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 581 SAVE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 582 SAVE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 583 SAVE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 584 SAVE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 585 } 586 587 /* 16 interrupt IDs per GICR_ICFGR register */ 588 regs_num = ppi_regs_num << 1; 589 for (i = 0U; i < regs_num; ++i) { 590 SAVE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 591 } 592 593 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 594 595 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 596 regs_num = ppi_regs_num << 3; 597 for (i = 0U; i < regs_num; ++i) { 598 rdist_ctx->gicr_ipriorityr[i] = 599 gicr_ipriorityr_read(gicr_base, i); 600 } 601 602 /* 603 * Call the pre-save hook that implements the IMP DEF sequence that may 604 * be required on some GIC implementations. As this may need to access 605 * the Redistributor registers, we pass it proc_num. 606 */ 607 gicv3_distif_pre_save(proc_num); 608 } 609 610 /***************************************************************************** 611 * Function to restore the GIC Redistributor register context. We disable 612 * LPI and per-cpu interrupts before we start restore of the Redistributor. 613 * This function must be invoked after Distributor restore but prior to 614 * CPU interface enable. The pending and active interrupts are restored 615 * after the interrupts are fully configured and enabled. 616 *****************************************************************************/ 617 void gicv3_rdistif_init_restore(unsigned int proc_num, 618 const gicv3_redist_ctx_t * const rdist_ctx) 619 { 620 uintptr_t gicr_base; 621 unsigned int i, ppi_regs_num, regs_num; 622 623 assert(gicv3_driver_data != NULL); 624 assert(proc_num < gicv3_driver_data->rdistif_num); 625 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 626 assert(IS_IN_EL3()); 627 assert(rdist_ctx != NULL); 628 629 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 630 631 #if GIC_EXT_INTID 632 /* Calculate number of PPI registers */ 633 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 634 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 635 /* All other values except PPInum [0-2] are reserved */ 636 if (ppi_regs_num > 3U) { 637 ppi_regs_num = 1U; 638 } 639 #else 640 ppi_regs_num = 1U; 641 #endif 642 /* Power on redistributor */ 643 gicv3_rdistif_on(proc_num); 644 645 /* 646 * Call the post-restore hook that implements the IMP DEF sequence that 647 * may be required on some GIC implementations. As this may need to 648 * access the Redistributor registers, we pass it proc_num. 649 */ 650 gicv3_distif_post_restore(proc_num); 651 652 /* 653 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 654 * This is a more scalable approach as it avoids clearing the enable 655 * bits in the GICD_CTLR. 656 */ 657 for (i = 0U; i < ppi_regs_num; ++i) { 658 gicr_write_icenabler(gicr_base, i, ~0U); 659 } 660 661 /* Wait for pending writes to GICR_ICENABLER */ 662 gicr_wait_for_pending_write(gicr_base); 663 664 /* 665 * Disable the LPIs to avoid unpredictable behavior when writing to 666 * GICR_PROPBASER and GICR_PENDBASER. 667 */ 668 gicr_write_ctlr(gicr_base, 669 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 670 671 /* Restore registers' content */ 672 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 673 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 674 675 /* 32 interrupt IDs per register */ 676 for (i = 0U; i < ppi_regs_num; ++i) { 677 RESTORE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 678 RESTORE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 679 } 680 681 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 682 regs_num = ppi_regs_num << 3; 683 for (i = 0U; i < regs_num; ++i) { 684 gicr_ipriorityr_write(gicr_base, i, 685 rdist_ctx->gicr_ipriorityr[i]); 686 } 687 688 /* 16 interrupt IDs per GICR_ICFGR register */ 689 regs_num = ppi_regs_num << 1; 690 for (i = 0U; i < regs_num; ++i) { 691 RESTORE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 692 } 693 694 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 695 696 /* Restore after group and priorities are set. 697 * 32 interrupt IDs per register 698 */ 699 for (i = 0U; i < ppi_regs_num; ++i) { 700 RESTORE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 701 RESTORE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 702 } 703 704 /* 705 * Wait for all writes to the Distributor to complete before enabling 706 * the SGI and (E)PPIs. 707 */ 708 gicr_wait_for_upstream_pending_write(gicr_base); 709 710 /* 32 interrupt IDs per GICR_ISENABLER register */ 711 for (i = 0U; i < ppi_regs_num; ++i) { 712 RESTORE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 713 } 714 715 /* 716 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 717 * the first write to GICR_CTLR was still in flight (this write only 718 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 719 * bit). 720 */ 721 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 722 gicr_wait_for_pending_write(gicr_base); 723 } 724 725 /***************************************************************************** 726 * Function to save the GIC Distributor register context. This function 727 * must be invoked after CPU interface disable and Redistributor save. 728 *****************************************************************************/ 729 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 730 { 731 unsigned int typer_reg, num_ints; 732 #if GIC_EXT_INTID 733 unsigned int num_eints; 734 #endif 735 736 assert(gicv3_driver_data != NULL); 737 assert(gicv3_driver_data->gicd_base != 0U); 738 assert(IS_IN_EL3()); 739 assert(dist_ctx != NULL); 740 741 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 742 743 typer_reg = gicd_read_typer(gicd_base); 744 745 /* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */ 746 num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5; 747 748 /* Filter out special INTIDs 1020-1023 */ 749 if (num_ints > (MAX_SPI_ID + 1U)) { 750 num_ints = MAX_SPI_ID + 1U; 751 } 752 753 #if GIC_EXT_INTID 754 /* Check if extended SPI range is implemented */ 755 if ((typer_reg & TYPER_ESPI) != 0U) { 756 /* 757 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095 758 */ 759 num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) & 760 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID; 761 } else { 762 num_eints = 0U; 763 } 764 #endif 765 /* Wait for pending write to complete */ 766 gicd_wait_for_pending_write(gicd_base); 767 768 /* Save the GICD_CTLR */ 769 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 770 771 /* Save GICD_IGROUPR for INTIDs 32 - 1019 */ 772 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 773 774 /* Save GICD_IGROUPRE for INTIDs 4096 - 5119 */ 775 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 776 777 /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */ 778 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 779 780 /* Save GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 781 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 782 783 /* Save GICD_ISPENDR for INTIDs 32 - 1019 */ 784 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 785 786 /* Save GICD_ISPENDRE for INTIDs 4096 - 5119 */ 787 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 788 789 /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */ 790 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 791 792 /* Save GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 793 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 794 795 /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */ 796 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 797 798 /* Save GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 799 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 800 801 /* Save GICD_ICFGR for INTIDs 32 - 1019 */ 802 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 803 804 /* Save GICD_ICFGRE for INTIDs 4096 - 5119 */ 805 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 806 807 /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */ 808 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 809 810 /* Save GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 811 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 812 813 /* Save GICD_NSACR for INTIDs 32 - 1019 */ 814 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 815 816 /* Save GICD_NSACRE for INTIDs 4096 - 5119 */ 817 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 818 819 /* Save GICD_IROUTER for INTIDs 32 - 1019 */ 820 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 821 822 /* Save GICD_IROUTERE for INTIDs 4096 - 5119 */ 823 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 824 825 /* 826 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 827 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 828 * driver. 829 */ 830 } 831 832 /***************************************************************************** 833 * Function to restore the GIC Distributor register context. We disable G0, G1S 834 * and G1NS interrupt groups before we start restore of the Distributor. This 835 * function must be invoked prior to Redistributor restore and CPU interface 836 * enable. The pending and active interrupts are restored after the interrupts 837 * are fully configured and enabled. 838 *****************************************************************************/ 839 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 840 { 841 unsigned int typer_reg, num_ints; 842 #if GIC_EXT_INTID 843 unsigned int num_eints; 844 #endif 845 846 assert(gicv3_driver_data != NULL); 847 assert(gicv3_driver_data->gicd_base != 0U); 848 assert(IS_IN_EL3()); 849 assert(dist_ctx != NULL); 850 851 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 852 853 /* 854 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 855 * the ARE_S bit. The Distributor might generate a system error 856 * otherwise. 857 */ 858 gicd_clr_ctlr(gicd_base, 859 CTLR_ENABLE_G0_BIT | 860 CTLR_ENABLE_G1S_BIT | 861 CTLR_ENABLE_G1NS_BIT, 862 RWP_TRUE); 863 864 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 865 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 866 867 typer_reg = gicd_read_typer(gicd_base); 868 869 /* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */ 870 num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5; 871 872 /* Filter out special INTIDs 1020-1023 */ 873 if (num_ints > (MAX_SPI_ID + 1U)) { 874 num_ints = MAX_SPI_ID + 1U; 875 } 876 877 #if GIC_EXT_INTID 878 /* Check if extended SPI range is implemented */ 879 if ((typer_reg & TYPER_ESPI) != 0U) { 880 /* 881 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095 882 */ 883 num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) & 884 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID; 885 } else { 886 num_eints = 0U; 887 } 888 #endif 889 /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */ 890 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 891 892 /* Restore GICD_IGROUPRE for INTIDs 4096 - 5119 */ 893 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 894 895 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */ 896 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 897 898 /* Restore GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 899 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 900 901 /* Restore GICD_ICFGR for INTIDs 32 - 1019 */ 902 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 903 904 /* Restore GICD_ICFGRE for INTIDs 4096 - 5119 */ 905 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 906 907 /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */ 908 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 909 910 /* Restore GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 911 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 912 913 /* Restore GICD_NSACR for INTIDs 32 - 1019 */ 914 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 915 916 /* Restore GICD_NSACRE for INTIDs 4096 - 5119 */ 917 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 918 919 /* Restore GICD_IROUTER for INTIDs 32 - 1019 */ 920 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 921 922 /* Restore GICD_IROUTERE for INTIDs 4096 - 5119 */ 923 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 924 925 /* 926 * Restore ISENABLER(E), ISPENDR(E) and ISACTIVER(E) after 927 * the interrupts are configured. 928 */ 929 930 /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */ 931 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 932 933 /* Restore GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 934 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 935 936 /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */ 937 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 938 939 /* Restore GICD_ISPENDRE for INTIDs 4096 - 5119 */ 940 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 941 942 /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */ 943 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 944 945 /* Restore GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 946 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 947 948 /* Restore the GICD_CTLR */ 949 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 950 gicd_wait_for_pending_write(gicd_base); 951 } 952 953 /******************************************************************************* 954 * This function gets the priority of the interrupt the processor is currently 955 * servicing. 956 ******************************************************************************/ 957 unsigned int gicv3_get_running_priority(void) 958 { 959 return (unsigned int)read_icc_rpr_el1(); 960 } 961 962 /******************************************************************************* 963 * This function checks if the interrupt identified by id is active (whether the 964 * state is either active, or active and pending). The proc_num is used if the 965 * interrupt is SGI or (E)PPI and programs the corresponding Redistributor 966 * interface. 967 ******************************************************************************/ 968 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) 969 { 970 assert(gicv3_driver_data != NULL); 971 assert(gicv3_driver_data->gicd_base != 0U); 972 assert(proc_num < gicv3_driver_data->rdistif_num); 973 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 974 975 /* Check interrupt ID */ 976 if (is_sgi_ppi(id)) { 977 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 978 return gicr_get_isactiver( 979 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 980 } 981 982 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 983 return gicd_get_isactiver(gicv3_driver_data->gicd_base, id); 984 } 985 986 /******************************************************************************* 987 * This function enables the interrupt identified by id. The proc_num 988 * is used if the interrupt is SGI or PPI, and programs the corresponding 989 * Redistributor interface. 990 ******************************************************************************/ 991 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) 992 { 993 assert(gicv3_driver_data != NULL); 994 assert(gicv3_driver_data->gicd_base != 0U); 995 assert(proc_num < gicv3_driver_data->rdistif_num); 996 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 997 998 /* 999 * Ensure that any shared variable updates depending on out of band 1000 * interrupt trigger are observed before enabling interrupt. 1001 */ 1002 dsbishst(); 1003 1004 /* Check interrupt ID */ 1005 if (is_sgi_ppi(id)) { 1006 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1007 gicr_set_isenabler( 1008 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1009 } else { 1010 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1011 gicd_set_isenabler(gicv3_driver_data->gicd_base, id); 1012 } 1013 } 1014 1015 /******************************************************************************* 1016 * This function disables the interrupt identified by id. The proc_num 1017 * is used if the interrupt is SGI or PPI, and programs the corresponding 1018 * Redistributor interface. 1019 ******************************************************************************/ 1020 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) 1021 { 1022 assert(gicv3_driver_data != NULL); 1023 assert(gicv3_driver_data->gicd_base != 0U); 1024 assert(proc_num < gicv3_driver_data->rdistif_num); 1025 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1026 1027 /* 1028 * Disable interrupt, and ensure that any shared variable updates 1029 * depending on out of band interrupt trigger are observed afterwards. 1030 */ 1031 1032 /* Check interrupt ID */ 1033 if (is_sgi_ppi(id)) { 1034 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1035 gicr_set_icenabler( 1036 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1037 1038 /* Write to clear enable requires waiting for pending writes */ 1039 gicr_wait_for_pending_write( 1040 gicv3_driver_data->rdistif_base_addrs[proc_num]); 1041 } else { 1042 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1043 gicd_set_icenabler(gicv3_driver_data->gicd_base, id); 1044 1045 /* Write to clear enable requires waiting for pending writes */ 1046 gicd_wait_for_pending_write(gicv3_driver_data->gicd_base); 1047 } 1048 1049 dsbishst(); 1050 } 1051 1052 /******************************************************************************* 1053 * This function sets the interrupt priority as supplied for the given interrupt 1054 * id. 1055 ******************************************************************************/ 1056 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 1057 unsigned int priority) 1058 { 1059 uintptr_t gicr_base; 1060 1061 assert(gicv3_driver_data != NULL); 1062 assert(gicv3_driver_data->gicd_base != 0U); 1063 assert(proc_num < gicv3_driver_data->rdistif_num); 1064 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1065 1066 /* Check interrupt ID */ 1067 if (is_sgi_ppi(id)) { 1068 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1069 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1070 gicr_set_ipriorityr(gicr_base, id, priority); 1071 } else { 1072 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1073 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority); 1074 } 1075 } 1076 1077 /******************************************************************************* 1078 * This function assigns group for the interrupt identified by id. The proc_num 1079 * is used if the interrupt is SGI or (E)PPI, and programs the corresponding 1080 * Redistributor interface. The group can be any of GICV3_INTR_GROUP* 1081 ******************************************************************************/ 1082 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 1083 unsigned int type) 1084 { 1085 bool igroup = false, grpmod = false; 1086 uintptr_t gicr_base; 1087 1088 assert(gicv3_driver_data != NULL); 1089 assert(gicv3_driver_data->gicd_base != 0U); 1090 assert(proc_num < gicv3_driver_data->rdistif_num); 1091 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1092 1093 switch (type) { 1094 case INTR_GROUP1S: 1095 igroup = false; 1096 grpmod = true; 1097 break; 1098 case INTR_GROUP0: 1099 igroup = false; 1100 grpmod = false; 1101 break; 1102 case INTR_GROUP1NS: 1103 igroup = true; 1104 grpmod = false; 1105 break; 1106 default: 1107 assert(false); 1108 break; 1109 } 1110 1111 /* Check interrupt ID */ 1112 if (is_sgi_ppi(id)) { 1113 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1114 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1115 1116 igroup ? gicr_set_igroupr(gicr_base, id) : 1117 gicr_clr_igroupr(gicr_base, id); 1118 grpmod ? gicr_set_igrpmodr(gicr_base, id) : 1119 gicr_clr_igrpmodr(gicr_base, id); 1120 } else { 1121 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1122 1123 /* Serialize read-modify-write to Distributor registers */ 1124 spin_lock(&gic_lock); 1125 1126 igroup ? gicd_set_igroupr(gicv3_driver_data->gicd_base, id) : 1127 gicd_clr_igroupr(gicv3_driver_data->gicd_base, id); 1128 grpmod ? gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id) : 1129 gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id); 1130 1131 spin_unlock(&gic_lock); 1132 } 1133 } 1134 1135 /******************************************************************************* 1136 * This function raises the specified Secure Group 0 SGI. 1137 * 1138 * The target parameter must be a valid MPIDR in the system. 1139 ******************************************************************************/ 1140 void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target) 1141 { 1142 unsigned int tgt, aff3, aff2, aff1, aff0; 1143 uint64_t sgi_val; 1144 1145 /* Verify interrupt number is in the SGI range */ 1146 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID)); 1147 1148 /* Extract affinity fields from target */ 1149 aff0 = MPIDR_AFFLVL0_VAL(target); 1150 aff1 = MPIDR_AFFLVL1_VAL(target); 1151 aff2 = MPIDR_AFFLVL2_VAL(target); 1152 aff3 = MPIDR_AFFLVL3_VAL(target); 1153 1154 /* 1155 * Make target list from affinity 0, and ensure GICv3 SGI can target 1156 * this PE. 1157 */ 1158 assert(aff0 < GICV3_MAX_SGI_TARGETS); 1159 tgt = BIT_32(aff0); 1160 1161 /* Raise SGI to PE specified by its affinity */ 1162 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF, 1163 tgt); 1164 1165 /* 1166 * Ensure that any shared variable updates depending on out of band 1167 * interrupt trigger are observed before raising SGI. 1168 */ 1169 dsbishst(); 1170 write_icc_sgi0r_el1(sgi_val); 1171 isb(); 1172 } 1173 1174 /******************************************************************************* 1175 * This function sets the interrupt routing for the given (E)SPI interrupt id. 1176 * The interrupt routing is specified in routing mode and mpidr. 1177 * 1178 * The routing mode can be either of: 1179 * - GICV3_IRM_ANY 1180 * - GICV3_IRM_PE 1181 * 1182 * The mpidr is the affinity of the PE to which the interrupt will be routed, 1183 * and is ignored for routing mode GICV3_IRM_ANY. 1184 ******************************************************************************/ 1185 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr) 1186 { 1187 unsigned long long aff; 1188 uint64_t router; 1189 1190 assert(gicv3_driver_data != NULL); 1191 assert(gicv3_driver_data->gicd_base != 0U); 1192 1193 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE)); 1194 1195 assert(IS_SPI(id)); 1196 1197 aff = gicd_irouter_val_from_mpidr(mpidr, irm); 1198 gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff); 1199 1200 /* 1201 * In implementations that do not require 1 of N distribution of SPIs, 1202 * IRM might be RAZ/WI. Read back and verify IRM bit. 1203 */ 1204 if (irm == GICV3_IRM_ANY) { 1205 router = gicd_read_irouter(gicv3_driver_data->gicd_base, id); 1206 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) { 1207 ERROR("GICv3 implementation doesn't support routing ANY\n"); 1208 panic(); 1209 } 1210 } 1211 } 1212 1213 /******************************************************************************* 1214 * This function clears the pending status of an interrupt identified by id. 1215 * The proc_num is used if the interrupt is SGI or (E)PPI, and programs the 1216 * corresponding Redistributor interface. 1217 ******************************************************************************/ 1218 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num) 1219 { 1220 assert(gicv3_driver_data != NULL); 1221 assert(gicv3_driver_data->gicd_base != 0U); 1222 assert(proc_num < gicv3_driver_data->rdistif_num); 1223 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1224 1225 /* 1226 * Clear pending interrupt, and ensure that any shared variable updates 1227 * depending on out of band interrupt trigger are observed afterwards. 1228 */ 1229 1230 /* Check interrupt ID */ 1231 if (is_sgi_ppi(id)) { 1232 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1233 gicr_set_icpendr( 1234 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1235 } else { 1236 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1237 gicd_set_icpendr(gicv3_driver_data->gicd_base, id); 1238 } 1239 1240 dsbishst(); 1241 } 1242 1243 /******************************************************************************* 1244 * This function sets the pending status of an interrupt identified by id. 1245 * The proc_num is used if the interrupt is SGI or PPI and programs the 1246 * corresponding Redistributor interface. 1247 ******************************************************************************/ 1248 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num) 1249 { 1250 assert(gicv3_driver_data != NULL); 1251 assert(gicv3_driver_data->gicd_base != 0U); 1252 assert(proc_num < gicv3_driver_data->rdistif_num); 1253 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1254 1255 /* 1256 * Ensure that any shared variable updates depending on out of band 1257 * interrupt trigger are observed before setting interrupt pending. 1258 */ 1259 dsbishst(); 1260 1261 /* Check interrupt ID */ 1262 if (is_sgi_ppi(id)) { 1263 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1264 gicr_set_ispendr( 1265 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1266 } else { 1267 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1268 gicd_set_ispendr(gicv3_driver_data->gicd_base, id); 1269 } 1270 } 1271 1272 /******************************************************************************* 1273 * This function sets the PMR register with the supplied value. Returns the 1274 * original PMR. 1275 ******************************************************************************/ 1276 unsigned int gicv3_set_pmr(unsigned int mask) 1277 { 1278 unsigned int old_mask; 1279 1280 old_mask = (unsigned int)read_icc_pmr_el1(); 1281 1282 /* 1283 * Order memory updates w.r.t. PMR write, and ensure they're visible 1284 * before potential out of band interrupt trigger because of PMR update. 1285 * PMR system register writes are self-synchronizing, so no ISB required 1286 * thereafter. 1287 */ 1288 dsbishst(); 1289 write_icc_pmr_el1(mask); 1290 1291 return old_mask; 1292 } 1293 1294 /******************************************************************************* 1295 * This function delegates the responsibility of discovering the corresponding 1296 * Redistributor frames to each CPU itself. It is a modified version of 1297 * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform 1298 * unlike the previous way in which only the Primary CPU did the discovery of 1299 * all the Redistributor frames for every CPU. It also handles the scenario in 1300 * which the frames of various CPUs are not contiguous in physical memory. 1301 ******************************************************************************/ 1302 int gicv3_rdistif_probe(const uintptr_t gicr_frame) 1303 { 1304 u_register_t mpidr, mpidr_self; 1305 unsigned int proc_num; 1306 uint64_t typer_val; 1307 uintptr_t rdistif_base; 1308 bool gicr_frame_found = false; 1309 1310 assert(gicv3_driver_data->gicr_base == 0U); 1311 1312 /* Ensure this function is called with Data Cache enabled */ 1313 #ifndef __aarch64__ 1314 assert((read_sctlr() & SCTLR_C_BIT) != 0U); 1315 #else 1316 assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U); 1317 #endif /* !__aarch64__ */ 1318 1319 mpidr_self = read_mpidr_el1() & MPIDR_AFFINITY_MASK; 1320 rdistif_base = gicr_frame; 1321 do { 1322 typer_val = gicr_read_typer(rdistif_base); 1323 mpidr = mpidr_from_gicr_typer(typer_val); 1324 if (gicv3_driver_data->mpidr_to_core_pos != NULL) { 1325 proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr); 1326 } else { 1327 proc_num = (unsigned int)(typer_val >> 1328 TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK; 1329 } 1330 if (mpidr == mpidr_self) { 1331 /* The base address doesn't need to be initialized on 1332 * every warm boot. 1333 */ 1334 if (gicv3_driver_data->rdistif_base_addrs[proc_num] 1335 != 0U) { 1336 return 0; 1337 } 1338 gicv3_driver_data->rdistif_base_addrs[proc_num] = 1339 rdistif_base; 1340 gicr_frame_found = true; 1341 break; 1342 } 1343 rdistif_base += (uintptr_t)(ULL(1) << GICR_PCPUBASE_SHIFT); 1344 } while ((typer_val & TYPER_LAST_BIT) == 0U); 1345 1346 if (!gicr_frame_found) { 1347 return -1; 1348 } 1349 1350 /* 1351 * Flush the driver data to ensure coherency. This is 1352 * not required if platform has HW_ASSISTED_COHERENCY 1353 * enabled. 1354 */ 1355 #if !HW_ASSISTED_COHERENCY 1356 /* 1357 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 1358 */ 1359 flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]), 1360 sizeof(*(gicv3_driver_data->rdistif_base_addrs))); 1361 #endif 1362 return 0; /* Found matching GICR frame */ 1363 } 1364 1365 /****************************************************************************** 1366 * This function checks the interrupt ID and returns true for SGIs and (E)PPIs 1367 * and false for (E)SPIs IDs. 1368 *****************************************************************************/ 1369 static bool is_sgi_ppi(unsigned int id) 1370 { 1371 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 1372 if (IS_SGI_PPI(id)) { 1373 return true; 1374 } 1375 1376 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 1377 if (IS_SPI(id)) { 1378 return false; 1379 } 1380 1381 assert(false); 1382 panic(); 1383 } 1384