1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gicv3.h> 12 #include "gicv3_private.h" 13 14 const gicv3_driver_data_t *gicv3_driver_data; 15 static unsigned int gicv2_compat; 16 17 /* 18 * Redistributor power operations are weakly bound so that they can be 19 * overridden 20 */ 21 #pragma weak gicv3_rdistif_off 22 #pragma weak gicv3_rdistif_on 23 24 25 /* Helper macros to save and restore GICD registers to and from the context */ 26 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 27 do { \ 28 for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \ 29 int_id += (1 << REG##_SHIFT)) { \ 30 gicd_write_##reg(base, int_id, \ 31 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT]); \ 32 } \ 33 } while (0) 34 35 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 36 do { \ 37 for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \ 38 int_id += (1 << REG##_SHIFT)) { \ 39 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT] =\ 40 gicd_read_##reg(base, int_id); \ 41 } \ 42 } while (0) 43 44 45 /******************************************************************************* 46 * This function initialises the ARM GICv3 driver in EL3 with provided platform 47 * inputs. 48 ******************************************************************************/ 49 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 50 { 51 unsigned int gic_version; 52 53 assert(plat_driver_data); 54 assert(plat_driver_data->gicd_base); 55 assert(plat_driver_data->gicr_base); 56 assert(plat_driver_data->rdistif_num); 57 assert(plat_driver_data->rdistif_base_addrs); 58 59 assert(IS_IN_EL3()); 60 61 /* 62 * The platform should provide a list of at least one type of 63 * interrupts 64 */ 65 assert(plat_driver_data->g0_interrupt_array || 66 plat_driver_data->g1s_interrupt_array); 67 68 /* 69 * If there are no interrupts of a particular type, then the number of 70 * interrupts of that type should be 0 and vice-versa. 71 */ 72 assert(plat_driver_data->g0_interrupt_array ? 73 plat_driver_data->g0_interrupt_num : 74 plat_driver_data->g0_interrupt_num == 0); 75 assert(plat_driver_data->g1s_interrupt_array ? 76 plat_driver_data->g1s_interrupt_num : 77 plat_driver_data->g1s_interrupt_num == 0); 78 79 /* Check for system register support */ 80 #ifdef AARCH32 81 assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)); 82 #else 83 assert(read_id_aa64pfr0_el1() & 84 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)); 85 #endif /* AARCH32 */ 86 87 /* The GIC version should be 3.0 */ 88 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 89 gic_version >>= PIDR2_ARCH_REV_SHIFT; 90 gic_version &= PIDR2_ARCH_REV_MASK; 91 assert(gic_version == ARCH_REV_GICV3); 92 93 /* 94 * Find out whether the GIC supports the GICv2 compatibility mode. The 95 * ARE_S bit resets to 0 if supported 96 */ 97 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 98 gicv2_compat >>= CTLR_ARE_S_SHIFT; 99 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); 100 101 /* 102 * Find the base address of each implemented Redistributor interface. 103 * The number of interfaces should be equal to the number of CPUs in the 104 * system. The memory for saving these addresses has to be allocated by 105 * the platform port 106 */ 107 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 108 plat_driver_data->rdistif_num, 109 plat_driver_data->gicr_base, 110 plat_driver_data->mpidr_to_core_pos); 111 112 gicv3_driver_data = plat_driver_data; 113 114 /* 115 * The GIC driver data is initialized by the primary CPU with caches 116 * enabled. When the secondary CPU boots up, it initializes the 117 * GICC/GICR interface with the caches disabled. Hence flush the 118 * driver data to ensure coherency. This is not required if the 119 * platform has HW_ASSISTED_COHERENCY enabled. 120 */ 121 #if !HW_ASSISTED_COHERENCY 122 flush_dcache_range((uintptr_t) &gicv3_driver_data, 123 sizeof(gicv3_driver_data)); 124 flush_dcache_range((uintptr_t) gicv3_driver_data, 125 sizeof(*gicv3_driver_data)); 126 #endif 127 128 INFO("GICv3 %s legacy support detected." 129 " ARM GICV3 driver initialized in EL3\n", 130 gicv2_compat ? "with" : "without"); 131 } 132 133 /******************************************************************************* 134 * This function initialises the GIC distributor interface based upon the data 135 * provided by the platform while initialising the driver. 136 ******************************************************************************/ 137 void gicv3_distif_init(void) 138 { 139 unsigned int bitmap = 0; 140 141 assert(gicv3_driver_data); 142 assert(gicv3_driver_data->gicd_base); 143 assert(gicv3_driver_data->g1s_interrupt_array || 144 gicv3_driver_data->g0_interrupt_array); 145 146 assert(IS_IN_EL3()); 147 148 /* 149 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 150 * the ARE_S bit. The Distributor might generate a system error 151 * otherwise. 152 */ 153 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 154 CTLR_ENABLE_G0_BIT | 155 CTLR_ENABLE_G1S_BIT | 156 CTLR_ENABLE_G1NS_BIT, 157 RWP_TRUE); 158 159 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 160 gicd_set_ctlr(gicv3_driver_data->gicd_base, 161 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 162 163 /* Set the default attribute of all SPIs */ 164 gicv3_spis_configure_defaults(gicv3_driver_data->gicd_base); 165 166 /* Configure the G1S SPIs */ 167 if (gicv3_driver_data->g1s_interrupt_array) { 168 gicv3_secure_spis_configure(gicv3_driver_data->gicd_base, 169 gicv3_driver_data->g1s_interrupt_num, 170 gicv3_driver_data->g1s_interrupt_array, 171 INTR_GROUP1S); 172 bitmap |= CTLR_ENABLE_G1S_BIT; 173 } 174 175 /* Configure the G0 SPIs */ 176 if (gicv3_driver_data->g0_interrupt_array) { 177 gicv3_secure_spis_configure(gicv3_driver_data->gicd_base, 178 gicv3_driver_data->g0_interrupt_num, 179 gicv3_driver_data->g0_interrupt_array, 180 INTR_GROUP0); 181 bitmap |= CTLR_ENABLE_G0_BIT; 182 } 183 184 /* Enable the secure SPIs now that they have been configured */ 185 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 186 } 187 188 /******************************************************************************* 189 * This function initialises the GIC Redistributor interface of the calling CPU 190 * (identified by the 'proc_num' parameter) based upon the data provided by the 191 * platform while initialising the driver. 192 ******************************************************************************/ 193 void gicv3_rdistif_init(unsigned int proc_num) 194 { 195 uintptr_t gicr_base; 196 197 assert(gicv3_driver_data); 198 assert(proc_num < gicv3_driver_data->rdistif_num); 199 assert(gicv3_driver_data->rdistif_base_addrs); 200 assert(gicv3_driver_data->gicd_base); 201 assert(gicd_read_ctlr(gicv3_driver_data->gicd_base) & CTLR_ARE_S_BIT); 202 assert(gicv3_driver_data->g1s_interrupt_array || 203 gicv3_driver_data->g0_interrupt_array); 204 205 assert(IS_IN_EL3()); 206 207 /* Power on redistributor */ 208 gicv3_rdistif_on(proc_num); 209 210 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 211 212 /* Set the default attribute of all SGIs and PPIs */ 213 gicv3_ppi_sgi_configure_defaults(gicr_base); 214 215 /* Configure the G1S SGIs/PPIs */ 216 if (gicv3_driver_data->g1s_interrupt_array) { 217 gicv3_secure_ppi_sgi_configure(gicr_base, 218 gicv3_driver_data->g1s_interrupt_num, 219 gicv3_driver_data->g1s_interrupt_array, 220 INTR_GROUP1S); 221 } 222 223 /* Configure the G0 SGIs/PPIs */ 224 if (gicv3_driver_data->g0_interrupt_array) { 225 gicv3_secure_ppi_sgi_configure(gicr_base, 226 gicv3_driver_data->g0_interrupt_num, 227 gicv3_driver_data->g0_interrupt_array, 228 INTR_GROUP0); 229 } 230 } 231 232 /******************************************************************************* 233 * Functions to perform power operations on GIC Redistributor 234 ******************************************************************************/ 235 void gicv3_rdistif_off(unsigned int proc_num) 236 { 237 return; 238 } 239 240 void gicv3_rdistif_on(unsigned int proc_num) 241 { 242 return; 243 } 244 245 /******************************************************************************* 246 * This function enables the GIC CPU interface of the calling CPU using only 247 * system register accesses. 248 ******************************************************************************/ 249 void gicv3_cpuif_enable(unsigned int proc_num) 250 { 251 uintptr_t gicr_base; 252 unsigned int scr_el3; 253 unsigned int icc_sre_el3; 254 255 assert(gicv3_driver_data); 256 assert(proc_num < gicv3_driver_data->rdistif_num); 257 assert(gicv3_driver_data->rdistif_base_addrs); 258 assert(IS_IN_EL3()); 259 260 /* Mark the connected core as awake */ 261 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 262 gicv3_rdistif_mark_core_awake(gicr_base); 263 264 /* Disable the legacy interrupt bypass */ 265 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 266 267 /* 268 * Enable system register access for EL3 and allow lower exception 269 * levels to configure the same for themselves. If the legacy mode is 270 * not supported, the SRE bit is RAO/WI 271 */ 272 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 273 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 274 275 scr_el3 = read_scr_el3(); 276 277 /* 278 * Switch to NS state to write Non secure ICC_SRE_EL1 and 279 * ICC_SRE_EL2 registers. 280 */ 281 write_scr_el3(scr_el3 | SCR_NS_BIT); 282 isb(); 283 284 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 285 write_icc_sre_el1(ICC_SRE_SRE_BIT); 286 isb(); 287 288 /* Switch to secure state. */ 289 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 290 isb(); 291 292 /* Program the idle priority in the PMR */ 293 write_icc_pmr_el1(GIC_PRI_MASK); 294 295 /* Enable Group0 interrupts */ 296 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 297 298 /* Enable Group1 Secure interrupts */ 299 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 300 IGRPEN1_EL3_ENABLE_G1S_BIT); 301 302 /* Write the secure ICC_SRE_EL1 register */ 303 write_icc_sre_el1(ICC_SRE_SRE_BIT); 304 isb(); 305 } 306 307 /******************************************************************************* 308 * This function disables the GIC CPU interface of the calling CPU using 309 * only system register accesses. 310 ******************************************************************************/ 311 void gicv3_cpuif_disable(unsigned int proc_num) 312 { 313 uintptr_t gicr_base; 314 315 assert(gicv3_driver_data); 316 assert(proc_num < gicv3_driver_data->rdistif_num); 317 assert(gicv3_driver_data->rdistif_base_addrs); 318 319 assert(IS_IN_EL3()); 320 321 /* Disable legacy interrupt bypass */ 322 write_icc_sre_el3(read_icc_sre_el3() | 323 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 324 325 /* Disable Group0 interrupts */ 326 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 327 ~IGRPEN1_EL1_ENABLE_G0_BIT); 328 329 /* Disable Group1 Secure and Non-Secure interrupts */ 330 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 331 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 332 IGRPEN1_EL3_ENABLE_G1S_BIT)); 333 334 /* Synchronise accesses to group enable registers */ 335 isb(); 336 337 /* Mark the connected core as asleep */ 338 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 339 gicv3_rdistif_mark_core_asleep(gicr_base); 340 } 341 342 /******************************************************************************* 343 * This function returns the id of the highest priority pending interrupt at 344 * the GIC cpu interface. 345 ******************************************************************************/ 346 unsigned int gicv3_get_pending_interrupt_id(void) 347 { 348 unsigned int id; 349 350 assert(IS_IN_EL3()); 351 id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 352 353 /* 354 * If the ID is special identifier corresponding to G1S or G1NS 355 * interrupt, then read the highest pending group 1 interrupt. 356 */ 357 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) 358 return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 359 360 return id; 361 } 362 363 /******************************************************************************* 364 * This function returns the type of the highest priority pending interrupt at 365 * the GIC cpu interface. The return values can be one of the following : 366 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 367 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 368 * 0 - 1019 : The interrupt type is secure Group 0. 369 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 370 * sufficient priority to be signaled 371 ******************************************************************************/ 372 unsigned int gicv3_get_pending_interrupt_type(void) 373 { 374 assert(IS_IN_EL3()); 375 return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 376 } 377 378 /******************************************************************************* 379 * This function returns the type of the interrupt id depending upon the group 380 * this interrupt has been configured under by the interrupt controller i.e. 381 * group0 or group1 Secure / Non Secure. The return value can be one of the 382 * following : 383 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 384 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 385 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 386 * interrupt. 387 ******************************************************************************/ 388 unsigned int gicv3_get_interrupt_type(unsigned int id, 389 unsigned int proc_num) 390 { 391 unsigned int igroup, grpmodr; 392 uintptr_t gicr_base; 393 394 assert(IS_IN_EL3()); 395 assert(gicv3_driver_data); 396 397 /* Ensure the parameters are valid */ 398 assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID); 399 assert(proc_num < gicv3_driver_data->rdistif_num); 400 401 /* All LPI interrupts are Group 1 non secure */ 402 if (id >= MIN_LPI_ID) 403 return INTR_GROUP1NS; 404 405 if (id < MIN_SPI_ID) { 406 assert(gicv3_driver_data->rdistif_base_addrs); 407 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 408 igroup = gicr_get_igroupr0(gicr_base, id); 409 grpmodr = gicr_get_igrpmodr0(gicr_base, id); 410 } else { 411 assert(gicv3_driver_data->gicd_base); 412 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id); 413 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id); 414 } 415 416 /* 417 * If the IGROUP bit is set, then it is a Group 1 Non secure 418 * interrupt 419 */ 420 if (igroup) 421 return INTR_GROUP1NS; 422 423 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 424 if (grpmodr) 425 return INTR_GROUP1S; 426 427 /* Else it is a Group 0 Secure interrupt */ 428 return INTR_GROUP0; 429 } 430 431 /***************************************************************************** 432 * Function to save and disable the GIC ITS register context. The power 433 * management of GIC ITS is implementation-defined and this function doesn't 434 * save any memory structures required to support ITS. As the sequence to save 435 * this state is implementation defined, it should be executed in platform 436 * specific code. Calling this function alone and then powering down the GIC and 437 * ITS without implementing the aforementioned platform specific code will 438 * corrupt the ITS state. 439 * 440 * This function must be invoked after the GIC CPU interface is disabled. 441 *****************************************************************************/ 442 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx) 443 { 444 int i; 445 446 assert(gicv3_driver_data); 447 assert(IS_IN_EL3()); 448 assert(its_ctx); 449 assert(gits_base); 450 451 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 452 453 /* Disable the ITS */ 454 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & 455 (~GITS_CTLR_ENABLED_BIT)); 456 457 /* Wait for quiescent state */ 458 gits_wait_for_quiescent_bit(gits_base); 459 460 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 461 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 462 463 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++) 464 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 465 } 466 467 /***************************************************************************** 468 * Function to restore the GIC ITS register context. The power 469 * management of GIC ITS is implementation defined and this function doesn't 470 * restore any memory structures required to support ITS. The assumption is 471 * that these structures are in memory and are retained during system suspend. 472 * 473 * This must be invoked before the GIC CPU interface is enabled. 474 *****************************************************************************/ 475 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx) 476 { 477 int i; 478 479 assert(gicv3_driver_data); 480 assert(IS_IN_EL3()); 481 assert(its_ctx); 482 assert(gits_base); 483 484 /* Assert that the GITS is disabled and quiescent */ 485 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0); 486 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0); 487 488 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 489 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 490 491 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++) 492 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 493 494 /* Restore the ITS CTLR but leave the ITS disabled */ 495 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & 496 (~GITS_CTLR_ENABLED_BIT)); 497 } 498 499 /***************************************************************************** 500 * Function to save the GIC Redistributor register context. This function 501 * must be invoked after CPU interface disable and prior to Distributor save. 502 *****************************************************************************/ 503 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx) 504 { 505 uintptr_t gicr_base; 506 unsigned int int_id; 507 508 assert(gicv3_driver_data); 509 assert(proc_num < gicv3_driver_data->rdistif_num); 510 assert(gicv3_driver_data->rdistif_base_addrs); 511 assert(IS_IN_EL3()); 512 assert(rdist_ctx); 513 514 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 515 516 /* 517 * Wait for any write to GICR_CTLR to complete before trying to save any 518 * state. 519 */ 520 gicr_wait_for_pending_write(gicr_base); 521 522 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 523 524 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 525 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 526 527 rdist_ctx->gicr_igroupr0 = gicr_read_igroupr0(gicr_base); 528 rdist_ctx->gicr_isenabler0 = gicr_read_isenabler0(gicr_base); 529 rdist_ctx->gicr_ispendr0 = gicr_read_ispendr0(gicr_base); 530 rdist_ctx->gicr_isactiver0 = gicr_read_isactiver0(gicr_base); 531 rdist_ctx->gicr_icfgr0 = gicr_read_icfgr0(gicr_base); 532 rdist_ctx->gicr_icfgr1 = gicr_read_icfgr1(gicr_base); 533 rdist_ctx->gicr_igrpmodr0 = gicr_read_igrpmodr0(gicr_base); 534 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 535 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 536 int_id += (1 << IPRIORITYR_SHIFT)) { 537 rdist_ctx->gicr_ipriorityr[(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT] = 538 gicr_read_ipriorityr(gicr_base, int_id); 539 } 540 541 542 /* 543 * Call the pre-save hook that implements the IMP DEF sequence that may 544 * be required on some GIC implementations. As this may need to access 545 * the Redistributor registers, we pass it proc_num. 546 */ 547 gicv3_distif_pre_save(proc_num); 548 } 549 550 /***************************************************************************** 551 * Function to restore the GIC Redistributor register context. We disable 552 * LPI and per-cpu interrupts before we start restore of the Redistributor. 553 * This function must be invoked after Distributor restore but prior to 554 * CPU interface enable. The pending and active interrupts are restored 555 * after the interrupts are fully configured and enabled. 556 *****************************************************************************/ 557 void gicv3_rdistif_init_restore(unsigned int proc_num, 558 const gicv3_redist_ctx_t * const rdist_ctx) 559 { 560 uintptr_t gicr_base; 561 unsigned int int_id; 562 563 assert(gicv3_driver_data); 564 assert(proc_num < gicv3_driver_data->rdistif_num); 565 assert(gicv3_driver_data->rdistif_base_addrs); 566 assert(IS_IN_EL3()); 567 assert(rdist_ctx); 568 569 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 570 571 /* Power on redistributor */ 572 gicv3_rdistif_on(proc_num); 573 574 /* 575 * Call the post-restore hook that implements the IMP DEF sequence that 576 * may be required on some GIC implementations. As this may need to 577 * access the Redistributor registers, we pass it proc_num. 578 */ 579 gicv3_distif_post_restore(proc_num); 580 581 /* 582 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a 583 * more scalable approach as it avoids clearing the enable bits in the 584 * GICD_CTLR 585 */ 586 gicr_write_icenabler0(gicr_base, ~0); 587 /* Wait for pending writes to GICR_ICENABLER */ 588 gicr_wait_for_pending_write(gicr_base); 589 590 /* 591 * Disable the LPIs to avoid unpredictable behavior when writing to 592 * GICR_PROPBASER and GICR_PENDBASER. 593 */ 594 gicr_write_ctlr(gicr_base, 595 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 596 597 /* Restore registers' content */ 598 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 599 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 600 601 gicr_write_igroupr0(gicr_base, rdist_ctx->gicr_igroupr0); 602 603 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 604 int_id += (1 << IPRIORITYR_SHIFT)) { 605 gicr_write_ipriorityr(gicr_base, int_id, 606 rdist_ctx->gicr_ipriorityr[ 607 (int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT]); 608 } 609 610 gicr_write_icfgr0(gicr_base, rdist_ctx->gicr_icfgr0); 611 gicr_write_icfgr1(gicr_base, rdist_ctx->gicr_icfgr1); 612 gicr_write_igrpmodr0(gicr_base, rdist_ctx->gicr_igrpmodr0); 613 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 614 615 /* Restore after group and priorities are set */ 616 gicr_write_ispendr0(gicr_base, rdist_ctx->gicr_ispendr0); 617 gicr_write_isactiver0(gicr_base, rdist_ctx->gicr_isactiver0); 618 619 /* 620 * Wait for all writes to the Distributor to complete before enabling 621 * the SGI and PPIs. 622 */ 623 gicr_wait_for_upstream_pending_write(gicr_base); 624 gicr_write_isenabler0(gicr_base, rdist_ctx->gicr_isenabler0); 625 626 /* 627 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 628 * the first write to GICR_CTLR was still in flight (this write only 629 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 630 * bit). 631 */ 632 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 633 gicr_wait_for_pending_write(gicr_base); 634 } 635 636 /***************************************************************************** 637 * Function to save the GIC Distributor register context. This function 638 * must be invoked after CPU interface disable and Redistributor save. 639 *****************************************************************************/ 640 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 641 { 642 unsigned int num_ints; 643 644 assert(gicv3_driver_data); 645 assert(gicv3_driver_data->gicd_base); 646 assert(IS_IN_EL3()); 647 assert(dist_ctx); 648 649 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 650 651 num_ints = gicd_read_typer(gicd_base); 652 num_ints &= TYPER_IT_LINES_NO_MASK; 653 num_ints = (num_ints + 1) << 5; 654 655 assert(num_ints <= MAX_SPI_ID + 1); 656 657 /* Wait for pending write to complete */ 658 gicd_wait_for_pending_write(gicd_base); 659 660 /* Save the GICD_CTLR */ 661 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 662 663 /* Save GICD_IGROUPR for INTIDs 32 - 1020 */ 664 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 665 666 /* Save GICD_ISENABLER for INT_IDs 32 - 1020 */ 667 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 668 669 /* Save GICD_ISPENDR for INTIDs 32 - 1020 */ 670 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 671 672 /* Save GICD_ISACTIVER for INTIDs 32 - 1020 */ 673 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 674 675 /* Save GICD_IPRIORITYR for INTIDs 32 - 1020 */ 676 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 677 678 /* Save GICD_ICFGR for INTIDs 32 - 1020 */ 679 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 680 681 /* Save GICD_IGRPMODR for INTIDs 32 - 1020 */ 682 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 683 684 /* Save GICD_NSACR for INTIDs 32 - 1020 */ 685 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 686 687 /* Save GICD_IROUTER for INTIDs 32 - 1024 */ 688 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 689 690 /* 691 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 692 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 693 * driver. 694 */ 695 } 696 697 /***************************************************************************** 698 * Function to restore the GIC Distributor register context. We disable G0, G1S 699 * and G1NS interrupt groups before we start restore of the Distributor. This 700 * function must be invoked prior to Redistributor restore and CPU interface 701 * enable. The pending and active interrupts are restored after the interrupts 702 * are fully configured and enabled. 703 *****************************************************************************/ 704 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 705 { 706 unsigned int num_ints = 0; 707 708 assert(gicv3_driver_data); 709 assert(gicv3_driver_data->gicd_base); 710 assert(IS_IN_EL3()); 711 assert(dist_ctx); 712 713 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 714 715 /* 716 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 717 * the ARE_S bit. The Distributor might generate a system error 718 * otherwise. 719 */ 720 gicd_clr_ctlr(gicd_base, 721 CTLR_ENABLE_G0_BIT | 722 CTLR_ENABLE_G1S_BIT | 723 CTLR_ENABLE_G1NS_BIT, 724 RWP_TRUE); 725 726 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 727 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 728 729 num_ints = gicd_read_typer(gicd_base); 730 num_ints &= TYPER_IT_LINES_NO_MASK; 731 num_ints = (num_ints + 1) << 5; 732 733 assert(num_ints <= MAX_SPI_ID + 1); 734 735 /* Restore GICD_IGROUPR for INTIDs 32 - 1020 */ 736 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 737 738 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1020 */ 739 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 740 741 /* Restore GICD_ICFGR for INTIDs 32 - 1020 */ 742 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 743 744 /* Restore GICD_IGRPMODR for INTIDs 32 - 1020 */ 745 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 746 747 /* Restore GICD_NSACR for INTIDs 32 - 1020 */ 748 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 749 750 /* Restore GICD_IROUTER for INTIDs 32 - 1020 */ 751 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 752 753 /* 754 * Restore ISENABLER, ISPENDR and ISACTIVER after the interrupts are 755 * configured. 756 */ 757 758 /* Restore GICD_ISENABLER for INT_IDs 32 - 1020 */ 759 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 760 761 /* Restore GICD_ISPENDR for INTIDs 32 - 1020 */ 762 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 763 764 /* Restore GICD_ISACTIVER for INTIDs 32 - 1020 */ 765 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 766 767 /* Restore the GICD_CTLR */ 768 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 769 gicd_wait_for_pending_write(gicd_base); 770 771 } 772