1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <debug.h> 35 #include <gic_common.h> 36 #include <gicv3.h> 37 #include "gicv3_private.h" 38 39 static const gicv3_driver_data_t *driver_data; 40 static unsigned int gicv2_compat; 41 42 /******************************************************************************* 43 * This function initialises the ARM GICv3 driver in EL3 with provided platform 44 * inputs. 45 ******************************************************************************/ 46 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 47 { 48 unsigned int gic_version; 49 50 assert(plat_driver_data); 51 assert(plat_driver_data->gicd_base); 52 assert(plat_driver_data->gicr_base); 53 assert(plat_driver_data->rdistif_num); 54 assert(plat_driver_data->rdistif_base_addrs); 55 56 assert(IS_IN_EL3()); 57 58 /* 59 * The platform should provide a list of at least one type of 60 * interrupts 61 */ 62 assert(plat_driver_data->g0_interrupt_array || 63 plat_driver_data->g1s_interrupt_array); 64 65 /* 66 * If there are no interrupts of a particular type, then the number of 67 * interrupts of that type should be 0 and vice-versa. 68 */ 69 assert(plat_driver_data->g0_interrupt_array ? 70 plat_driver_data->g0_interrupt_num : 71 plat_driver_data->g0_interrupt_num == 0); 72 assert(plat_driver_data->g1s_interrupt_array ? 73 plat_driver_data->g1s_interrupt_num : 74 plat_driver_data->g1s_interrupt_num == 0); 75 76 /* Check for system register support */ 77 assert(read_id_aa64pfr0_el1() & 78 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)); 79 80 /* The GIC version should be 3.0 */ 81 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 82 gic_version >>= PIDR2_ARCH_REV_SHIFT; 83 gic_version &= PIDR2_ARCH_REV_MASK; 84 assert(gic_version == ARCH_REV_GICV3); 85 86 /* 87 * Find out whether the GIC supports the GICv2 compatibility mode. The 88 * ARE_S bit resets to 0 if supported 89 */ 90 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 91 gicv2_compat >>= CTLR_ARE_S_SHIFT; 92 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); 93 94 /* 95 * Find the base address of each implemented Redistributor interface. 96 * The number of interfaces should be equal to the number of CPUs in the 97 * system. The memory for saving these addresses has to be allocated by 98 * the platform port 99 */ 100 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 101 plat_driver_data->rdistif_num, 102 plat_driver_data->gicr_base, 103 plat_driver_data->mpidr_to_core_pos); 104 105 driver_data = plat_driver_data; 106 107 INFO("GICv3 %s legacy support detected." 108 " ARM GICV3 driver initialized in EL3\n", 109 gicv2_compat ? "with" : "without"); 110 } 111 112 /******************************************************************************* 113 * This function initialises the GIC distributor interface based upon the data 114 * provided by the platform while initialising the driver. 115 ******************************************************************************/ 116 void gicv3_distif_init(void) 117 { 118 assert(driver_data); 119 assert(driver_data->gicd_base); 120 assert(driver_data->g1s_interrupt_array); 121 assert(driver_data->g0_interrupt_array); 122 123 assert(IS_IN_EL3()); 124 125 /* 126 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 127 * the ARE_S bit. The Distributor might generate a system error 128 * otherwise. 129 */ 130 gicd_clr_ctlr(driver_data->gicd_base, 131 CTLR_ENABLE_G0_BIT | 132 CTLR_ENABLE_G1S_BIT | 133 CTLR_ENABLE_G1NS_BIT, 134 RWP_TRUE); 135 136 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 137 gicd_set_ctlr(driver_data->gicd_base, 138 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 139 140 /* Set the default attribute of all SPIs */ 141 gicv3_spis_configure_defaults(driver_data->gicd_base); 142 143 /* Configure the G1S SPIs */ 144 gicv3_secure_spis_configure(driver_data->gicd_base, 145 driver_data->g1s_interrupt_num, 146 driver_data->g1s_interrupt_array, 147 INTR_GROUP1S); 148 149 /* Configure the G0 SPIs */ 150 gicv3_secure_spis_configure(driver_data->gicd_base, 151 driver_data->g0_interrupt_num, 152 driver_data->g0_interrupt_array, 153 INTR_GROUP0); 154 155 /* Enable the secure SPIs now that they have been configured */ 156 gicd_set_ctlr(driver_data->gicd_base, 157 CTLR_ENABLE_G1S_BIT | CTLR_ENABLE_G0_BIT, 158 RWP_TRUE); 159 } 160 161 /******************************************************************************* 162 * This function initialises the GIC Redistributor interface of the calling CPU 163 * (identified by the 'proc_num' parameter) based upon the data provided by the 164 * platform while initialising the driver. 165 ******************************************************************************/ 166 void gicv3_rdistif_init(unsigned int proc_num) 167 { 168 uintptr_t gicr_base; 169 170 assert(driver_data); 171 assert(proc_num < driver_data->rdistif_num); 172 assert(driver_data->rdistif_base_addrs); 173 assert(driver_data->gicd_base); 174 assert(gicd_read_ctlr(driver_data->gicd_base) & CTLR_ARE_S_BIT); 175 assert(driver_data->g1s_interrupt_array); 176 assert(driver_data->g0_interrupt_array); 177 178 assert(IS_IN_EL3()); 179 180 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 181 182 /* Set the default attribute of all SGIs and PPIs */ 183 gicv3_ppi_sgi_configure_defaults(gicr_base); 184 185 /* Configure the G1S SGIs/PPIs */ 186 gicv3_secure_ppi_sgi_configure(gicr_base, 187 driver_data->g1s_interrupt_num, 188 driver_data->g1s_interrupt_array, 189 INTR_GROUP1S); 190 191 /* Configure the G0 SGIs/PPIs */ 192 gicv3_secure_ppi_sgi_configure(gicr_base, 193 driver_data->g0_interrupt_num, 194 driver_data->g0_interrupt_array, 195 INTR_GROUP0); 196 } 197 198 /******************************************************************************* 199 * This function enables the GIC CPU interface of the calling CPU using only 200 * system register accesses. 201 ******************************************************************************/ 202 void gicv3_cpuif_enable(unsigned int proc_num) 203 { 204 uintptr_t gicr_base; 205 unsigned int scr_el3; 206 unsigned int icc_sre_el3; 207 208 assert(driver_data); 209 assert(proc_num < driver_data->rdistif_num); 210 assert(driver_data->rdistif_base_addrs); 211 assert(IS_IN_EL3()); 212 213 /* Mark the connected core as awake */ 214 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 215 gicv3_rdistif_mark_core_awake(gicr_base); 216 217 /* Disable the legacy interrupt bypass */ 218 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 219 220 /* 221 * Enable system register access for EL3 and allow lower exception 222 * levels to configure the same for themselves. If the legacy mode is 223 * not supported, the SRE bit is RAO/WI 224 */ 225 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 226 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 227 228 scr_el3 = read_scr_el3(); 229 230 /* 231 * Switch to NS state to write Non secure ICC_SRE_EL1 and 232 * ICC_SRE_EL2 registers. 233 */ 234 write_scr_el3(scr_el3 | SCR_NS_BIT); 235 isb(); 236 237 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 238 write_icc_sre_el1(ICC_SRE_SRE_BIT); 239 isb(); 240 241 /* Switch to secure state. */ 242 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 243 isb(); 244 245 /* Program the idle priority in the PMR */ 246 write_icc_pmr_el1(GIC_PRI_MASK); 247 248 /* Enable Group0 interrupts */ 249 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 250 251 /* Enable Group1 Secure interrupts */ 252 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 253 IGRPEN1_EL3_ENABLE_G1S_BIT); 254 255 /* Write the secure ICC_SRE_EL1 register */ 256 write_icc_sre_el1(ICC_SRE_SRE_BIT); 257 isb(); 258 } 259 260 /******************************************************************************* 261 * This function disables the GIC CPU interface of the calling CPU using 262 * only system register accesses. 263 ******************************************************************************/ 264 void gicv3_cpuif_disable(unsigned int proc_num) 265 { 266 uintptr_t gicr_base; 267 268 assert(driver_data); 269 assert(proc_num < driver_data->rdistif_num); 270 assert(driver_data->rdistif_base_addrs); 271 272 assert(IS_IN_EL3()); 273 274 /* Disable legacy interrupt bypass */ 275 write_icc_sre_el3(read_icc_sre_el3() | 276 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 277 278 /* Disable Group0 interrupts */ 279 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 280 ~IGRPEN1_EL1_ENABLE_G0_BIT); 281 282 /* Disable Group1 Secure interrupts */ 283 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 284 ~IGRPEN1_EL3_ENABLE_G1S_BIT); 285 286 /* Synchronise accesses to group enable registers */ 287 isb(); 288 289 /* Mark the connected core as asleep */ 290 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 291 gicv3_rdistif_mark_core_asleep(gicr_base); 292 } 293 294 /******************************************************************************* 295 * This function returns the id of the highest priority pending interrupt at 296 * the GIC cpu interface. 297 ******************************************************************************/ 298 unsigned int gicv3_get_pending_interrupt_id(void) 299 { 300 unsigned int id; 301 302 assert(IS_IN_EL3()); 303 id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 304 305 /* 306 * If the ID is special identifier corresponding to G1S or G1NS 307 * interrupt, then read the highest pending group 1 interrupt. 308 */ 309 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) 310 return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 311 312 return id; 313 } 314 315 /******************************************************************************* 316 * This function returns the type of the highest priority pending interrupt at 317 * the GIC cpu interface. The return values can be one of the following : 318 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 319 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 320 * 0 - 1019 : The interrupt type is secure Group 0. 321 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 322 * sufficient priority to be signaled 323 ******************************************************************************/ 324 unsigned int gicv3_get_pending_interrupt_type(void) 325 { 326 assert(IS_IN_EL3()); 327 return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 328 } 329 330 /******************************************************************************* 331 * This function returns the type of the interrupt id depending upon the group 332 * this interrupt has been configured under by the interrupt controller i.e. 333 * group0 or group1 Secure / Non Secure. The return value can be one of the 334 * following : 335 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 336 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 337 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 338 * interrupt. 339 ******************************************************************************/ 340 unsigned int gicv3_get_interrupt_type(unsigned int id, 341 unsigned int proc_num) 342 { 343 unsigned int igroup, grpmodr; 344 uintptr_t gicr_base; 345 346 assert(IS_IN_EL3()); 347 assert(driver_data); 348 349 /* Ensure the parameters are valid */ 350 assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID); 351 assert(proc_num < driver_data->rdistif_num); 352 353 /* All LPI interrupts are Group 1 non secure */ 354 if (id >= MIN_LPI_ID) 355 return INTR_GROUP1NS; 356 357 if (id < MIN_SPI_ID) { 358 assert(driver_data->rdistif_base_addrs); 359 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 360 igroup = gicr_get_igroupr0(gicr_base, id); 361 grpmodr = gicr_get_igrpmodr0(gicr_base, id); 362 } else { 363 assert(driver_data->gicd_base); 364 igroup = gicd_get_igroupr(driver_data->gicd_base, id); 365 grpmodr = gicd_get_igrpmodr(driver_data->gicd_base, id); 366 } 367 368 /* 369 * If the IGROUP bit is set, then it is a Group 1 Non secure 370 * interrupt 371 */ 372 if (igroup) 373 return INTR_GROUP1NS; 374 375 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 376 if (grpmodr) 377 return INTR_GROUP1S; 378 379 /* Else it is a Group 0 Secure interrupt */ 380 return INTR_GROUP0; 381 } 382