1 /* 2 * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <common/interrupt_props.h> 14 #include <drivers/arm/gic600_multichip.h> 15 #include <drivers/arm/gicv3.h> 16 #include <lib/spinlock.h> 17 #include <plat/common/platform.h> 18 19 #include "gicv3_private.h" 20 21 const gicv3_driver_data_t *gicv3_driver_data; 22 23 /* 24 * Spinlock to guard registers needing read-modify-write. APIs protected by this 25 * spinlock are used either at boot time (when only a single CPU is active), or 26 * when the system is fully coherent. 27 */ 28 static spinlock_t gic_lock; 29 30 /* 31 * Redistributor power operations are weakly bound so that they can be 32 * overridden 33 */ 34 #pragma weak gicv3_rdistif_off 35 #pragma weak gicv3_rdistif_on 36 37 /* Check interrupt ID for SGI/(E)PPI and (E)SPIs */ 38 static bool is_sgi_ppi(unsigned int id); 39 40 /* 41 * Helper macros to save and restore GICR and GICD registers 42 * corresponding to their numbers to and from the context 43 */ 44 #define RESTORE_GICR_REG(base, ctx, name, i) \ 45 gicr_write_##name((base), (i), (ctx)->gicr_##name[(i)]) 46 47 #define SAVE_GICR_REG(base, ctx, name, i) \ 48 (ctx)->gicr_##name[(i)] = gicr_read_##name((base), (i)) 49 50 /* Helper macros to save and restore GICD registers to and from the context */ 51 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 52 do { \ 53 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 54 int_id += (1U << REG##R_SHIFT)) { \ 55 gicd_write_##reg((base), int_id, \ 56 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 57 REG##R_SHIFT]); \ 58 } \ 59 } while (false) 60 61 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 62 do { \ 63 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 64 int_id += (1U << REG##R_SHIFT)) { \ 65 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 66 REG##R_SHIFT] = gicd_read_##reg((base), int_id); \ 67 } \ 68 } while (false) 69 70 #if GIC_EXT_INTID 71 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 72 do { \ 73 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 74 int_id += (1U << REG##R_SHIFT)) { \ 75 gicd_write_##reg((base), int_id, \ 76 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ 77 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ 78 >> REG##R_SHIFT]); \ 79 } \ 80 } while (false) 81 82 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 83 do { \ 84 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 85 int_id += (1U << REG##R_SHIFT)) { \ 86 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ 87 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ 88 >> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\ 89 } \ 90 } while (false) 91 #else 92 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) 93 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) 94 #endif /* GIC_EXT_INTID */ 95 96 /******************************************************************************* 97 * This function initialises the ARM GICv3 driver in EL3 with provided platform 98 * inputs. 99 ******************************************************************************/ 100 void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 101 { 102 unsigned int gic_version; 103 unsigned int gicv2_compat; 104 105 assert(plat_driver_data != NULL); 106 assert(plat_driver_data->gicd_base != 0U); 107 assert(plat_driver_data->rdistif_num != 0U); 108 assert(plat_driver_data->rdistif_base_addrs != NULL); 109 110 assert(IS_IN_EL3()); 111 112 assert((plat_driver_data->interrupt_props_num != 0U) ? 113 (plat_driver_data->interrupt_props != NULL) : 1); 114 115 /* Check for system register support */ 116 #ifndef __aarch64__ 117 assert((read_id_pfr1() & 118 (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); 119 #else 120 assert((read_id_aa64pfr0_el1() & 121 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U); 122 #endif /* !__aarch64__ */ 123 124 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 125 gic_version >>= PIDR2_ARCH_REV_SHIFT; 126 gic_version &= PIDR2_ARCH_REV_MASK; 127 128 /* Check GIC version */ 129 #if !GIC_ENABLE_V4_EXTN 130 assert(gic_version == ARCH_REV_GICV3); 131 #endif 132 /* 133 * Find out whether the GIC supports the GICv2 compatibility mode. 134 * The ARE_S bit resets to 0 if supported 135 */ 136 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 137 gicv2_compat >>= CTLR_ARE_S_SHIFT; 138 gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK; 139 140 if (plat_driver_data->gicr_base != 0U) { 141 /* 142 * Find the base address of each implemented Redistributor interface. 143 * The number of interfaces should be equal to the number of CPUs in the 144 * system. The memory for saving these addresses has to be allocated by 145 * the platform port 146 */ 147 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 148 plat_driver_data->rdistif_num, 149 plat_driver_data->gicr_base, 150 plat_driver_data->mpidr_to_core_pos); 151 #if !HW_ASSISTED_COHERENCY 152 /* 153 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 154 */ 155 flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs), 156 plat_driver_data->rdistif_num * 157 sizeof(*(plat_driver_data->rdistif_base_addrs))); 158 #endif 159 } 160 gicv3_driver_data = plat_driver_data; 161 162 /* 163 * The GIC driver data is initialized by the primary CPU with caches 164 * enabled. When the secondary CPU boots up, it initializes the 165 * GICC/GICR interface with the caches disabled. Hence flush the 166 * driver data to ensure coherency. This is not required if the 167 * platform has HW_ASSISTED_COHERENCY enabled. 168 */ 169 #if !HW_ASSISTED_COHERENCY 170 flush_dcache_range((uintptr_t)&gicv3_driver_data, 171 sizeof(gicv3_driver_data)); 172 flush_dcache_range((uintptr_t)gicv3_driver_data, 173 sizeof(*gicv3_driver_data)); 174 #endif 175 gicv3_check_erratas_applies(plat_driver_data->gicd_base); 176 177 INFO("GICv%u with%s legacy support detected.\n", gic_version, 178 (gicv2_compat == 0U) ? "" : "out"); 179 INFO("ARM GICv%u driver initialized in EL3\n", gic_version); 180 } 181 182 /******************************************************************************* 183 * This function initialises the GIC distributor interface based upon the data 184 * provided by the platform while initialising the driver. 185 ******************************************************************************/ 186 void __init gicv3_distif_init(void) 187 { 188 unsigned int bitmap; 189 190 assert(gicv3_driver_data != NULL); 191 assert(gicv3_driver_data->gicd_base != 0U); 192 193 assert(IS_IN_EL3()); 194 195 /* 196 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 197 * the ARE_S bit. The Distributor might generate a system error 198 * otherwise. 199 */ 200 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 201 CTLR_ENABLE_G0_BIT | 202 CTLR_ENABLE_G1S_BIT | 203 CTLR_ENABLE_G1NS_BIT, 204 RWP_TRUE); 205 206 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 207 gicd_set_ctlr(gicv3_driver_data->gicd_base, 208 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 209 210 /* Set the default attribute of all (E)SPIs */ 211 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); 212 213 bitmap = gicv3_secure_spis_config_props( 214 gicv3_driver_data->gicd_base, 215 gicv3_driver_data->interrupt_props, 216 gicv3_driver_data->interrupt_props_num); 217 218 /* Enable the secure (E)SPIs now that they have been configured */ 219 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 220 } 221 222 /******************************************************************************* 223 * This function initialises the GIC Redistributor interface of the calling CPU 224 * (identified by the 'proc_num' parameter) based upon the data provided by the 225 * platform while initialising the driver. 226 ******************************************************************************/ 227 void gicv3_rdistif_init(unsigned int proc_num) 228 { 229 uintptr_t gicr_base; 230 unsigned int bitmap; 231 uint32_t ctlr; 232 233 assert(gicv3_driver_data != NULL); 234 assert(proc_num < gicv3_driver_data->rdistif_num); 235 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 236 assert(gicv3_driver_data->gicd_base != 0U); 237 238 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base); 239 assert((ctlr & CTLR_ARE_S_BIT) != 0U); 240 241 assert(IS_IN_EL3()); 242 243 /* Power on redistributor */ 244 gicv3_rdistif_on(proc_num); 245 246 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 247 assert(gicr_base != 0U); 248 249 /* Set the default attribute of all SGIs and (E)PPIs */ 250 gicv3_ppi_sgi_config_defaults(gicr_base); 251 252 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, 253 gicv3_driver_data->interrupt_props, 254 gicv3_driver_data->interrupt_props_num); 255 256 /* Enable interrupt groups as required, if not already */ 257 if ((ctlr & bitmap) != bitmap) { 258 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 259 } 260 } 261 262 /******************************************************************************* 263 * Functions to perform power operations on GIC Redistributor 264 ******************************************************************************/ 265 void gicv3_rdistif_off(unsigned int proc_num) 266 { 267 } 268 269 void gicv3_rdistif_on(unsigned int proc_num) 270 { 271 } 272 273 /******************************************************************************* 274 * This function enables the GIC CPU interface of the calling CPU using only 275 * system register accesses. 276 ******************************************************************************/ 277 void gicv3_cpuif_enable(unsigned int proc_num) 278 { 279 uintptr_t gicr_base; 280 u_register_t scr_el3; 281 unsigned int icc_sre_el3; 282 283 assert(gicv3_driver_data != NULL); 284 assert(proc_num < gicv3_driver_data->rdistif_num); 285 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 286 assert(IS_IN_EL3()); 287 288 /* Mark the connected core as awake */ 289 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 290 gicv3_rdistif_mark_core_awake(gicr_base); 291 292 /* Disable the legacy interrupt bypass */ 293 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 294 295 /* 296 * Enable system register access for EL3 and allow lower exception 297 * levels to configure the same for themselves. If the legacy mode is 298 * not supported, the SRE bit is RAO/WI 299 */ 300 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 301 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 302 303 scr_el3 = read_scr_el3(); 304 305 /* 306 * Switch to NS state to write Non secure ICC_SRE_EL1 and 307 * ICC_SRE_EL2 registers. 308 */ 309 write_scr_el3(scr_el3 | SCR_NS_BIT); 310 isb(); 311 312 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 313 write_icc_sre_el1(ICC_SRE_SRE_BIT); 314 isb(); 315 316 /* Switch to secure state. */ 317 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 318 isb(); 319 320 /* Write the secure ICC_SRE_EL1 register */ 321 write_icc_sre_el1(ICC_SRE_SRE_BIT); 322 isb(); 323 324 /* Program the idle priority in the PMR */ 325 write_icc_pmr_el1(GIC_PRI_MASK); 326 327 /* Enable Group0 interrupts */ 328 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 329 330 /* Enable Group1 Secure interrupts */ 331 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 332 IGRPEN1_EL3_ENABLE_G1S_BIT); 333 /* and restore the original */ 334 write_scr_el3(scr_el3); 335 isb(); 336 /* Add DSB to ensure visibility of System register writes */ 337 dsb(); 338 } 339 340 /******************************************************************************* 341 * This function disables the GIC CPU interface of the calling CPU using 342 * only system register accesses. 343 ******************************************************************************/ 344 void gicv3_cpuif_disable(unsigned int proc_num) 345 { 346 uintptr_t gicr_base; 347 348 assert(gicv3_driver_data != NULL); 349 assert(proc_num < gicv3_driver_data->rdistif_num); 350 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 351 352 assert(IS_IN_EL3()); 353 354 /* Disable legacy interrupt bypass */ 355 write_icc_sre_el3(read_icc_sre_el3() | 356 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 357 358 /* Disable Group0 interrupts */ 359 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 360 ~IGRPEN1_EL1_ENABLE_G0_BIT); 361 362 /* Disable Group1 Secure and Non-Secure interrupts */ 363 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 364 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 365 IGRPEN1_EL3_ENABLE_G1S_BIT)); 366 367 /* Synchronise accesses to group enable registers */ 368 isb(); 369 /* Add DSB to ensure visibility of System register writes */ 370 dsb(); 371 372 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 373 assert(gicr_base != 0UL); 374 375 /* 376 * dsb() already issued previously after clearing the CPU group 377 * enabled, apply below workaround to toggle the "DPG*" 378 * bits of GICR_CTLR register for unblocking event. 379 */ 380 gicv3_apply_errata_wa_2384374(gicr_base); 381 382 /* Mark the connected core as asleep */ 383 gicv3_rdistif_mark_core_asleep(gicr_base); 384 } 385 386 /******************************************************************************* 387 * This function returns the id of the highest priority pending interrupt at 388 * the GIC cpu interface. 389 ******************************************************************************/ 390 unsigned int gicv3_get_pending_interrupt_id(void) 391 { 392 unsigned int id; 393 394 assert(IS_IN_EL3()); 395 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 396 397 /* 398 * If the ID is special identifier corresponding to G1S or G1NS 399 * interrupt, then read the highest pending group 1 interrupt. 400 */ 401 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) { 402 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 403 } 404 405 return id; 406 } 407 408 /******************************************************************************* 409 * This function returns the type of the highest priority pending interrupt at 410 * the GIC cpu interface. The return values can be one of the following : 411 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 412 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 413 * 0 - 1019 : The interrupt type is secure Group 0. 414 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 415 * sufficient priority to be signaled 416 ******************************************************************************/ 417 unsigned int gicv3_get_pending_interrupt_type(void) 418 { 419 assert(IS_IN_EL3()); 420 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 421 } 422 423 /******************************************************************************* 424 * This function returns the type of the interrupt id depending upon the group 425 * this interrupt has been configured under by the interrupt controller i.e. 426 * group0 or group1 Secure / Non Secure. The return value can be one of the 427 * following : 428 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 429 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 430 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 431 * interrupt. 432 ******************************************************************************/ 433 unsigned int gicv3_get_interrupt_type(unsigned int id, unsigned int proc_num) 434 { 435 unsigned int igroup, grpmodr; 436 uintptr_t gicr_base; 437 uintptr_t gicd_base; 438 439 assert(IS_IN_EL3()); 440 assert(gicv3_driver_data != NULL); 441 442 /* Ensure the parameters are valid */ 443 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID)); 444 assert(proc_num < gicv3_driver_data->rdistif_num); 445 446 /* All LPI interrupts are Group 1 non secure */ 447 if (id >= MIN_LPI_ID) { 448 return INTR_GROUP1NS; 449 } 450 451 /* Check interrupt ID */ 452 if (is_sgi_ppi(id)) { 453 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 454 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 455 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 456 igroup = gicr_get_igroupr(gicr_base, id); 457 grpmodr = gicr_get_igrpmodr(gicr_base, id); 458 } else { 459 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 460 assert(gicv3_driver_data->gicd_base != 0U); 461 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 462 igroup = gicd_get_igroupr(gicd_base, id); 463 grpmodr = gicd_get_igrpmodr(gicd_base, id); 464 } 465 466 /* 467 * If the IGROUP bit is set, then it is a Group 1 Non secure 468 * interrupt 469 */ 470 if (igroup != 0U) { 471 return INTR_GROUP1NS; 472 } 473 474 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 475 if (grpmodr != 0U) { 476 return INTR_GROUP1S; 477 } 478 479 /* Else it is a Group 0 Secure interrupt */ 480 return INTR_GROUP0; 481 } 482 483 /***************************************************************************** 484 * Function to save and disable the GIC ITS register context. The power 485 * management of GIC ITS is implementation-defined and this function doesn't 486 * save any memory structures required to support ITS. As the sequence to save 487 * this state is implementation defined, it should be executed in platform 488 * specific code. Calling this function alone and then powering down the GIC and 489 * ITS without implementing the aforementioned platform specific code will 490 * corrupt the ITS state. 491 * 492 * This function must be invoked after the GIC CPU interface is disabled. 493 *****************************************************************************/ 494 void gicv3_its_save_disable(uintptr_t gits_base, 495 gicv3_its_ctx_t * const its_ctx) 496 { 497 unsigned int i; 498 499 assert(gicv3_driver_data != NULL); 500 assert(IS_IN_EL3()); 501 assert(its_ctx != NULL); 502 assert(gits_base != 0U); 503 504 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 505 506 /* Disable the ITS */ 507 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 508 509 /* Wait for quiescent state */ 510 gits_wait_for_quiescent_bit(gits_base); 511 512 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 513 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 514 515 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 516 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 517 } 518 } 519 520 /***************************************************************************** 521 * Function to restore the GIC ITS register context. The power 522 * management of GIC ITS is implementation defined and this function doesn't 523 * restore any memory structures required to support ITS. The assumption is 524 * that these structures are in memory and are retained during system suspend. 525 * 526 * This must be invoked before the GIC CPU interface is enabled. 527 *****************************************************************************/ 528 void gicv3_its_restore(uintptr_t gits_base, 529 const gicv3_its_ctx_t * const its_ctx) 530 { 531 unsigned int i; 532 533 assert(gicv3_driver_data != NULL); 534 assert(IS_IN_EL3()); 535 assert(its_ctx != NULL); 536 assert(gits_base != 0U); 537 538 /* Assert that the GITS is disabled and quiescent */ 539 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 540 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U); 541 542 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 543 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 544 545 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 546 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 547 } 548 549 /* Restore the ITS CTLR but leave the ITS disabled */ 550 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 551 } 552 553 /***************************************************************************** 554 * Function to save the GIC Redistributor register context. This function 555 * must be invoked after CPU interface disable and prior to Distributor save. 556 *****************************************************************************/ 557 void gicv3_rdistif_save(unsigned int proc_num, 558 gicv3_redist_ctx_t * const rdist_ctx) 559 { 560 uintptr_t gicr_base; 561 unsigned int i, ppi_regs_num, regs_num; 562 563 assert(gicv3_driver_data != NULL); 564 assert(proc_num < gicv3_driver_data->rdistif_num); 565 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 566 assert(IS_IN_EL3()); 567 assert(rdist_ctx != NULL); 568 569 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 570 571 #if GIC_EXT_INTID 572 /* Calculate number of PPI registers */ 573 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 574 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 575 /* All other values except PPInum [0-2] are reserved */ 576 if (ppi_regs_num > 3U) { 577 ppi_regs_num = 1U; 578 } 579 #else 580 ppi_regs_num = 1U; 581 #endif 582 /* 583 * Wait for any write to GICR_CTLR to complete before trying to save any 584 * state. 585 */ 586 gicr_wait_for_pending_write(gicr_base); 587 588 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 589 590 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 591 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 592 593 /* 32 interrupt IDs per register */ 594 for (i = 0U; i < ppi_regs_num; ++i) { 595 SAVE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 596 SAVE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 597 SAVE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 598 SAVE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 599 SAVE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 600 } 601 602 /* 16 interrupt IDs per GICR_ICFGR register */ 603 regs_num = ppi_regs_num << 1; 604 for (i = 0U; i < regs_num; ++i) { 605 SAVE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 606 } 607 608 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 609 610 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 611 regs_num = ppi_regs_num << 3; 612 for (i = 0U; i < regs_num; ++i) { 613 rdist_ctx->gicr_ipriorityr[i] = 614 gicr_ipriorityr_read(gicr_base, i); 615 } 616 617 /* 618 * Call the pre-save hook that implements the IMP DEF sequence that may 619 * be required on some GIC implementations. As this may need to access 620 * the Redistributor registers, we pass it proc_num. 621 */ 622 gicv3_distif_pre_save(proc_num); 623 } 624 625 /***************************************************************************** 626 * Function to restore the GIC Redistributor register context. We disable 627 * LPI and per-cpu interrupts before we start restore of the Redistributor. 628 * This function must be invoked after Distributor restore but prior to 629 * CPU interface enable. The pending and active interrupts are restored 630 * after the interrupts are fully configured and enabled. 631 *****************************************************************************/ 632 void gicv3_rdistif_init_restore(unsigned int proc_num, 633 const gicv3_redist_ctx_t * const rdist_ctx) 634 { 635 uintptr_t gicr_base; 636 unsigned int i, ppi_regs_num, regs_num; 637 638 assert(gicv3_driver_data != NULL); 639 assert(proc_num < gicv3_driver_data->rdistif_num); 640 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 641 assert(IS_IN_EL3()); 642 assert(rdist_ctx != NULL); 643 644 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 645 646 #if GIC_EXT_INTID 647 /* Calculate number of PPI registers */ 648 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 649 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 650 /* All other values except PPInum [0-2] are reserved */ 651 if (ppi_regs_num > 3U) { 652 ppi_regs_num = 1U; 653 } 654 #else 655 ppi_regs_num = 1U; 656 #endif 657 /* Power on redistributor */ 658 gicv3_rdistif_on(proc_num); 659 660 /* 661 * Call the post-restore hook that implements the IMP DEF sequence that 662 * may be required on some GIC implementations. As this may need to 663 * access the Redistributor registers, we pass it proc_num. 664 */ 665 gicv3_distif_post_restore(proc_num); 666 667 /* 668 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 669 * This is a more scalable approach as it avoids clearing the enable 670 * bits in the GICD_CTLR. 671 */ 672 for (i = 0U; i < ppi_regs_num; ++i) { 673 gicr_write_icenabler(gicr_base, i, ~0U); 674 } 675 676 /* Wait for pending writes to GICR_ICENABLER */ 677 gicr_wait_for_pending_write(gicr_base); 678 679 /* 680 * Disable the LPIs to avoid unpredictable behavior when writing to 681 * GICR_PROPBASER and GICR_PENDBASER. 682 */ 683 gicr_write_ctlr(gicr_base, 684 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 685 686 /* Restore registers' content */ 687 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 688 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 689 690 /* 32 interrupt IDs per register */ 691 for (i = 0U; i < ppi_regs_num; ++i) { 692 RESTORE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 693 RESTORE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 694 } 695 696 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 697 regs_num = ppi_regs_num << 3; 698 for (i = 0U; i < regs_num; ++i) { 699 gicr_ipriorityr_write(gicr_base, i, 700 rdist_ctx->gicr_ipriorityr[i]); 701 } 702 703 /* 16 interrupt IDs per GICR_ICFGR register */ 704 regs_num = ppi_regs_num << 1; 705 for (i = 0U; i < regs_num; ++i) { 706 RESTORE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 707 } 708 709 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 710 711 /* Restore after group and priorities are set. 712 * 32 interrupt IDs per register 713 */ 714 for (i = 0U; i < ppi_regs_num; ++i) { 715 RESTORE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 716 RESTORE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 717 } 718 719 /* 720 * Wait for all writes to the Distributor to complete before enabling 721 * the SGI and (E)PPIs. 722 */ 723 gicr_wait_for_upstream_pending_write(gicr_base); 724 725 /* 32 interrupt IDs per GICR_ISENABLER register */ 726 for (i = 0U; i < ppi_regs_num; ++i) { 727 RESTORE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 728 } 729 730 /* 731 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 732 * the first write to GICR_CTLR was still in flight (this write only 733 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 734 * bit). 735 */ 736 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 737 gicr_wait_for_pending_write(gicr_base); 738 } 739 740 /***************************************************************************** 741 * Function to save the GIC Distributor register context. This function 742 * must be invoked after CPU interface disable and Redistributor save. 743 *****************************************************************************/ 744 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 745 { 746 assert(gicv3_driver_data != NULL); 747 assert(gicv3_driver_data->gicd_base != 0U); 748 assert(IS_IN_EL3()); 749 assert(dist_ctx != NULL); 750 751 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 752 unsigned int num_ints = gicv3_get_spi_limit(gicd_base); 753 #if GIC_EXT_INTID 754 unsigned int num_eints = gicv3_get_espi_limit(gicd_base); 755 #endif 756 757 /* Wait for pending write to complete */ 758 gicd_wait_for_pending_write(gicd_base); 759 760 /* Save the GICD_CTLR */ 761 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 762 763 /* Save GICD_IGROUPR for INTIDs 32 - 1019 */ 764 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 765 766 /* Save GICD_IGROUPRE for INTIDs 4096 - 5119 */ 767 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 768 769 /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */ 770 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 771 772 /* Save GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 773 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 774 775 /* Save GICD_ISPENDR for INTIDs 32 - 1019 */ 776 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 777 778 /* Save GICD_ISPENDRE for INTIDs 4096 - 5119 */ 779 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 780 781 /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */ 782 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 783 784 /* Save GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 785 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 786 787 /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */ 788 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 789 790 /* Save GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 791 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 792 793 /* Save GICD_ICFGR for INTIDs 32 - 1019 */ 794 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 795 796 /* Save GICD_ICFGRE for INTIDs 4096 - 5119 */ 797 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 798 799 /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */ 800 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 801 802 /* Save GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 803 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 804 805 /* Save GICD_NSACR for INTIDs 32 - 1019 */ 806 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 807 808 /* Save GICD_NSACRE for INTIDs 4096 - 5119 */ 809 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 810 811 /* Save GICD_IROUTER for INTIDs 32 - 1019 */ 812 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 813 814 /* Save GICD_IROUTERE for INTIDs 4096 - 5119 */ 815 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 816 817 /* 818 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 819 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 820 * driver. 821 */ 822 } 823 824 /***************************************************************************** 825 * Function to restore the GIC Distributor register context. We disable G0, G1S 826 * and G1NS interrupt groups before we start restore of the Distributor. This 827 * function must be invoked prior to Redistributor restore and CPU interface 828 * enable. The pending and active interrupts are restored after the interrupts 829 * are fully configured and enabled. 830 *****************************************************************************/ 831 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 832 { 833 assert(gicv3_driver_data != NULL); 834 assert(gicv3_driver_data->gicd_base != 0U); 835 assert(IS_IN_EL3()); 836 assert(dist_ctx != NULL); 837 838 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 839 840 /* 841 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 842 * the ARE_S bit. The Distributor might generate a system error 843 * otherwise. 844 */ 845 gicd_clr_ctlr(gicd_base, 846 CTLR_ENABLE_G0_BIT | 847 CTLR_ENABLE_G1S_BIT | 848 CTLR_ENABLE_G1NS_BIT, 849 RWP_TRUE); 850 851 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 852 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 853 854 unsigned int num_ints = gicv3_get_spi_limit(gicd_base); 855 #if GIC_EXT_INTID 856 unsigned int num_eints = gicv3_get_espi_limit(gicd_base); 857 #endif 858 /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */ 859 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 860 861 /* Restore GICD_IGROUPRE for INTIDs 4096 - 5119 */ 862 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 863 864 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */ 865 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 866 867 /* Restore GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 868 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 869 870 /* Restore GICD_ICFGR for INTIDs 32 - 1019 */ 871 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 872 873 /* Restore GICD_ICFGRE for INTIDs 4096 - 5119 */ 874 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 875 876 /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */ 877 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 878 879 /* Restore GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 880 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 881 882 /* Restore GICD_NSACR for INTIDs 32 - 1019 */ 883 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 884 885 /* Restore GICD_NSACRE for INTIDs 4096 - 5119 */ 886 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 887 888 /* Restore GICD_IROUTER for INTIDs 32 - 1019 */ 889 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 890 891 /* Restore GICD_IROUTERE for INTIDs 4096 - 5119 */ 892 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 893 894 /* 895 * Restore ISENABLER(E), ISPENDR(E) and ISACTIVER(E) after 896 * the interrupts are configured. 897 */ 898 899 /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */ 900 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 901 902 /* Restore GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 903 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 904 905 /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */ 906 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 907 908 /* Restore GICD_ISPENDRE for INTIDs 4096 - 5119 */ 909 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 910 911 /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */ 912 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 913 914 /* Restore GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 915 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 916 917 /* Restore the GICD_CTLR */ 918 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 919 gicd_wait_for_pending_write(gicd_base); 920 } 921 922 /******************************************************************************* 923 * This function gets the priority of the interrupt the processor is currently 924 * servicing. 925 ******************************************************************************/ 926 unsigned int gicv3_get_running_priority(void) 927 { 928 return (unsigned int)read_icc_rpr_el1(); 929 } 930 931 /******************************************************************************* 932 * This function checks if the interrupt identified by id is active (whether the 933 * state is either active, or active and pending). The proc_num is used if the 934 * interrupt is SGI or (E)PPI and programs the corresponding Redistributor 935 * interface. 936 ******************************************************************************/ 937 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) 938 { 939 uintptr_t gicd_base; 940 941 assert(gicv3_driver_data != NULL); 942 assert(gicv3_driver_data->gicd_base != 0U); 943 assert(proc_num < gicv3_driver_data->rdistif_num); 944 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 945 946 /* Check interrupt ID */ 947 if (is_sgi_ppi(id)) { 948 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 949 return gicr_get_isactiver( 950 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 951 } 952 953 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 954 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 955 return gicd_get_isactiver(gicd_base, id); 956 } 957 958 /******************************************************************************* 959 * This function enables the interrupt identified by id. The proc_num 960 * is used if the interrupt is SGI or PPI, and programs the corresponding 961 * Redistributor interface. 962 ******************************************************************************/ 963 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) 964 { 965 uintptr_t gicd_base; 966 967 assert(gicv3_driver_data != NULL); 968 assert(gicv3_driver_data->gicd_base != 0U); 969 assert(proc_num < gicv3_driver_data->rdistif_num); 970 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 971 972 /* 973 * Ensure that any shared variable updates depending on out of band 974 * interrupt trigger are observed before enabling interrupt. 975 */ 976 dsbishst(); 977 978 /* Check interrupt ID */ 979 if (is_sgi_ppi(id)) { 980 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 981 gicr_set_isenabler( 982 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 983 } else { 984 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 985 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 986 gicd_set_isenabler(gicd_base, id); 987 } 988 } 989 990 /******************************************************************************* 991 * This function disables the interrupt identified by id. The proc_num 992 * is used if the interrupt is SGI or PPI, and programs the corresponding 993 * Redistributor interface. 994 ******************************************************************************/ 995 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) 996 { 997 uintptr_t gicd_base; 998 999 assert(gicv3_driver_data != NULL); 1000 assert(gicv3_driver_data->gicd_base != 0U); 1001 assert(proc_num < gicv3_driver_data->rdistif_num); 1002 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1003 1004 /* 1005 * Disable interrupt, and ensure that any shared variable updates 1006 * depending on out of band interrupt trigger are observed afterwards. 1007 */ 1008 1009 /* Check interrupt ID */ 1010 if (is_sgi_ppi(id)) { 1011 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1012 gicr_set_icenabler( 1013 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1014 1015 /* Write to clear enable requires waiting for pending writes */ 1016 gicr_wait_for_pending_write( 1017 gicv3_driver_data->rdistif_base_addrs[proc_num]); 1018 } else { 1019 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1020 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1021 gicd_set_icenabler(gicd_base, id); 1022 1023 /* Write to clear enable requires waiting for pending writes */ 1024 gicd_wait_for_pending_write(gicd_base); 1025 } 1026 1027 dsbishst(); 1028 } 1029 1030 /******************************************************************************* 1031 * This function sets the interrupt priority as supplied for the given interrupt 1032 * id. 1033 ******************************************************************************/ 1034 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 1035 unsigned int priority) 1036 { 1037 uintptr_t gicr_base; 1038 uintptr_t gicd_base; 1039 1040 assert(gicv3_driver_data != NULL); 1041 assert(gicv3_driver_data->gicd_base != 0U); 1042 assert(proc_num < gicv3_driver_data->rdistif_num); 1043 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1044 1045 /* Check interrupt ID */ 1046 if (is_sgi_ppi(id)) { 1047 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1048 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1049 gicr_set_ipriorityr(gicr_base, id, priority); 1050 } else { 1051 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1052 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1053 gicd_set_ipriorityr(gicd_base, id, priority); 1054 } 1055 } 1056 1057 /******************************************************************************* 1058 * This function assigns group for the interrupt identified by id. The proc_num 1059 * is used if the interrupt is SGI or (E)PPI, and programs the corresponding 1060 * Redistributor interface. The group can be any of GICV3_INTR_GROUP* 1061 ******************************************************************************/ 1062 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 1063 unsigned int type) 1064 { 1065 bool igroup = false, grpmod = false; 1066 uintptr_t gicr_base; 1067 uintptr_t gicd_base; 1068 1069 assert(gicv3_driver_data != NULL); 1070 assert(gicv3_driver_data->gicd_base != 0U); 1071 assert(proc_num < gicv3_driver_data->rdistif_num); 1072 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1073 1074 switch (type) { 1075 case INTR_GROUP1S: 1076 igroup = false; 1077 grpmod = true; 1078 break; 1079 case INTR_GROUP0: 1080 igroup = false; 1081 grpmod = false; 1082 break; 1083 case INTR_GROUP1NS: 1084 igroup = true; 1085 grpmod = false; 1086 break; 1087 default: 1088 assert(false); 1089 break; 1090 } 1091 1092 /* Check interrupt ID */ 1093 if (is_sgi_ppi(id)) { 1094 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1095 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1096 1097 igroup ? gicr_set_igroupr(gicr_base, id) : 1098 gicr_clr_igroupr(gicr_base, id); 1099 grpmod ? gicr_set_igrpmodr(gicr_base, id) : 1100 gicr_clr_igrpmodr(gicr_base, id); 1101 } else { 1102 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1103 1104 /* Serialize read-modify-write to Distributor registers */ 1105 spin_lock(&gic_lock); 1106 1107 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1108 1109 igroup ? gicd_set_igroupr(gicd_base, id) : 1110 gicd_clr_igroupr(gicd_base, id); 1111 grpmod ? gicd_set_igrpmodr(gicd_base, id) : 1112 gicd_clr_igrpmodr(gicd_base, id); 1113 1114 spin_unlock(&gic_lock); 1115 } 1116 } 1117 1118 /******************************************************************************* 1119 * This function raises the specified SGI of the specified group. 1120 * 1121 * The target parameter must be a valid MPIDR in the system. 1122 ******************************************************************************/ 1123 void gicv3_raise_sgi(unsigned int sgi_num, gicv3_irq_group_t group, 1124 u_register_t target) 1125 { 1126 unsigned int tgt, aff3, aff2, aff1, aff0; 1127 uint64_t sgi_val; 1128 1129 /* Verify interrupt number is in the SGI range */ 1130 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID)); 1131 1132 /* Extract affinity fields from target */ 1133 aff0 = MPIDR_AFFLVL0_VAL(target); 1134 aff1 = MPIDR_AFFLVL1_VAL(target); 1135 aff2 = MPIDR_AFFLVL2_VAL(target); 1136 aff3 = MPIDR_AFFLVL3_VAL(target); 1137 1138 /* 1139 * Make target list from affinity 0, and ensure GICv3 SGI can target 1140 * this PE. 1141 */ 1142 assert(aff0 < GICV3_MAX_SGI_TARGETS); 1143 tgt = BIT_32(aff0); 1144 1145 /* Raise SGI to PE specified by its affinity */ 1146 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF, 1147 tgt); 1148 1149 /* 1150 * Ensure that any shared variable updates depending on out of band 1151 * interrupt trigger are observed before raising SGI. 1152 */ 1153 dsbishst(); 1154 1155 switch (group) { 1156 case GICV3_G0: 1157 write_icc_sgi0r_el1(sgi_val); 1158 break; 1159 case GICV3_G1NS: 1160 write_icc_asgi1r(sgi_val); 1161 break; 1162 case GICV3_G1S: 1163 write_icc_sgi1r(sgi_val); 1164 break; 1165 default: 1166 assert(false); 1167 break; 1168 } 1169 1170 isb(); 1171 } 1172 1173 /******************************************************************************* 1174 * This function sets the interrupt routing for the given (E)SPI interrupt id. 1175 * The interrupt routing is specified in routing mode and mpidr. 1176 * 1177 * The routing mode can be either of: 1178 * - GICV3_IRM_ANY 1179 * - GICV3_IRM_PE 1180 * 1181 * The mpidr is the affinity of the PE to which the interrupt will be routed, 1182 * and is ignored for routing mode GICV3_IRM_ANY. 1183 ******************************************************************************/ 1184 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr) 1185 { 1186 unsigned long long aff; 1187 uint64_t router; 1188 uintptr_t gicd_base; 1189 1190 assert(gicv3_driver_data != NULL); 1191 assert(gicv3_driver_data->gicd_base != 0U); 1192 1193 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE)); 1194 1195 assert(IS_SPI(id)); 1196 1197 aff = gicd_irouter_val_from_mpidr(mpidr, irm); 1198 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1199 gicd_write_irouter(gicd_base, id, aff); 1200 1201 /* 1202 * In implementations that do not require 1 of N distribution of SPIs, 1203 * IRM might be RAZ/WI. Read back and verify IRM bit. 1204 */ 1205 if (irm == GICV3_IRM_ANY) { 1206 router = gicd_read_irouter(gicd_base, id); 1207 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) { 1208 ERROR("GICv3 implementation doesn't support routing ANY\n"); 1209 panic(); 1210 } 1211 } 1212 } 1213 1214 /******************************************************************************* 1215 * This function clears the pending status of an interrupt identified by id. 1216 * The proc_num is used if the interrupt is SGI or (E)PPI, and programs the 1217 * corresponding Redistributor interface. 1218 ******************************************************************************/ 1219 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num) 1220 { 1221 uintptr_t gicd_base; 1222 1223 assert(gicv3_driver_data != NULL); 1224 assert(gicv3_driver_data->gicd_base != 0U); 1225 assert(proc_num < gicv3_driver_data->rdistif_num); 1226 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1227 1228 /* 1229 * Clear pending interrupt, and ensure that any shared variable updates 1230 * depending on out of band interrupt trigger are observed afterwards. 1231 */ 1232 1233 /* Check interrupt ID */ 1234 if (is_sgi_ppi(id)) { 1235 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1236 gicr_set_icpendr( 1237 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1238 } else { 1239 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1240 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1241 gicd_set_icpendr(gicd_base, id); 1242 } 1243 1244 dsbishst(); 1245 } 1246 1247 /******************************************************************************* 1248 * This function sets the pending status of an interrupt identified by id. 1249 * The proc_num is used if the interrupt is SGI or PPI and programs the 1250 * corresponding Redistributor interface. 1251 ******************************************************************************/ 1252 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num) 1253 { 1254 uintptr_t gicd_base; 1255 1256 assert(gicv3_driver_data != NULL); 1257 assert(gicv3_driver_data->gicd_base != 0U); 1258 assert(proc_num < gicv3_driver_data->rdistif_num); 1259 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1260 1261 /* 1262 * Ensure that any shared variable updates depending on out of band 1263 * interrupt trigger are observed before setting interrupt pending. 1264 */ 1265 dsbishst(); 1266 1267 /* Check interrupt ID */ 1268 if (is_sgi_ppi(id)) { 1269 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1270 gicr_set_ispendr( 1271 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1272 } else { 1273 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1274 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1275 gicd_set_ispendr(gicd_base, id); 1276 } 1277 } 1278 1279 /******************************************************************************* 1280 * This function sets the PMR register with the supplied value. Returns the 1281 * original PMR. 1282 ******************************************************************************/ 1283 unsigned int gicv3_set_pmr(unsigned int mask) 1284 { 1285 unsigned int old_mask; 1286 1287 old_mask = (unsigned int)read_icc_pmr_el1(); 1288 1289 /* 1290 * Order memory updates w.r.t. PMR write, and ensure they're visible 1291 * before potential out of band interrupt trigger because of PMR update. 1292 * PMR system register writes are self-synchronizing, so no ISB required 1293 * thereafter. 1294 */ 1295 dsbishst(); 1296 write_icc_pmr_el1(mask); 1297 1298 return old_mask; 1299 } 1300 1301 /******************************************************************************* 1302 * This function delegates the responsibility of discovering the corresponding 1303 * Redistributor frames to each CPU itself. It is a modified version of 1304 * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform 1305 * unlike the previous way in which only the Primary CPU did the discovery of 1306 * all the Redistributor frames for every CPU. It also handles the scenario in 1307 * which the frames of various CPUs are not contiguous in physical memory. 1308 ******************************************************************************/ 1309 int gicv3_rdistif_probe(const uintptr_t gicr_frame) 1310 { 1311 u_register_t mpidr, mpidr_self; 1312 unsigned int proc_num; 1313 uint64_t typer_val; 1314 uintptr_t rdistif_base; 1315 bool gicr_frame_found = false; 1316 1317 assert(gicv3_driver_data->gicr_base == 0U); 1318 1319 if (plat_can_cmo()) { 1320 /* Ensure this function is called with Data Cache enabled */ 1321 #ifndef __aarch64__ 1322 assert((read_sctlr() & SCTLR_C_BIT) != 0U); 1323 #else 1324 assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U); 1325 #endif /* !__aarch64__ */ 1326 } 1327 1328 mpidr_self = read_mpidr_el1() & MPIDR_AFFINITY_MASK; 1329 rdistif_base = gicr_frame; 1330 do { 1331 typer_val = gicr_read_typer(rdistif_base); 1332 mpidr = mpidr_from_gicr_typer(typer_val); 1333 if (gicv3_driver_data->mpidr_to_core_pos != NULL) { 1334 proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr); 1335 } else { 1336 proc_num = (unsigned int)(typer_val >> 1337 TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK; 1338 } 1339 if (mpidr == mpidr_self) { 1340 /* The base address doesn't need to be initialized on 1341 * every warm boot. 1342 */ 1343 if (gicv3_driver_data->rdistif_base_addrs[proc_num] 1344 != 0U) { 1345 return 0; 1346 } 1347 gicv3_driver_data->rdistif_base_addrs[proc_num] = 1348 rdistif_base; 1349 gicr_frame_found = true; 1350 break; 1351 } 1352 rdistif_base += gicv3_redist_size(typer_val); 1353 } while ((typer_val & TYPER_LAST_BIT) == 0U); 1354 1355 if (!gicr_frame_found) { 1356 return -1; 1357 } 1358 1359 /* 1360 * Flush the driver data to ensure coherency. This is 1361 * not required if platform has HW_ASSISTED_COHERENCY 1362 * enabled. 1363 */ 1364 #if !HW_ASSISTED_COHERENCY 1365 /* 1366 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 1367 */ 1368 flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]), 1369 sizeof(*(gicv3_driver_data->rdistif_base_addrs))); 1370 #endif 1371 return 0; /* Found matching GICR frame */ 1372 } 1373 1374 /****************************************************************************** 1375 * This function checks the interrupt ID and returns true for SGIs and (E)PPIs 1376 * and false for (E)SPIs IDs. 1377 *****************************************************************************/ 1378 static bool is_sgi_ppi(unsigned int id) 1379 { 1380 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 1381 if (IS_SGI_PPI(id)) { 1382 return true; 1383 } 1384 1385 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 1386 if (IS_SPI(id)) { 1387 return false; 1388 } 1389 1390 assert(false); 1391 panic(); 1392 } 1393