1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <debug.h> 35 #include <gic_common.h> 36 #include <gicv3.h> 37 #include "../common/gic_common_private.h" 38 #include "gicv3_private.h" 39 40 static const gicv3_driver_data_t *driver_data; 41 static unsigned int gicv2_compat; 42 43 /******************************************************************************* 44 * This function initialises the ARM GICv3 driver in EL3 with provided platform 45 * inputs. 46 ******************************************************************************/ 47 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 48 { 49 unsigned int gic_version; 50 51 assert(plat_driver_data); 52 assert(plat_driver_data->gicd_base); 53 assert(plat_driver_data->gicr_base); 54 assert(plat_driver_data->rdistif_num); 55 assert(plat_driver_data->rdistif_base_addrs); 56 57 assert(IS_IN_EL3()); 58 59 /* 60 * The platform should provide a list of at least one type of 61 * interrupts 62 */ 63 assert(plat_driver_data->g0_interrupt_array || 64 plat_driver_data->g1s_interrupt_array); 65 66 /* 67 * If there are no interrupts of a particular type, then the number of 68 * interrupts of that type should be 0 and vice-versa. 69 */ 70 assert(plat_driver_data->g0_interrupt_array ? 71 plat_driver_data->g0_interrupt_num : 72 plat_driver_data->g0_interrupt_num == 0); 73 assert(plat_driver_data->g1s_interrupt_array ? 74 plat_driver_data->g1s_interrupt_num : 75 plat_driver_data->g1s_interrupt_num == 0); 76 77 /* Check for system register support */ 78 #ifdef AARCH32 79 assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)); 80 #else 81 assert(read_id_aa64pfr0_el1() & 82 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)); 83 #endif /* AARCH32 */ 84 85 /* The GIC version should be 3.0 */ 86 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 87 gic_version >>= PIDR2_ARCH_REV_SHIFT; 88 gic_version &= PIDR2_ARCH_REV_MASK; 89 assert(gic_version == ARCH_REV_GICV3); 90 91 /* 92 * Find out whether the GIC supports the GICv2 compatibility mode. The 93 * ARE_S bit resets to 0 if supported 94 */ 95 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 96 gicv2_compat >>= CTLR_ARE_S_SHIFT; 97 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); 98 99 /* 100 * Find the base address of each implemented Redistributor interface. 101 * The number of interfaces should be equal to the number of CPUs in the 102 * system. The memory for saving these addresses has to be allocated by 103 * the platform port 104 */ 105 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 106 plat_driver_data->rdistif_num, 107 plat_driver_data->gicr_base, 108 plat_driver_data->mpidr_to_core_pos); 109 110 driver_data = plat_driver_data; 111 112 INFO("GICv3 %s legacy support detected." 113 " ARM GICV3 driver initialized in EL3\n", 114 gicv2_compat ? "with" : "without"); 115 } 116 117 /******************************************************************************* 118 * This function initialises the GIC distributor interface based upon the data 119 * provided by the platform while initialising the driver. 120 ******************************************************************************/ 121 void gicv3_distif_init(void) 122 { 123 assert(driver_data); 124 assert(driver_data->gicd_base); 125 assert(driver_data->g1s_interrupt_array); 126 assert(driver_data->g0_interrupt_array); 127 128 assert(IS_IN_EL3()); 129 130 /* 131 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 132 * the ARE_S bit. The Distributor might generate a system error 133 * otherwise. 134 */ 135 gicd_clr_ctlr(driver_data->gicd_base, 136 CTLR_ENABLE_G0_BIT | 137 CTLR_ENABLE_G1S_BIT | 138 CTLR_ENABLE_G1NS_BIT, 139 RWP_TRUE); 140 141 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 142 gicd_set_ctlr(driver_data->gicd_base, 143 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 144 145 /* Set the default attribute of all SPIs */ 146 gicv3_spis_configure_defaults(driver_data->gicd_base); 147 148 /* Configure the G1S SPIs */ 149 gicv3_secure_spis_configure(driver_data->gicd_base, 150 driver_data->g1s_interrupt_num, 151 driver_data->g1s_interrupt_array, 152 INTR_GROUP1S); 153 154 /* Configure the G0 SPIs */ 155 gicv3_secure_spis_configure(driver_data->gicd_base, 156 driver_data->g0_interrupt_num, 157 driver_data->g0_interrupt_array, 158 INTR_GROUP0); 159 160 /* Enable the secure SPIs now that they have been configured */ 161 gicd_set_ctlr(driver_data->gicd_base, 162 CTLR_ENABLE_G1S_BIT | CTLR_ENABLE_G0_BIT, 163 RWP_TRUE); 164 } 165 166 /******************************************************************************* 167 * This function initialises the GIC Redistributor interface of the calling CPU 168 * (identified by the 'proc_num' parameter) based upon the data provided by the 169 * platform while initialising the driver. 170 ******************************************************************************/ 171 void gicv3_rdistif_init(unsigned int proc_num) 172 { 173 uintptr_t gicr_base; 174 175 assert(driver_data); 176 assert(proc_num < driver_data->rdistif_num); 177 assert(driver_data->rdistif_base_addrs); 178 assert(driver_data->gicd_base); 179 assert(gicd_read_ctlr(driver_data->gicd_base) & CTLR_ARE_S_BIT); 180 assert(driver_data->g1s_interrupt_array); 181 assert(driver_data->g0_interrupt_array); 182 183 assert(IS_IN_EL3()); 184 185 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 186 187 /* Set the default attribute of all SGIs and PPIs */ 188 gicv3_ppi_sgi_configure_defaults(gicr_base); 189 190 /* Configure the G1S SGIs/PPIs */ 191 gicv3_secure_ppi_sgi_configure(gicr_base, 192 driver_data->g1s_interrupt_num, 193 driver_data->g1s_interrupt_array, 194 INTR_GROUP1S); 195 196 /* Configure the G0 SGIs/PPIs */ 197 gicv3_secure_ppi_sgi_configure(gicr_base, 198 driver_data->g0_interrupt_num, 199 driver_data->g0_interrupt_array, 200 INTR_GROUP0); 201 } 202 203 /******************************************************************************* 204 * This function enables the GIC CPU interface of the calling CPU using only 205 * system register accesses. 206 ******************************************************************************/ 207 void gicv3_cpuif_enable(unsigned int proc_num) 208 { 209 uintptr_t gicr_base; 210 unsigned int scr_el3; 211 unsigned int icc_sre_el3; 212 213 assert(driver_data); 214 assert(proc_num < driver_data->rdistif_num); 215 assert(driver_data->rdistif_base_addrs); 216 assert(IS_IN_EL3()); 217 218 /* Mark the connected core as awake */ 219 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 220 gicv3_rdistif_mark_core_awake(gicr_base); 221 222 /* Disable the legacy interrupt bypass */ 223 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 224 225 /* 226 * Enable system register access for EL3 and allow lower exception 227 * levels to configure the same for themselves. If the legacy mode is 228 * not supported, the SRE bit is RAO/WI 229 */ 230 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 231 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 232 233 scr_el3 = read_scr_el3(); 234 235 /* 236 * Switch to NS state to write Non secure ICC_SRE_EL1 and 237 * ICC_SRE_EL2 registers. 238 */ 239 write_scr_el3(scr_el3 | SCR_NS_BIT); 240 isb(); 241 242 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 243 write_icc_sre_el1(ICC_SRE_SRE_BIT); 244 isb(); 245 246 /* Switch to secure state. */ 247 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 248 isb(); 249 250 /* Program the idle priority in the PMR */ 251 write_icc_pmr_el1(GIC_PRI_MASK); 252 253 /* Enable Group0 interrupts */ 254 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 255 256 /* Enable Group1 Secure interrupts */ 257 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 258 IGRPEN1_EL3_ENABLE_G1S_BIT); 259 260 /* Write the secure ICC_SRE_EL1 register */ 261 write_icc_sre_el1(ICC_SRE_SRE_BIT); 262 isb(); 263 } 264 265 /******************************************************************************* 266 * This function disables the GIC CPU interface of the calling CPU using 267 * only system register accesses. 268 ******************************************************************************/ 269 void gicv3_cpuif_disable(unsigned int proc_num) 270 { 271 uintptr_t gicr_base; 272 273 assert(driver_data); 274 assert(proc_num < driver_data->rdistif_num); 275 assert(driver_data->rdistif_base_addrs); 276 277 assert(IS_IN_EL3()); 278 279 /* Disable legacy interrupt bypass */ 280 write_icc_sre_el3(read_icc_sre_el3() | 281 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 282 283 /* Disable Group0 interrupts */ 284 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 285 ~IGRPEN1_EL1_ENABLE_G0_BIT); 286 287 /* Disable Group1 Secure and Non-Secure interrupts */ 288 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 289 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 290 IGRPEN1_EL3_ENABLE_G1S_BIT)); 291 292 /* Synchronise accesses to group enable registers */ 293 isb(); 294 295 /* Mark the connected core as asleep */ 296 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 297 gicv3_rdistif_mark_core_asleep(gicr_base); 298 } 299 300 /******************************************************************************* 301 * This function returns the id of the highest priority pending interrupt at 302 * the GIC cpu interface. 303 ******************************************************************************/ 304 unsigned int gicv3_get_pending_interrupt_id(void) 305 { 306 unsigned int id; 307 308 assert(IS_IN_EL3()); 309 id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 310 311 /* 312 * If the ID is special identifier corresponding to G1S or G1NS 313 * interrupt, then read the highest pending group 1 interrupt. 314 */ 315 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) 316 return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 317 318 return id; 319 } 320 321 /******************************************************************************* 322 * This function returns the type of the highest priority pending interrupt at 323 * the GIC cpu interface. The return values can be one of the following : 324 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 325 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 326 * 0 - 1019 : The interrupt type is secure Group 0. 327 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 328 * sufficient priority to be signaled 329 ******************************************************************************/ 330 unsigned int gicv3_get_pending_interrupt_type(void) 331 { 332 assert(IS_IN_EL3()); 333 return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 334 } 335 336 /******************************************************************************* 337 * This function returns the type of the interrupt id depending upon the group 338 * this interrupt has been configured under by the interrupt controller i.e. 339 * group0 or group1 Secure / Non Secure. The return value can be one of the 340 * following : 341 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 342 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 343 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 344 * interrupt. 345 ******************************************************************************/ 346 unsigned int gicv3_get_interrupt_type(unsigned int id, 347 unsigned int proc_num) 348 { 349 unsigned int igroup, grpmodr; 350 uintptr_t gicr_base; 351 352 assert(IS_IN_EL3()); 353 assert(driver_data); 354 355 /* Ensure the parameters are valid */ 356 assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID); 357 assert(proc_num < driver_data->rdistif_num); 358 359 /* All LPI interrupts are Group 1 non secure */ 360 if (id >= MIN_LPI_ID) 361 return INTR_GROUP1NS; 362 363 if (id < MIN_SPI_ID) { 364 assert(driver_data->rdistif_base_addrs); 365 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 366 igroup = gicr_get_igroupr0(gicr_base, id); 367 grpmodr = gicr_get_igrpmodr0(gicr_base, id); 368 } else { 369 assert(driver_data->gicd_base); 370 igroup = gicd_get_igroupr(driver_data->gicd_base, id); 371 grpmodr = gicd_get_igrpmodr(driver_data->gicd_base, id); 372 } 373 374 /* 375 * If the IGROUP bit is set, then it is a Group 1 Non secure 376 * interrupt 377 */ 378 if (igroup) 379 return INTR_GROUP1NS; 380 381 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 382 if (grpmodr) 383 return INTR_GROUP1S; 384 385 /* Else it is a Group 0 Secure interrupt */ 386 return INTR_GROUP0; 387 } 388