1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gicv3.h> 12 #include <interrupt_props.h> 13 #include <spinlock.h> 14 #include "gicv3_private.h" 15 16 const gicv3_driver_data_t *gicv3_driver_data; 17 static unsigned int gicv2_compat; 18 19 /* 20 * Spinlock to guard registers needing read-modify-write. APIs protected by this 21 * spinlock are used either at boot time (when only a single CPU is active), or 22 * when the system is fully coherent. 23 */ 24 static spinlock_t gic_lock; 25 26 /* 27 * Redistributor power operations are weakly bound so that they can be 28 * overridden 29 */ 30 #pragma weak gicv3_rdistif_off 31 #pragma weak gicv3_rdistif_on 32 33 34 /* Helper macros to save and restore GICD registers to and from the context */ 35 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 36 do { \ 37 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \ 38 int_id += (1U << REG##_SHIFT)) { \ 39 gicd_write_##reg(base, int_id, \ 40 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT]); \ 41 } \ 42 } while (false) 43 44 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 45 do { \ 46 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \ 47 int_id += (1U << REG##_SHIFT)) { \ 48 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT] =\ 49 gicd_read_##reg(base, int_id); \ 50 } \ 51 } while (false) 52 53 54 /******************************************************************************* 55 * This function initialises the ARM GICv3 driver in EL3 with provided platform 56 * inputs. 57 ******************************************************************************/ 58 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 59 { 60 unsigned int gic_version; 61 62 assert(plat_driver_data != NULL); 63 assert(plat_driver_data->gicd_base != 0U); 64 assert(plat_driver_data->gicr_base != 0U); 65 assert(plat_driver_data->rdistif_num != 0U); 66 assert(plat_driver_data->rdistif_base_addrs != NULL); 67 68 assert(IS_IN_EL3()); 69 70 assert(plat_driver_data->interrupt_props_num > 0 ? 71 plat_driver_data->interrupt_props != NULL : 1); 72 73 /* Check for system register support */ 74 #ifdef AARCH32 75 assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); 76 #else 77 assert((read_id_aa64pfr0_el1() & 78 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U); 79 #endif /* AARCH32 */ 80 81 /* The GIC version should be 3.0 */ 82 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 83 gic_version >>= PIDR2_ARCH_REV_SHIFT; 84 gic_version &= PIDR2_ARCH_REV_MASK; 85 assert(gic_version == ARCH_REV_GICV3); 86 87 /* 88 * Find out whether the GIC supports the GICv2 compatibility mode. The 89 * ARE_S bit resets to 0 if supported 90 */ 91 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 92 gicv2_compat >>= CTLR_ARE_S_SHIFT; 93 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); 94 95 /* 96 * Find the base address of each implemented Redistributor interface. 97 * The number of interfaces should be equal to the number of CPUs in the 98 * system. The memory for saving these addresses has to be allocated by 99 * the platform port 100 */ 101 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 102 plat_driver_data->rdistif_num, 103 plat_driver_data->gicr_base, 104 plat_driver_data->mpidr_to_core_pos); 105 106 gicv3_driver_data = plat_driver_data; 107 108 /* 109 * The GIC driver data is initialized by the primary CPU with caches 110 * enabled. When the secondary CPU boots up, it initializes the 111 * GICC/GICR interface with the caches disabled. Hence flush the 112 * driver data to ensure coherency. This is not required if the 113 * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY 114 * enabled. 115 */ 116 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 117 flush_dcache_range((uintptr_t) &gicv3_driver_data, 118 sizeof(gicv3_driver_data)); 119 flush_dcache_range((uintptr_t) gicv3_driver_data, 120 sizeof(*gicv3_driver_data)); 121 #endif 122 123 INFO("GICv3 %s legacy support detected." 124 " ARM GICV3 driver initialized in EL3\n", 125 gicv2_compat ? "with" : "without"); 126 } 127 128 /******************************************************************************* 129 * This function initialises the GIC distributor interface based upon the data 130 * provided by the platform while initialising the driver. 131 ******************************************************************************/ 132 void gicv3_distif_init(void) 133 { 134 unsigned int bitmap = 0; 135 136 assert(gicv3_driver_data != NULL); 137 assert(gicv3_driver_data->gicd_base != 0U); 138 139 assert(IS_IN_EL3()); 140 141 /* 142 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 143 * the ARE_S bit. The Distributor might generate a system error 144 * otherwise. 145 */ 146 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 147 CTLR_ENABLE_G0_BIT | 148 CTLR_ENABLE_G1S_BIT | 149 CTLR_ENABLE_G1NS_BIT, 150 RWP_TRUE); 151 152 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 153 gicd_set_ctlr(gicv3_driver_data->gicd_base, 154 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 155 156 /* Set the default attribute of all SPIs */ 157 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); 158 159 bitmap = gicv3_secure_spis_config_props( 160 gicv3_driver_data->gicd_base, 161 gicv3_driver_data->interrupt_props, 162 gicv3_driver_data->interrupt_props_num); 163 164 /* Enable the secure SPIs now that they have been configured */ 165 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 166 } 167 168 /******************************************************************************* 169 * This function initialises the GIC Redistributor interface of the calling CPU 170 * (identified by the 'proc_num' parameter) based upon the data provided by the 171 * platform while initialising the driver. 172 ******************************************************************************/ 173 void gicv3_rdistif_init(unsigned int proc_num) 174 { 175 uintptr_t gicr_base; 176 unsigned int bitmap = 0U; 177 uint32_t ctlr; 178 179 assert(gicv3_driver_data != NULL); 180 assert(proc_num < gicv3_driver_data->rdistif_num); 181 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 182 assert(gicv3_driver_data->gicd_base != 0U); 183 184 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base); 185 assert((ctlr & CTLR_ARE_S_BIT) != 0U); 186 187 assert(IS_IN_EL3()); 188 189 /* Power on redistributor */ 190 gicv3_rdistif_on(proc_num); 191 192 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 193 194 /* Set the default attribute of all SGIs and PPIs */ 195 gicv3_ppi_sgi_config_defaults(gicr_base); 196 197 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, 198 gicv3_driver_data->interrupt_props, 199 gicv3_driver_data->interrupt_props_num); 200 201 /* Enable interrupt groups as required, if not already */ 202 if ((ctlr & bitmap) != bitmap) 203 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 204 } 205 206 /******************************************************************************* 207 * Functions to perform power operations on GIC Redistributor 208 ******************************************************************************/ 209 void gicv3_rdistif_off(unsigned int proc_num) 210 { 211 return; 212 } 213 214 void gicv3_rdistif_on(unsigned int proc_num) 215 { 216 return; 217 } 218 219 /******************************************************************************* 220 * This function enables the GIC CPU interface of the calling CPU using only 221 * system register accesses. 222 ******************************************************************************/ 223 void gicv3_cpuif_enable(unsigned int proc_num) 224 { 225 uintptr_t gicr_base; 226 unsigned int scr_el3; 227 unsigned int icc_sre_el3; 228 229 assert(gicv3_driver_data != NULL); 230 assert(proc_num < gicv3_driver_data->rdistif_num); 231 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 232 assert(IS_IN_EL3()); 233 234 /* Mark the connected core as awake */ 235 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 236 gicv3_rdistif_mark_core_awake(gicr_base); 237 238 /* Disable the legacy interrupt bypass */ 239 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 240 241 /* 242 * Enable system register access for EL3 and allow lower exception 243 * levels to configure the same for themselves. If the legacy mode is 244 * not supported, the SRE bit is RAO/WI 245 */ 246 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 247 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 248 249 scr_el3 = (uint32_t) read_scr_el3(); 250 251 /* 252 * Switch to NS state to write Non secure ICC_SRE_EL1 and 253 * ICC_SRE_EL2 registers. 254 */ 255 write_scr_el3(scr_el3 | SCR_NS_BIT); 256 isb(); 257 258 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 259 write_icc_sre_el1(ICC_SRE_SRE_BIT); 260 isb(); 261 262 /* Switch to secure state. */ 263 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 264 isb(); 265 266 /* Program the idle priority in the PMR */ 267 write_icc_pmr_el1(GIC_PRI_MASK); 268 269 /* Enable Group0 interrupts */ 270 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 271 272 /* Enable Group1 Secure interrupts */ 273 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 274 IGRPEN1_EL3_ENABLE_G1S_BIT); 275 276 /* Write the secure ICC_SRE_EL1 register */ 277 write_icc_sre_el1(ICC_SRE_SRE_BIT); 278 isb(); 279 } 280 281 /******************************************************************************* 282 * This function disables the GIC CPU interface of the calling CPU using 283 * only system register accesses. 284 ******************************************************************************/ 285 void gicv3_cpuif_disable(unsigned int proc_num) 286 { 287 uintptr_t gicr_base; 288 289 assert(gicv3_driver_data != NULL); 290 assert(proc_num < gicv3_driver_data->rdistif_num); 291 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 292 293 assert(IS_IN_EL3()); 294 295 /* Disable legacy interrupt bypass */ 296 write_icc_sre_el3(read_icc_sre_el3() | 297 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 298 299 /* Disable Group0 interrupts */ 300 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 301 ~IGRPEN1_EL1_ENABLE_G0_BIT); 302 303 /* Disable Group1 Secure and Non-Secure interrupts */ 304 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 305 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 306 IGRPEN1_EL3_ENABLE_G1S_BIT)); 307 308 /* Synchronise accesses to group enable registers */ 309 isb(); 310 311 /* Mark the connected core as asleep */ 312 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 313 gicv3_rdistif_mark_core_asleep(gicr_base); 314 } 315 316 /******************************************************************************* 317 * This function returns the id of the highest priority pending interrupt at 318 * the GIC cpu interface. 319 ******************************************************************************/ 320 unsigned int gicv3_get_pending_interrupt_id(void) 321 { 322 unsigned int id; 323 324 assert(IS_IN_EL3()); 325 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 326 327 /* 328 * If the ID is special identifier corresponding to G1S or G1NS 329 * interrupt, then read the highest pending group 1 interrupt. 330 */ 331 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) 332 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 333 334 return id; 335 } 336 337 /******************************************************************************* 338 * This function returns the type of the highest priority pending interrupt at 339 * the GIC cpu interface. The return values can be one of the following : 340 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 341 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 342 * 0 - 1019 : The interrupt type is secure Group 0. 343 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 344 * sufficient priority to be signaled 345 ******************************************************************************/ 346 unsigned int gicv3_get_pending_interrupt_type(void) 347 { 348 assert(IS_IN_EL3()); 349 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 350 } 351 352 /******************************************************************************* 353 * This function returns the type of the interrupt id depending upon the group 354 * this interrupt has been configured under by the interrupt controller i.e. 355 * group0 or group1 Secure / Non Secure. The return value can be one of the 356 * following : 357 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 358 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 359 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 360 * interrupt. 361 ******************************************************************************/ 362 unsigned int gicv3_get_interrupt_type(unsigned int id, 363 unsigned int proc_num) 364 { 365 unsigned int igroup, grpmodr; 366 uintptr_t gicr_base; 367 368 assert(IS_IN_EL3()); 369 assert(gicv3_driver_data != NULL); 370 371 /* Ensure the parameters are valid */ 372 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID)); 373 assert(proc_num < gicv3_driver_data->rdistif_num); 374 375 /* All LPI interrupts are Group 1 non secure */ 376 if (id >= MIN_LPI_ID) 377 return INTR_GROUP1NS; 378 379 if (id < MIN_SPI_ID) { 380 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 381 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 382 igroup = gicr_get_igroupr0(gicr_base, id); 383 grpmodr = gicr_get_igrpmodr0(gicr_base, id); 384 } else { 385 assert(gicv3_driver_data->gicd_base != 0U); 386 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id); 387 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id); 388 } 389 390 /* 391 * If the IGROUP bit is set, then it is a Group 1 Non secure 392 * interrupt 393 */ 394 if (igroup != 0U) 395 return INTR_GROUP1NS; 396 397 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 398 if (grpmodr != 0U) 399 return INTR_GROUP1S; 400 401 /* Else it is a Group 0 Secure interrupt */ 402 return INTR_GROUP0; 403 } 404 405 /***************************************************************************** 406 * Function to save and disable the GIC ITS register context. The power 407 * management of GIC ITS is implementation-defined and this function doesn't 408 * save any memory structures required to support ITS. As the sequence to save 409 * this state is implementation defined, it should be executed in platform 410 * specific code. Calling this function alone and then powering down the GIC and 411 * ITS without implementing the aforementioned platform specific code will 412 * corrupt the ITS state. 413 * 414 * This function must be invoked after the GIC CPU interface is disabled. 415 *****************************************************************************/ 416 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx) 417 { 418 unsigned int i; 419 420 assert(gicv3_driver_data != NULL); 421 assert(IS_IN_EL3()); 422 assert(its_ctx != NULL); 423 assert(gits_base != 0U); 424 425 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 426 427 /* Disable the ITS */ 428 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & 429 (~GITS_CTLR_ENABLED_BIT)); 430 431 /* Wait for quiescent state */ 432 gits_wait_for_quiescent_bit(gits_base); 433 434 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 435 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 436 437 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++) 438 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 439 } 440 441 /***************************************************************************** 442 * Function to restore the GIC ITS register context. The power 443 * management of GIC ITS is implementation defined and this function doesn't 444 * restore any memory structures required to support ITS. The assumption is 445 * that these structures are in memory and are retained during system suspend. 446 * 447 * This must be invoked before the GIC CPU interface is enabled. 448 *****************************************************************************/ 449 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx) 450 { 451 unsigned int i; 452 453 assert(gicv3_driver_data != NULL); 454 assert(IS_IN_EL3()); 455 assert(its_ctx != NULL); 456 assert(gits_base != 0U); 457 458 /* Assert that the GITS is disabled and quiescent */ 459 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 460 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U); 461 462 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 463 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 464 465 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++) 466 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 467 468 /* Restore the ITS CTLR but leave the ITS disabled */ 469 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & 470 (~GITS_CTLR_ENABLED_BIT)); 471 } 472 473 /***************************************************************************** 474 * Function to save the GIC Redistributor register context. This function 475 * must be invoked after CPU interface disable and prior to Distributor save. 476 *****************************************************************************/ 477 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx) 478 { 479 uintptr_t gicr_base; 480 unsigned int int_id; 481 482 assert(gicv3_driver_data != NULL); 483 assert(proc_num < gicv3_driver_data->rdistif_num); 484 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 485 assert(IS_IN_EL3()); 486 assert(rdist_ctx != NULL); 487 488 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 489 490 /* 491 * Wait for any write to GICR_CTLR to complete before trying to save any 492 * state. 493 */ 494 gicr_wait_for_pending_write(gicr_base); 495 496 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 497 498 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 499 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 500 501 rdist_ctx->gicr_igroupr0 = gicr_read_igroupr0(gicr_base); 502 rdist_ctx->gicr_isenabler0 = gicr_read_isenabler0(gicr_base); 503 rdist_ctx->gicr_ispendr0 = gicr_read_ispendr0(gicr_base); 504 rdist_ctx->gicr_isactiver0 = gicr_read_isactiver0(gicr_base); 505 rdist_ctx->gicr_icfgr0 = gicr_read_icfgr0(gicr_base); 506 rdist_ctx->gicr_icfgr1 = gicr_read_icfgr1(gicr_base); 507 rdist_ctx->gicr_igrpmodr0 = gicr_read_igrpmodr0(gicr_base); 508 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 509 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 510 int_id += (1U << IPRIORITYR_SHIFT)) { 511 rdist_ctx->gicr_ipriorityr[(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT] = 512 gicr_read_ipriorityr(gicr_base, int_id); 513 } 514 515 516 /* 517 * Call the pre-save hook that implements the IMP DEF sequence that may 518 * be required on some GIC implementations. As this may need to access 519 * the Redistributor registers, we pass it proc_num. 520 */ 521 gicv3_distif_pre_save(proc_num); 522 } 523 524 /***************************************************************************** 525 * Function to restore the GIC Redistributor register context. We disable 526 * LPI and per-cpu interrupts before we start restore of the Redistributor. 527 * This function must be invoked after Distributor restore but prior to 528 * CPU interface enable. The pending and active interrupts are restored 529 * after the interrupts are fully configured and enabled. 530 *****************************************************************************/ 531 void gicv3_rdistif_init_restore(unsigned int proc_num, 532 const gicv3_redist_ctx_t * const rdist_ctx) 533 { 534 uintptr_t gicr_base; 535 unsigned int int_id; 536 537 assert(gicv3_driver_data != NULL); 538 assert(proc_num < gicv3_driver_data->rdistif_num); 539 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 540 assert(IS_IN_EL3()); 541 assert(rdist_ctx != NULL); 542 543 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 544 545 /* Power on redistributor */ 546 gicv3_rdistif_on(proc_num); 547 548 /* 549 * Call the post-restore hook that implements the IMP DEF sequence that 550 * may be required on some GIC implementations. As this may need to 551 * access the Redistributor registers, we pass it proc_num. 552 */ 553 gicv3_distif_post_restore(proc_num); 554 555 /* 556 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a 557 * more scalable approach as it avoids clearing the enable bits in the 558 * GICD_CTLR 559 */ 560 gicr_write_icenabler0(gicr_base, ~0U); 561 /* Wait for pending writes to GICR_ICENABLER */ 562 gicr_wait_for_pending_write(gicr_base); 563 564 /* 565 * Disable the LPIs to avoid unpredictable behavior when writing to 566 * GICR_PROPBASER and GICR_PENDBASER. 567 */ 568 gicr_write_ctlr(gicr_base, 569 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 570 571 /* Restore registers' content */ 572 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 573 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 574 575 gicr_write_igroupr0(gicr_base, rdist_ctx->gicr_igroupr0); 576 577 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 578 int_id += (1U << IPRIORITYR_SHIFT)) { 579 gicr_write_ipriorityr(gicr_base, int_id, 580 rdist_ctx->gicr_ipriorityr[ 581 (int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT]); 582 } 583 584 gicr_write_icfgr0(gicr_base, rdist_ctx->gicr_icfgr0); 585 gicr_write_icfgr1(gicr_base, rdist_ctx->gicr_icfgr1); 586 gicr_write_igrpmodr0(gicr_base, rdist_ctx->gicr_igrpmodr0); 587 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 588 589 /* Restore after group and priorities are set */ 590 gicr_write_ispendr0(gicr_base, rdist_ctx->gicr_ispendr0); 591 gicr_write_isactiver0(gicr_base, rdist_ctx->gicr_isactiver0); 592 593 /* 594 * Wait for all writes to the Distributor to complete before enabling 595 * the SGI and PPIs. 596 */ 597 gicr_wait_for_upstream_pending_write(gicr_base); 598 gicr_write_isenabler0(gicr_base, rdist_ctx->gicr_isenabler0); 599 600 /* 601 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 602 * the first write to GICR_CTLR was still in flight (this write only 603 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 604 * bit). 605 */ 606 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 607 gicr_wait_for_pending_write(gicr_base); 608 } 609 610 /***************************************************************************** 611 * Function to save the GIC Distributor register context. This function 612 * must be invoked after CPU interface disable and Redistributor save. 613 *****************************************************************************/ 614 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 615 { 616 unsigned int num_ints; 617 618 assert(gicv3_driver_data != NULL); 619 assert(gicv3_driver_data->gicd_base != 0U); 620 assert(IS_IN_EL3()); 621 assert(dist_ctx != NULL); 622 623 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 624 625 num_ints = gicd_read_typer(gicd_base); 626 num_ints &= TYPER_IT_LINES_NO_MASK; 627 num_ints = (num_ints + 1U) << 5; 628 629 assert(num_ints <= (MAX_SPI_ID + 1U)); 630 631 /* Wait for pending write to complete */ 632 gicd_wait_for_pending_write(gicd_base); 633 634 /* Save the GICD_CTLR */ 635 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 636 637 /* Save GICD_IGROUPR for INTIDs 32 - 1020 */ 638 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 639 640 /* Save GICD_ISENABLER for INT_IDs 32 - 1020 */ 641 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 642 643 /* Save GICD_ISPENDR for INTIDs 32 - 1020 */ 644 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 645 646 /* Save GICD_ISACTIVER for INTIDs 32 - 1020 */ 647 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 648 649 /* Save GICD_IPRIORITYR for INTIDs 32 - 1020 */ 650 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 651 652 /* Save GICD_ICFGR for INTIDs 32 - 1020 */ 653 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 654 655 /* Save GICD_IGRPMODR for INTIDs 32 - 1020 */ 656 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 657 658 /* Save GICD_NSACR for INTIDs 32 - 1020 */ 659 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 660 661 /* Save GICD_IROUTER for INTIDs 32 - 1024 */ 662 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 663 664 /* 665 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 666 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 667 * driver. 668 */ 669 } 670 671 /***************************************************************************** 672 * Function to restore the GIC Distributor register context. We disable G0, G1S 673 * and G1NS interrupt groups before we start restore of the Distributor. This 674 * function must be invoked prior to Redistributor restore and CPU interface 675 * enable. The pending and active interrupts are restored after the interrupts 676 * are fully configured and enabled. 677 *****************************************************************************/ 678 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 679 { 680 unsigned int num_ints = 0U; 681 682 assert(gicv3_driver_data != NULL); 683 assert(gicv3_driver_data->gicd_base != 0U); 684 assert(IS_IN_EL3()); 685 assert(dist_ctx != NULL); 686 687 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 688 689 /* 690 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 691 * the ARE_S bit. The Distributor might generate a system error 692 * otherwise. 693 */ 694 gicd_clr_ctlr(gicd_base, 695 CTLR_ENABLE_G0_BIT | 696 CTLR_ENABLE_G1S_BIT | 697 CTLR_ENABLE_G1NS_BIT, 698 RWP_TRUE); 699 700 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 701 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 702 703 num_ints = gicd_read_typer(gicd_base); 704 num_ints &= TYPER_IT_LINES_NO_MASK; 705 num_ints = (num_ints + 1U) << 5; 706 707 assert(num_ints <= (MAX_SPI_ID + 1U)); 708 709 /* Restore GICD_IGROUPR for INTIDs 32 - 1020 */ 710 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 711 712 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1020 */ 713 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 714 715 /* Restore GICD_ICFGR for INTIDs 32 - 1020 */ 716 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 717 718 /* Restore GICD_IGRPMODR for INTIDs 32 - 1020 */ 719 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 720 721 /* Restore GICD_NSACR for INTIDs 32 - 1020 */ 722 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 723 724 /* Restore GICD_IROUTER for INTIDs 32 - 1020 */ 725 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 726 727 /* 728 * Restore ISENABLER, ISPENDR and ISACTIVER after the interrupts are 729 * configured. 730 */ 731 732 /* Restore GICD_ISENABLER for INT_IDs 32 - 1020 */ 733 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 734 735 /* Restore GICD_ISPENDR for INTIDs 32 - 1020 */ 736 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 737 738 /* Restore GICD_ISACTIVER for INTIDs 32 - 1020 */ 739 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 740 741 /* Restore the GICD_CTLR */ 742 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 743 gicd_wait_for_pending_write(gicd_base); 744 745 } 746 747 /******************************************************************************* 748 * This function gets the priority of the interrupt the processor is currently 749 * servicing. 750 ******************************************************************************/ 751 unsigned int gicv3_get_running_priority(void) 752 { 753 return (unsigned int)read_icc_rpr_el1(); 754 } 755 756 /******************************************************************************* 757 * This function checks if the interrupt identified by id is active (whether the 758 * state is either active, or active and pending). The proc_num is used if the 759 * interrupt is SGI or PPI and programs the corresponding Redistributor 760 * interface. 761 ******************************************************************************/ 762 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) 763 { 764 unsigned int value; 765 766 assert(gicv3_driver_data != NULL); 767 assert(gicv3_driver_data->gicd_base != 0U); 768 assert(proc_num < gicv3_driver_data->rdistif_num); 769 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 770 assert(id <= MAX_SPI_ID); 771 772 if (id < MIN_SPI_ID) { 773 /* For SGIs and PPIs */ 774 value = gicr_get_isactiver0( 775 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 776 } else { 777 value = gicd_get_isactiver(gicv3_driver_data->gicd_base, id); 778 } 779 780 return value; 781 } 782 783 /******************************************************************************* 784 * This function enables the interrupt identified by id. The proc_num 785 * is used if the interrupt is SGI or PPI, and programs the corresponding 786 * Redistributor interface. 787 ******************************************************************************/ 788 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) 789 { 790 assert(gicv3_driver_data != NULL); 791 assert(gicv3_driver_data->gicd_base != 0U); 792 assert(proc_num < gicv3_driver_data->rdistif_num); 793 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 794 assert(id <= MAX_SPI_ID); 795 796 /* 797 * Ensure that any shared variable updates depending on out of band 798 * interrupt trigger are observed before enabling interrupt. 799 */ 800 dsbishst(); 801 if (id < MIN_SPI_ID) { 802 /* For SGIs and PPIs */ 803 gicr_set_isenabler0( 804 gicv3_driver_data->rdistif_base_addrs[proc_num], 805 id); 806 } else { 807 gicd_set_isenabler(gicv3_driver_data->gicd_base, id); 808 } 809 } 810 811 /******************************************************************************* 812 * This function disables the interrupt identified by id. The proc_num 813 * is used if the interrupt is SGI or PPI, and programs the corresponding 814 * Redistributor interface. 815 ******************************************************************************/ 816 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) 817 { 818 assert(gicv3_driver_data != NULL); 819 assert(gicv3_driver_data->gicd_base != 0U); 820 assert(proc_num < gicv3_driver_data->rdistif_num); 821 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 822 assert(id <= MAX_SPI_ID); 823 824 /* 825 * Disable interrupt, and ensure that any shared variable updates 826 * depending on out of band interrupt trigger are observed afterwards. 827 */ 828 if (id < MIN_SPI_ID) { 829 /* For SGIs and PPIs */ 830 gicr_set_icenabler0( 831 gicv3_driver_data->rdistif_base_addrs[proc_num], 832 id); 833 834 /* Write to clear enable requires waiting for pending writes */ 835 gicr_wait_for_pending_write( 836 gicv3_driver_data->rdistif_base_addrs[proc_num]); 837 } else { 838 gicd_set_icenabler(gicv3_driver_data->gicd_base, id); 839 840 /* Write to clear enable requires waiting for pending writes */ 841 gicd_wait_for_pending_write(gicv3_driver_data->gicd_base); 842 } 843 844 dsbishst(); 845 } 846 847 /******************************************************************************* 848 * This function sets the interrupt priority as supplied for the given interrupt 849 * id. 850 ******************************************************************************/ 851 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 852 unsigned int priority) 853 { 854 uintptr_t gicr_base; 855 856 assert(gicv3_driver_data != NULL); 857 assert(gicv3_driver_data->gicd_base != 0U); 858 assert(proc_num < gicv3_driver_data->rdistif_num); 859 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 860 assert(id <= MAX_SPI_ID); 861 862 if (id < MIN_SPI_ID) { 863 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 864 gicr_set_ipriorityr(gicr_base, id, priority); 865 } else { 866 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority); 867 } 868 } 869 870 /******************************************************************************* 871 * This function assigns group for the interrupt identified by id. The proc_num 872 * is used if the interrupt is SGI or PPI, and programs the corresponding 873 * Redistributor interface. The group can be any of GICV3_INTR_GROUP* 874 ******************************************************************************/ 875 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 876 unsigned int type) 877 { 878 bool igroup = false, grpmod = false; 879 uintptr_t gicr_base; 880 881 assert(gicv3_driver_data != NULL); 882 assert(gicv3_driver_data->gicd_base != 0U); 883 assert(proc_num < gicv3_driver_data->rdistif_num); 884 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 885 886 switch (type) { 887 case INTR_GROUP1S: 888 igroup = false; 889 grpmod = true; 890 break; 891 case INTR_GROUP0: 892 igroup = false; 893 grpmod = false; 894 break; 895 case INTR_GROUP1NS: 896 igroup = true; 897 grpmod = false; 898 break; 899 default: 900 assert(false); 901 break; 902 } 903 904 if (id < MIN_SPI_ID) { 905 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 906 if (igroup) 907 gicr_set_igroupr0(gicr_base, id); 908 else 909 gicr_clr_igroupr0(gicr_base, id); 910 911 if (grpmod) 912 gicr_set_igrpmodr0(gicr_base, id); 913 else 914 gicr_clr_igrpmodr0(gicr_base, id); 915 } else { 916 /* Serialize read-modify-write to Distributor registers */ 917 spin_lock(&gic_lock); 918 if (igroup) 919 gicd_set_igroupr(gicv3_driver_data->gicd_base, id); 920 else 921 gicd_clr_igroupr(gicv3_driver_data->gicd_base, id); 922 923 if (grpmod) 924 gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id); 925 else 926 gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id); 927 spin_unlock(&gic_lock); 928 } 929 } 930 931 /******************************************************************************* 932 * This function raises the specified Secure Group 0 SGI. 933 * 934 * The target parameter must be a valid MPIDR in the system. 935 ******************************************************************************/ 936 void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target) 937 { 938 unsigned int tgt, aff3, aff2, aff1, aff0; 939 uint64_t sgi_val; 940 941 /* Verify interrupt number is in the SGI range */ 942 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID)); 943 944 /* Extract affinity fields from target */ 945 aff0 = MPIDR_AFFLVL0_VAL(target); 946 aff1 = MPIDR_AFFLVL1_VAL(target); 947 aff2 = MPIDR_AFFLVL2_VAL(target); 948 aff3 = MPIDR_AFFLVL3_VAL(target); 949 950 /* 951 * Make target list from affinity 0, and ensure GICv3 SGI can target 952 * this PE. 953 */ 954 assert(aff0 < GICV3_MAX_SGI_TARGETS); 955 tgt = BIT_32(aff0); 956 957 /* Raise SGI to PE specified by its affinity */ 958 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF, 959 tgt); 960 961 /* 962 * Ensure that any shared variable updates depending on out of band 963 * interrupt trigger are observed before raising SGI. 964 */ 965 dsbishst(); 966 write_icc_sgi0r_el1(sgi_val); 967 isb(); 968 } 969 970 /******************************************************************************* 971 * This function sets the interrupt routing for the given SPI interrupt id. 972 * The interrupt routing is specified in routing mode and mpidr. 973 * 974 * The routing mode can be either of: 975 * - GICV3_IRM_ANY 976 * - GICV3_IRM_PE 977 * 978 * The mpidr is the affinity of the PE to which the interrupt will be routed, 979 * and is ignored for routing mode GICV3_IRM_ANY. 980 ******************************************************************************/ 981 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr) 982 { 983 unsigned long long aff; 984 uint64_t router; 985 986 assert(gicv3_driver_data != NULL); 987 assert(gicv3_driver_data->gicd_base != 0U); 988 989 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE)); 990 assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID)); 991 992 aff = gicd_irouter_val_from_mpidr(mpidr, irm); 993 gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff); 994 995 /* 996 * In implementations that do not require 1 of N distribution of SPIs, 997 * IRM might be RAZ/WI. Read back and verify IRM bit. 998 */ 999 if (irm == GICV3_IRM_ANY) { 1000 router = gicd_read_irouter(gicv3_driver_data->gicd_base, id); 1001 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) { 1002 ERROR("GICv3 implementation doesn't support routing ANY\n"); 1003 panic(); 1004 } 1005 } 1006 } 1007 1008 /******************************************************************************* 1009 * This function clears the pending status of an interrupt identified by id. 1010 * The proc_num is used if the interrupt is SGI or PPI, and programs the 1011 * corresponding Redistributor interface. 1012 ******************************************************************************/ 1013 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num) 1014 { 1015 assert(gicv3_driver_data != NULL); 1016 assert(gicv3_driver_data->gicd_base != 0U); 1017 assert(proc_num < gicv3_driver_data->rdistif_num); 1018 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1019 1020 /* 1021 * Clear pending interrupt, and ensure that any shared variable updates 1022 * depending on out of band interrupt trigger are observed afterwards. 1023 */ 1024 if (id < MIN_SPI_ID) { 1025 /* For SGIs and PPIs */ 1026 gicr_set_icpendr0(gicv3_driver_data->rdistif_base_addrs[proc_num], 1027 id); 1028 } else { 1029 gicd_set_icpendr(gicv3_driver_data->gicd_base, id); 1030 } 1031 dsbishst(); 1032 } 1033 1034 /******************************************************************************* 1035 * This function sets the pending status of an interrupt identified by id. 1036 * The proc_num is used if the interrupt is SGI or PPI and programs the 1037 * corresponding Redistributor interface. 1038 ******************************************************************************/ 1039 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num) 1040 { 1041 assert(gicv3_driver_data != NULL); 1042 assert(gicv3_driver_data->gicd_base != 0U); 1043 assert(proc_num < gicv3_driver_data->rdistif_num); 1044 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1045 1046 /* 1047 * Ensure that any shared variable updates depending on out of band 1048 * interrupt trigger are observed before setting interrupt pending. 1049 */ 1050 dsbishst(); 1051 if (id < MIN_SPI_ID) { 1052 /* For SGIs and PPIs */ 1053 gicr_set_ispendr0(gicv3_driver_data->rdistif_base_addrs[proc_num], 1054 id); 1055 } else { 1056 gicd_set_ispendr(gicv3_driver_data->gicd_base, id); 1057 } 1058 } 1059 1060 /******************************************************************************* 1061 * This function sets the PMR register with the supplied value. Returns the 1062 * original PMR. 1063 ******************************************************************************/ 1064 unsigned int gicv3_set_pmr(unsigned int mask) 1065 { 1066 unsigned int old_mask; 1067 1068 old_mask = (uint32_t) read_icc_pmr_el1(); 1069 1070 /* 1071 * Order memory updates w.r.t. PMR write, and ensure they're visible 1072 * before potential out of band interrupt trigger because of PMR update. 1073 * PMR system register writes are self-synchronizing, so no ISB required 1074 * thereafter. 1075 */ 1076 dsbishst(); 1077 write_icc_pmr_el1(mask); 1078 1079 return old_mask; 1080 } 1081