1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <platform_def.h> 9 10 #include <common/debug.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/arm/gic.h> 13 #include <drivers/arm/gicv3.h> 14 #include <lib/utils.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/common/platform.h> 17 18 #if USE_GIC_DRIVER != 3 19 #error "This file should only be used with USE_GIC_DRIVER=3" 20 #endif 21 22 /* The GICv3 driver only needs to be initialized in EL3 */ 23 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 24 25 /* Default GICR base address to be used for GICR probe. */ 26 static const uintptr_t gicr_base_addrs[2] = { 27 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */ 28 0U /* Zero Termination */ 29 }; 30 31 /* List of zero terminated GICR frame addresses which CPUs will probe */ 32 static const uintptr_t *gicr_frames = gicr_base_addrs; 33 34 static const interrupt_prop_t arm_interrupt_props[] = { 35 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S), 36 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0), 37 #if ENABLE_FEAT_RAS && FFH_SUPPORT 38 INTR_PROP_DESC(PLAT_CORE_FAULT_IRQ, PLAT_RAS_PRI, INTR_GROUP0, 39 GIC_INTR_CFG_LEVEL) 40 #endif 41 }; 42 43 /* 44 * We save and restore the GICv3 context on system suspend. Allocate the 45 * data in the designated EL3 Secure carve-out memory. The `used` attribute 46 * is used to prevent the compiler from removing the gicv3 contexts. 47 */ 48 static gicv3_redist_ctx_t rdist_ctx __section(".arm_el3_tzc_dram") __used; 49 static gicv3_dist_ctx_t dist_ctx __section(".arm_el3_tzc_dram") __used; 50 51 /* Define accessor function to get reference to the GICv3 context */ 52 DEFINE_LOAD_SYM_ADDR(rdist_ctx) 53 DEFINE_LOAD_SYM_ADDR(dist_ctx) 54 55 /* 56 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register 57 * to core position. 58 * 59 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity 60 * values read from GICR_TYPER don't have an MT field. To reuse the same 61 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into 62 * that read from GICR_TYPER. 63 * 64 * Assumptions: 65 * 66 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set; 67 * - No CPUs implemented in the system use affinity level 3. 68 */ 69 static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr) 70 { 71 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); 72 return plat_arm_calc_core_pos(mpidr); 73 } 74 75 gicv3_driver_data_t gic_data __unused = { 76 .gicd_base = PLAT_ARM_GICD_BASE, 77 .gicr_base = 0U, 78 .interrupt_props = arm_interrupt_props, 79 .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props), 80 .rdistif_num = PLATFORM_CORE_COUNT, 81 .rdistif_base_addrs = rdistif_base_addrs, 82 .mpidr_to_core_pos = arm_gicv3_mpidr_hash 83 }; 84 85 /* 86 * By default, gicr_frames will be pointing to gicr_base_addrs. If 87 * the platform supports a non-contiguous GICR frames (GICR frames located 88 * at uneven offset), plat_arm_override_gicr_frames function can be used by 89 * such platform to override the gicr_frames. 90 */ 91 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames) 92 { 93 assert(plat_gicr_frames != NULL); 94 gicr_frames = plat_gicr_frames; 95 } 96 97 /****************************************************************************** 98 * ARM common helper to initialize the GIC. Only invoked by BL31 99 *****************************************************************************/ 100 void __init gic_init(unsigned int cpu_idx) 101 { 102 gicv3_driver_init(&gic_data); 103 gicv3_distif_init(); 104 } 105 106 /****************************************************************************** 107 * ARM common helper to enable the GIC CPU interface 108 *****************************************************************************/ 109 void gic_cpuif_enable(unsigned int cpu_idx) 110 { 111 gicv3_cpuif_enable(cpu_idx); 112 } 113 114 /****************************************************************************** 115 * ARM common helper to disable the GIC CPU interface 116 *****************************************************************************/ 117 void gic_cpuif_disable(unsigned int cpu_idx) 118 { 119 gicv3_cpuif_disable(cpu_idx); 120 } 121 122 /****************************************************************************** 123 * ARM common helper function to iterate over all GICR frames and discover the 124 * corresponding per-cpu redistributor frame as well as initialize the 125 * corresponding interface in GICv3. 126 *****************************************************************************/ 127 void gic_pcpu_init(unsigned int cpu_idx) 128 { 129 int result; 130 const uintptr_t *plat_gicr_frames = gicr_frames; 131 132 do { 133 result = gicv3_rdistif_probe(*plat_gicr_frames); 134 135 /* If the probe is successful, no need to proceed further */ 136 if (result == 0) 137 break; 138 139 plat_gicr_frames++; 140 } while (*plat_gicr_frames != 0U); 141 142 if (result == -1) { 143 ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr()); 144 panic(); 145 } 146 gicv3_rdistif_init(cpu_idx); 147 } 148 149 /****************************************************************************** 150 * ARM common helpers to power GIC redistributor interface 151 *****************************************************************************/ 152 void gic_pcpu_off(unsigned int cpu_idx) 153 { 154 gicv3_rdistif_off(cpu_idx); 155 } 156 157 /****************************************************************************** 158 * Common helper to save & restore the GICv3 on resume from system suspend. It 159 * is the platform's responsibility to call these. 160 *****************************************************************************/ 161 void gic_save(void) 162 { 163 gicv3_redist_ctx_t * const rdist_context = 164 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx); 165 gicv3_dist_ctx_t * const dist_context = 166 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx); 167 168 /* 169 * If an ITS is available, save its context before 170 * the Redistributor using: 171 * gicv3_its_save_disable(gits_base, &its_ctx[i]) 172 * Additionally, an implementation-defined sequence may 173 * be required to save the whole ITS state. 174 */ 175 176 /* 177 * Save the GIC Redistributors and ITS contexts before the 178 * Distributor context. As we only handle SYSTEM SUSPEND API, 179 * we only need to save the context of the CPU that is issuing 180 * the SYSTEM SUSPEND call, i.e. the current CPU. 181 */ 182 gicv3_rdistif_save(plat_my_core_pos(), rdist_context); 183 184 /* Save the GIC Distributor context */ 185 gicv3_distif_save(dist_context); 186 187 /* 188 * From here, all the components of the GIC can be safely powered down 189 * as long as there is an alternate way to handle wakeup interrupt 190 * sources. 191 */ 192 } 193 194 void gic_resume(void) 195 { 196 const gicv3_redist_ctx_t *rdist_context = 197 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx); 198 const gicv3_dist_ctx_t *dist_context = 199 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx); 200 201 /* Restore the GIC Distributor context */ 202 gicv3_distif_init_restore(dist_context); 203 204 /* 205 * Restore the GIC Redistributor and ITS contexts after the 206 * Distributor context. As we only handle SYSTEM SUSPEND API, 207 * we only need to restore the context of the CPU that issued 208 * the SYSTEM SUSPEND call. 209 */ 210 gicv3_rdistif_init_restore(plat_my_core_pos(), rdist_context); 211 212 /* 213 * If an ITS is available, restore its context after 214 * the Redistributor using: 215 * gicv3_its_restore(gits_base, &its_ctx[i]) 216 * An implementation-defined sequence may be required to 217 * restore the whole ITS state. The ITS must also be 218 * re-enabled after this sequence has been executed. 219 */ 220 } 221