1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <platform_def.h> 9 10 #include <common/debug.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/arm/gic.h> 13 #include <drivers/arm/gicv3.h> 14 #include <lib/utils.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/common/platform.h> 17 18 #if USE_GIC_DRIVER != 3 19 #error "This file should only be used with USE_GIC_DRIVER=3" 20 #endif 21 22 /* The GICv3 driver only needs to be initialized in EL3 */ 23 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 24 25 /* List of zero terminated GICR frame addresses which CPUs will probe */ 26 static const uintptr_t *gicr_frames = NULL; 27 28 static const interrupt_prop_t arm_interrupt_props[] = { 29 #ifdef PLAT_ARM_G1S_IRQ_PROPS 30 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S), 31 #endif 32 #ifdef PLAT_ARM_G0_IRQ_PROPS 33 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0), 34 #endif 35 #if ENABLE_FEAT_RAS && FFH_SUPPORT 36 INTR_PROP_DESC(PLAT_CORE_FAULT_IRQ, PLAT_RAS_PRI, INTR_GROUP0, 37 GIC_INTR_CFG_LEVEL) 38 #endif 39 }; 40 41 /* 42 * We save and restore the GICv3 context on system suspend. Allocate the 43 * data in the designated EL3 Secure carve-out memory. The `used` attribute 44 * is used to prevent the compiler from removing the gicv3 contexts. 45 */ 46 static gicv3_redist_ctx_t rdist_ctx __section(".arm_el3_tzc_dram") __used; 47 static gicv3_dist_ctx_t dist_ctx __section(".arm_el3_tzc_dram") __used; 48 49 /* Define accessor function to get reference to the GICv3 context */ 50 DEFINE_LOAD_SYM_ADDR(rdist_ctx) 51 DEFINE_LOAD_SYM_ADDR(dist_ctx) 52 53 /* 54 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register 55 * to core position. 56 * 57 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity 58 * values read from GICR_TYPER don't have an MT field. To reuse the same 59 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into 60 * that read from GICR_TYPER. 61 * 62 * Assumptions: 63 * 64 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set; 65 * - No CPUs implemented in the system use affinity level 3. 66 */ 67 static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr) 68 { 69 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); 70 return plat_arm_calc_core_pos(mpidr); 71 } 72 73 gicv3_driver_data_t gic_data __unused = { 74 .gicd_base = PLAT_ARM_GICD_BASE, 75 /* unused for USE_GIC_DRIVER=3. Use gic_set_gicr_frames(), passing a ptr 76 * to an array with 2 values - the frame's base and a NULL pointer */ 77 .gicr_base = 0U, 78 .interrupt_props = arm_interrupt_props, 79 .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props), 80 .rdistif_num = PLATFORM_CORE_COUNT, 81 .rdistif_base_addrs = rdistif_base_addrs, 82 .mpidr_to_core_pos = arm_gicv3_mpidr_hash 83 }; 84 85 /* 86 * Initialises the gicr_frames array. It contains a NULL terminated list of 87 * non-contiguous blocks of GICR frames (located at uneven offsets). Most 88 * platforms will have one such block, except multichip configurations, which 89 * will usually have multiple. 90 */ 91 void gic_set_gicr_frames(const uintptr_t *plat_gicr_frames) 92 { 93 assert(plat_gicr_frames != NULL); 94 gicr_frames = plat_gicr_frames; 95 } 96 97 /****************************************************************************** 98 * ARM common helper to initialize the GIC. Only invoked by BL31 99 *****************************************************************************/ 100 void __init gic_init(unsigned int cpu_idx) 101 { 102 gicv3_driver_init(&gic_data); 103 gicv3_distif_init(); 104 } 105 106 /****************************************************************************** 107 * ARM common helper to enable the GIC CPU interface 108 *****************************************************************************/ 109 void gic_cpuif_enable(unsigned int cpu_idx) 110 { 111 gicv3_cpuif_enable(cpu_idx); 112 } 113 114 /****************************************************************************** 115 * ARM common helper to disable the GIC CPU interface 116 *****************************************************************************/ 117 void gic_cpuif_disable(unsigned int cpu_idx) 118 { 119 gicv3_cpuif_disable(cpu_idx); 120 } 121 122 /****************************************************************************** 123 * ARM common helper function to iterate over all GICR frames and discover the 124 * corresponding per-cpu redistributor frame as well as initialize the 125 * corresponding interface in GICv3. 126 *****************************************************************************/ 127 void gic_pcpu_init(unsigned int cpu_idx) 128 { 129 /* to guard against an empty array */ 130 int result = -1; 131 132 /* did the paltform initialise the array with gic_set_gicr_frames() */ 133 assert(gicr_frames != NULL); 134 135 do { 136 result = gicv3_rdistif_probe(*gicr_frames); 137 138 /* If the probe is successful, no need to proceed further */ 139 if (result == 0) 140 break; 141 142 gicr_frames++; 143 } while (*gicr_frames != 0U); 144 145 if (result == -1) { 146 ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr()); 147 panic(); 148 } 149 gicv3_rdistif_init(cpu_idx); 150 } 151 152 /****************************************************************************** 153 * ARM common helpers to power GIC redistributor interface 154 *****************************************************************************/ 155 void gic_pcpu_off(unsigned int cpu_idx) 156 { 157 gicv3_rdistif_off(cpu_idx); 158 } 159 160 /****************************************************************************** 161 * Common helper to save & restore the GICv3 on resume from system suspend. It 162 * is the platform's responsibility to call these. 163 *****************************************************************************/ 164 void gic_save(void) 165 { 166 gicv3_redist_ctx_t * const rdist_context = 167 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx); 168 gicv3_dist_ctx_t * const dist_context = 169 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx); 170 171 /* 172 * If an ITS is available, save its context before 173 * the Redistributor using: 174 * gicv3_its_save_disable(gits_base, &its_ctx[i]) 175 * Additionally, an implementation-defined sequence may 176 * be required to save the whole ITS state. 177 */ 178 179 /* 180 * Save the GIC Redistributors and ITS contexts before the 181 * Distributor context. As we only handle SYSTEM SUSPEND API, 182 * we only need to save the context of the CPU that is issuing 183 * the SYSTEM SUSPEND call, i.e. the current CPU. 184 */ 185 gicv3_rdistif_save(plat_my_core_pos(), rdist_context); 186 187 /* Save the GIC Distributor context */ 188 gicv3_distif_save(dist_context); 189 190 /* 191 * From here, all the components of the GIC can be safely powered down 192 * as long as there is an alternate way to handle wakeup interrupt 193 * sources. 194 */ 195 } 196 197 void gic_resume(void) 198 { 199 const gicv3_redist_ctx_t *rdist_context = 200 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx); 201 const gicv3_dist_ctx_t *dist_context = 202 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx); 203 204 /* Restore the GIC Distributor context */ 205 gicv3_distif_init_restore(dist_context); 206 207 /* 208 * Restore the GIC Redistributor and ITS contexts after the 209 * Distributor context. As we only handle SYSTEM SUSPEND API, 210 * we only need to restore the context of the CPU that issued 211 * the SYSTEM SUSPEND call. 212 */ 213 gicv3_rdistif_init_restore(plat_my_core_pos(), rdist_context); 214 215 /* 216 * If an ITS is available, restore its context after 217 * the Redistributor using: 218 * gicv3_its_restore(gits_base, &its_ctx[i]) 219 * An implementation-defined sequence may be required to 220 * restore the whole ITS state. The ITS must also be 221 * re-enabled after this sequence has been executed. 222 */ 223 } 224